Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - DC/DC voltage regulator Holder SO 8

VIN

ENA

GND

VSENSE

BOOT

VIN VOUT

SimplifiedSchematic

EfficiencyvsOutputCurrent

100

I - Output Current - A

Efficiency-%

0 1 2 3 4 5 6

V =12V,

V =5V,

f =500kHz,

T =25°C

TPS5450

www.ti.com

SLVS757C –MARCH 2007–REVISED OCTOBER 2013

5-A, WIDE INPUT RANGE, STEP-DOWN CONVERTER

Check for Samples: TPS5450

FEATURES

APPLICATIONS

• Wide Input Voltage Range: 5.5 V to 36 V

• High Density Point-of-Load Regulators

• Up to 5-A Continuous (6-A Peak) Output • LCD Displays, Plasma Displays

Current

• Battery Chargers

• High Efficiency Greater than 90% Enabled by

• 12-V/24-V Distributed Power Systems

110-mΩ Integrated MOSFET Switch

• Wide Output Voltage Range: Adjustable Down DESCRIPTION

to 1.22 V with 1.5% Initial Accuracy

The TPS5450 is a high-output-current PWM

converter that integrates a low resistance high side

• Internal Compensation Minimizes External

N-channel MOSFET. Included on the substrate with

Parts Count

the listed features are a high performance voltage

• Fixed 500 kHz Switching Frequency for Small

error amplifier that provides tight voltage regulation

Filter Size

accuracy under transient conditions; an undervoltage-

• 18 μA Shut Down Supply Current

lockout circuit to prevent start-up until the input

voltage reaches 5.5 V; an internally set slow-start

• Improved Line Regulation and Transient

circuit to limit inrush currents; and a voltage feed-

Response by Input Voltage Feed Forward

forward circuit to improve the transient response.

• System Protected by Overcurrent Limiting,

Using the ENA pin, shutdown supply current is

Overvoltage Protection and Thermal Shutdown

reduced to 18 μA typically. Other features include an

active-high enable, overcurrent limiting, overvoltage

• –40°C to 125°C Operating Junction

protection and thermal shutdown. To reduce design

Temperature Range

complexity and external component count, the

• Available in Small Thermally Enhanced 8-Pin

TPS5450 feedback loop is internally compensated.

SOIC PowerPAD™ Package

The TPS5450 device is available in a thermally

enhanced, 8-pin SOIC PowerPAD™ package. TI

provides evaluation modules and software tool to aid

in achieving high-performance power supply designs

to meet aggressive equipment development cycles.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (28 pages)

PAGE 1
TPS5450 www.ti.com SLVS757C – MARCH 2007 – REVISED OCTOBER 2013 5-A, WIDE INPUT RANGE, STEP-DOWN CONVERTER Check for Samples: TPS5450 FEATURES APPLICATIONS • • • • • • 1 2 • • • • • • • • • Wide Input Voltage Range: 5.5 V to 36 V Up to 5-A Continuous (6-A Peak) Output Current High Efficiency Greater than 90% Enabled by 110-mΩ Integrated MOSFET Switch Wide Output Voltage Range: Adjustable Down to 1.22 V with 1.
PAGE 2
TPS5450 SLVS757C – MARCH 2007 – REVISED OCTOBER 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION TJ INPUT VOLTAGE OUTPUT VOLTAGE PACKAGE (1) PART NUMBER –40°C to 125°C 5.5 V to 36 V Adjustable to 1.
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TPS5450 www.ti.com SLVS757C – MARCH 2007 – REVISED OCTOBER 2013 RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT VI Input voltage range 5.5 36 V TJ Operating junction temperature –40 125 °C TYP MAX UNIT 3 4.4 mA 18 50 μA Start threshold voltage, UVLO 5.3 5.5 Hysteresis voltage, UVLO 330 ELECTRICAL CHARACTERISTICS TJ = –40°C to 125°C, VIN = 5.
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TPS5450 SLVS757C – MARCH 2007 – REVISED OCTOBER 2013 www.ti.com PIN ASSIGNMENTS DDA PACKAGE (TOP VIEW) 8 PH 7 VIN 3 6 GND 4 5 ENA BOOT 1 NC 2 NC VSENSE PowerPAD (Pin 9) TERMINAL FUNCTIONS TERMINAL NAME DESCRIPTION NO. BOOT 1 NC 2, 3 Boost capacitor for the high-side FET gate driver. Connect 0.01 μF low ESR capacitor from BOOT pin to PH pin. Not connected internally. VSENSE 4 Feedback voltage for the regulator. Connect to output voltage divider. ENA 5 On/off control. Below 0.
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TPS5450 www.ti.com SLVS757C – MARCH 2007 – REVISED OCTOBER 2013 TYPICAL CHARACTERISTICS OSCILLATOR FREQUENCY vs JUNCTION TEMPERATURE NON-SWITCHING QUIESCENT CURRENT vs JUNCTION TEMPERATURE 530 3.5 VI = 12 V I Q−Quiescent Current −mA f − Oscillator Frequency − kHz 520 510 500 490 480 3.25 3 2.75 470 460 −50 −25 0 25 50 75 100 2.5 −50 125 −25 50 75 100 Figure 2.
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TPS5450 SLVS757C – MARCH 2007 – REVISED OCTOBER 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) MINIMUM CONTROLLABLE ON TIME vs JUNCTION TEMPERATURE MINIMUM CONTROLLABLE DUTY RATIO vs JUNCTION TEMPERATURE 8 170 7.75 Minimum Duty Ratio - % Minimum Controllable On Time − ns 180 160 150 140 7.50 7.25 130 120 −50 −25 0 25 50 75 100 TJ − Junction Temperature − °C 125 Figure 7. 6 7 -50 -25 50 0 25 75 100 TJ - Junction Temperature - °C 125 Figure 8.
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TPS5450 www.ti.com SLVS757C – MARCH 2007 – REVISED OCTOBER 2013 APPLICATION INFORMATION FUNCTIONAL BLOCK DIAGRAM VIN VIN 1.221 V Bandgap Reference UVLO VREF SHDN Slow Start Boot Regulator BOOT HICCUP 5 µA ENABLE ENA SHDN SHDN VSENSE Z1 Thermal Protection SHDN NC VIN Ramp Generator NC SHDN VSENSE PWM Comparator HICCUP Overcurrent Protection Oscillator OVP Z2 Feed Forward Gain = 25 SHDN GND POWERPAD Error Amplifier SHDN SHDN Gate Drive Control 112.
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TPS5450 SLVS757C – MARCH 2007 – REVISED OCTOBER 2013 www.ti.com Undervoltage Lockout (UVLO) The TPS5450 incorporates an undervoltage lockout circuit to keep the device disabled when VIN (the input voltage) is below the UVLO start voltage threshold. During power up, internal circuits are held inactive and the internal slow start is grounded until VIN exceeds the UVLO start threshold voltage. Once the UVLO start threshold voltage is reached, the internal slow start is released and device start-up begins.
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TPS5450 www.ti.com SLVS757C – MARCH 2007 – REVISED OCTOBER 2013 Overvoltage Protection The TPS5450 has an overvoltage protection (OVP) circuit to minimize voltage overshoot when recovering from output fault conditions. The OVP circuit includes an overvoltage comparator to compare the VSENSE pin voltage and a threshold of 112.5% x VREF. Once the VSENSE pin voltage is higher than the threshold, the high-side MOSFET will be forced off.
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TPS5450 SLVS757C – MARCH 2007 – REVISED OCTOBER 2013 www.ti.com Feedback Trace OUTPUT INDUCTOR BOOT CAPACITOR BOOT RESISTOR DIVIDER EXPOSED POWERPAD AREA PH NC VIN NC GND VSENSE ENA INPUT BYPASS CAPACITOR Vout PH Vin OUTPUT FILTER CAPACITOR CATCH DIODE Route INPUT VOLTAGE trace under the catch diode and output capacitor or on another layer TOPSIDE GROUND AREA Signal VIA Figure 9. Design Layout spacer 0,45 1,27 2,15 3,10 2,49 5,75 Figure 10.
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TPS5450 www.ti.com SLVS757C – MARCH 2007 – REVISED OCTOBER 2013 Application Circuits Figure 11 shows the schematic for a typical TPS5450 application. The TPS5450 can provide up to 5-A output current at a nominal output voltage of 5 V. For proper thermal performance, the exposed PowerPAD™ underneath the device must be soldered down to the printed-circuit board. Figure 11. Application Circuit, 12-V to 5.
PAGE 12
TPS5450 SLVS757C – MARCH 2007 – REVISED OCTOBER 2013 www.ti.com Switching Frequency The switching frequency for the TPS5450 is internally set to 500 kHz. It is not possible to adjust the switching frequency. Input Capacitors The TPS5450 requires an input decoupling capacitor and, depending on the application, a bulk input capacitor. The minimum recommended decoupling capacitance is 4.7 μF. A high quality ceramic type X5R or X7R is required.
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TPS5450 www.ti.com SLVS757C – MARCH 2007 – REVISED OCTOBER 2013 For the output filter inductor it is important that the RMS current and saturation current ratings not be exceeded. The RMS inductor current can be found from Equation 5: I L(RMS) + Ǹ 1 I2 ) OUT(MAX) 12 ǒ V V OUT ǒVIN(MAX) * VOUTǓ L IN(MAX) F OUT Ǔ 2 SW(MIN) (5) and the peak inductor current can be determined with Equation 6: V I L(PK) + I OUT(MAX) ) 1.
PAGE 14
TPS5450 SLVS757C – MARCH 2007 – REVISED OCTOBER 2013 www.ti.com For this design example, a single 330-μF output capacitor is chosen for C3. The calculated RMS ripple current is 143 mA and the maximum ESR required is 40 mΩ. A capacitor that meets these requirements is a Sanyo Poscap 10TPB330M, rated at 10 V with a maximum ESR of 35 mΩ and a ripple current rating of 3 A. An additional small 0.1-μF ceramic bypass capacitor, C6 is also used in this design.
PAGE 15
TPS5450 www.ti.com SLVS757C – MARCH 2007 – REVISED OCTOBER 2013 Where VINMIN = minimum input voltage IOMAX = maximum load current VD = catch diode forward voltage. RL= output inductor series resistance. This equation assumes maximum on resistance for the internal high side FET. The lower limit is constrained by the minimum controllable on time which may be as high as 200 ns. The approximate minimum output voltage for a given input voltage and minimum load current is given by: V OUTMIN + 0.
PAGE 16
TPS5450 SLVS757C – MARCH 2007 – REVISED OCTOBER 2013 www.ti.com PERFORMANCE GRAPHS The performance graphs (Figure 12 through Figure 18) are applicable to the circuit in Figure 11. TA = 25 °C. unless otherwise specified. 0.3 100 0.2 VI = 12 V 95 Output Regulation - % Efficiency - % VI = 15 V 90 VI = 24 V 85 VI = 28 V 80 0.1 0 -0.1 -0.2 75 0 1 2 3 4 IO - Output Current - A 5 6 Figure 12. Efficiency vs. Output Current -0.3 0 0.5 1 1.5 2 2.5 3 3.5 IO - Output Current - A 4 4.
PAGE 17
TPS5450 www.ti.com SLVS757C – MARCH 2007 – REVISED OCTOBER 2013 VOUT = 50 mV/div (AC Coupled, 20 MHz BWL) VOUT = 50 mV/div (AC Coupled, 20 MHz BWL) VPH = 10 V/div IOUT = 1 A/div t - Time = 1 ms/div t - Time = 100 ms/div Figure 16. Output Voltage Ripple and PH Node, IO = 5 A Figure 17. Transient Response, IO Step 1.25 to 3.75 A. TJ - Junction Temperature - °C 125 100 75 50 25 0 0.5 1 1.5 2 2.5 IC Power Dissipation - W 3 3.5 Figure 18. TPS5450 Power Dissipation vs Junction Temperature.
PAGE 18
TPS5450 SLVS757C – MARCH 2007 – REVISED OCTOBER 2013 www.ti.com REVISION HISTORY Changes from Original (March 2007) to Revision A • Replaced the DISSIPATION RATINGS with the THERMAL INFORMATION table ............................................................. 2 Changes from Revision A (January 2013) to Revision B • 18 Page Deleted SWIFT from the data sheet Title, Features, and Description ..................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 8-Oct-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PAGE 21
PACKAGE MATERIALS INFORMATION www.ti.com 8-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS5450DDAR Package Package Pins Type Drawing SO Power PAD DDA 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 6.4 B0 (mm) K0 (mm) P1 (mm) 5.2 2.1 8.0 W Pin1 (mm) Quadrant 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 8-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS5450DDAR SO PowerPAD DDA 8 2500 367.0 367.0 35.
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