Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - DC/DC voltage regulator Holder SO 8

VIN

ENA

GND

VSENSE

BOOT

VIN VOUT

SimplifiedSchematic

EfficiencyvsOutputCurrent

100

I - Output Current - A

Efficiency-%

0 1 2 3 4 5 6

V =12V,

V =5V,

f =500kHz,

T =25°C

TPS5450-Q1

www.ti.com

SLVS834A –JULY 2008– REVISED OCTOBER 2011

5-A, WIDE INPUT RANGE, STEP-DOWN SWIFT™ CONVERTER

Check for Samples: TPS5450-Q1

FEATURES

APPLICATIONS

• Qualified for Automotive Applications

• High-Density Point-of-Load Regulators

• Wide Input Voltage Range: 5.5 V to 36 V • LCD Displays, Plasma Displays

• Up to 5-A Continuous (6-A Peak) Output • Battery Chargers

Current

• 12-V/24-V Distributed Power Systems

• High Efficiency Greater than 90% Enabled by

110-mΩ Integrated MOSFET Switch DESCRIPTION

As a member of the SWIFT™ family of DC/DC

• Wide Output Voltage Range: Adjustable Down

regulators, the TPS5450 is a high-output-current

to 1.22 V with 1.5% Initial Accuracy

PWM converter that integrates a low-resistance

• Internal Compensation Minimizes External

high-side N-channel MOSFET. Included on the

Parts Count

substrate with the listed features are a

• Fixed 500-kHz Switching Frequency for Small

high-performance voltage error amplifier that provides

Filter Size

tight voltage regulation accuracy under transient

conditions, an undervoltage-lockout circuit to prevent

• 18-μA Shutdown Supply Current

start-up until the input voltage reaches 5.5 V, an

• Improved Line Regulation and Transient

internally set slow-start circuit to limit inrush currents,

Response by Input Voltage Feed Forward

and a voltage feed-forward circuit to improve the

• System Protected by Overcurrent Limiting, transient response. Using the ENA pin, shutdown

supply current is reduced to 18 μA typically. Other

Overvoltage Protection, and Thermal

features include an active-high enable, overcurrent

Shutdown

limiting, overvoltage protection, and thermal

• –40°C to 125°C Operating Junction

shutdown. To reduce design complexity and external

Temperature Range

component count, the TPS5450 feedback loop is

• Available in Small Thermally Enhanced 8-Pin

internally compensated.

SOIC PowerPAD™ Package

The TPS5450 device is available in a thermally

• For SWIFT™ Documentation, Application

enhanced, 8-pin SOIC PowerPAD™ package. TI

Reports and Design Software, See the TI

provides evaluation modules and software tools to aid

Website at www.ti.com/swift

in achieving high-performance power supply designs

to meet aggressive equipment development cycles.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2SWIFT, PowerPAD are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (26 pages)

PAGE 1
TPS5450-Q1 SLVS834A – JULY 2008 – REVISED OCTOBER 2011 www.ti.com 5-A, WIDE INPUT RANGE, STEP-DOWN SWIFT™ CONVERTER Check for Samples: TPS5450-Q1 FEATURES APPLICATIONS • • • • • • • 1 2 • • • • • • • • • • Qualified for Automotive Applications Wide Input Voltage Range: 5.5 V to 36 V Up to 5-A Continuous (6-A Peak) Output Current High Efficiency Greater than 90% Enabled by 110-mΩ Integrated MOSFET Switch Wide Output Voltage Range: Adjustable Down to 1.22 V with 1.
PAGE 2
TPS5450-Q1 SLVS834A – JULY 2008 – REVISED OCTOBER 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
PAGE 3
TPS5450-Q1 SLVS834A – JULY 2008 – REVISED OCTOBER 2011 www.ti.com DISSIPATION RATINGS (1) (1) (2) (3) (2) PACKAGE THERMAL IMPEDANCE JUNCTION-TO-AMBIENT 8-Pin DDA (4-layer board with solder) (3) 30°C/W Maximum power dissipation may be limited by overcurrent protection. Power rating at a specific ambient temperature TA should be determined with a junction temperature of 125°C. This is the point where distortion starts to substantially increase.
PAGE 4
TPS5450-Q1 SLVS834A – JULY 2008 – REVISED OCTOBER 2011 www.ti.com PIN ASSIGNMENTS DDA PACKAGE (TOP VIEW) 8 PH 7 VIN 3 6 GND 4 5 ENA BOOT 1 NC 2 NC VSENSE PowerPAD (Pin 9) TERMINAL FUNCTIONS TERMINAL NAME DESCRIPTION NO. BOOT 1 NC 2, 3 Boost capacitor for the high-side FET gate driver. Connect 0.01-μF low-ESR capacitor from BOOT pin to PH pin. No internal connection VSENSE 4 Feedback voltage for the regulator. Connect to output voltage divider. ENA 5 On/off control. Below 0.
PAGE 5
TPS5450-Q1 SLVS834A – JULY 2008 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS OSCILLATOR FREQUENCY vs JUNCTION TEMPERATURE NON-SWITCHING QUIESCENT CURRENT vs JUNCTION TEMPERATURE 530 3.5 VI = 12 V I Q−Quiescent Current −mA f − Oscillator Frequency − kHz 520 510 500 490 480 3.25 3 2.75 470 460 −50 −25 0 25 50 75 100 2.5 −50 125 −25 50 75 100 Figure 2.
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TPS5450-Q1 SLVS834A – JULY 2008 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) MINIMUM CONTROLLABLE ON TIME vs JUNCTION TEMPERATURE MINIMUM CONTROLLABLE DUTY RATIO vs JUNCTION TEMPERATURE 8 170 7.75 Minimum Duty Ratio - % Minimum Controllable On Time − ns 180 160 150 140 7.50 7.25 130 120 −50 −25 0 25 50 75 100 TJ − Junction Temperature − °C 125 7 -50 Figure 7. 6 -25 50 0 25 75 100 TJ - Junction Temperature - °C 125 Figure 8.
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TPS5450-Q1 SLVS834A – JULY 2008 – REVISED OCTOBER 2011 www.ti.com APPLICATION INFORMATION FUNCTIONAL BLOCK DIAGRAM VIN VIN 1.221 V Bandgap Reference UVLO VREF SHDN Slow Start Boot Regulator BOOT HICCUP 5 µA ENABLE ENA SHDN SHDN VSENSE Z1 Thermal Protection SHDN NC VIN Ramp Generator NC SHDN VSENSE HICCUP PWM Comparator Overcurrent Protection Oscillator OVP Z2 Feed Forward Gain = 25 SHDN GND POWERPAD Error Amplifier SHDN SHDN Gate Drive Control 112.
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TPS5450-Q1 SLVS834A – JULY 2008 – REVISED OCTOBER 2011 www.ti.com Undervoltage Lockout (UVLO) The TPS5450 incorporates an undervoltage lockout circuit to keep the device disabled when VIN (the input voltage) is below the UVLO start voltage threshold. During power up, internal circuits are held inactive and the internal slow start is grounded until VIN exceeds the UVLO start threshold voltage. Once the UVLO start threshold voltage is reached, the internal slow start is released and device start-up begins.
PAGE 9
TPS5450-Q1 SLVS834A – JULY 2008 – REVISED OCTOBER 2011 www.ti.com Overvoltage Protection The TPS5450 has an overvoltage protection (OVP) circuit to minimize voltage overshoot when recovering from output fault conditions. The OVP circuit includes an overvoltage comparator to compare the VSENSE pin voltage and a threshold of 112.5% × VREF. Once the VSENSE pin voltage is higher than the threshold, the high-side MOSFET is forced off.
PAGE 10
TPS5450-Q1 SLVS834A – JULY 2008 – REVISED OCTOBER 2011 www.ti.com Feedback Trace OUTPUT INDUCTOR BOOT CAPACITOR PH BOOT NC INPUT BYPASS CAPACITOR Vout PH Vin VIN EXPOSED POWERPAD AREA RESISTOR DIVIDER NC GND VSENSE ENA OUTPUT FILTER CAPACITOR CATCH DIODE TOPSIDE GROUND AREA Route INPUT VOLTAGE trace under the catch diode and output capacitor or on another layer Signal VIA Figure 9.
PAGE 11
TPS5450-Q1 SLVS834A – JULY 2008 – REVISED OCTOBER 2011 www.ti.com Figure 10. TPS5450 Land Pattern Application Circuits Figure 11 shows the schematic for a typical TPS5450 application. The TPS5450 can provide up to 5-A output current at a nominal output voltage of 5 V. For proper thermal performance, the exposed PowerPAD™ underneath the device must be soldered down to the printed-circuit board. Figure 11. Application Circuit, 12-V to 5.
PAGE 12
TPS5450-Q1 SLVS834A – JULY 2008 – REVISED OCTOBER 2011 www.ti.com Design Procedure The following design procedure can be used to select component values for the TPS5450. Alternately, the SWIFT™ Designer Software may be used to generate a complete design. The SWIFT™ Designer Software uses an iterative design procedure and accesses a comprehensive database of components when generating a design. This section presents a simplified discussion of the design process.
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TPS5450-Q1 SLVS834A – JULY 2008 – REVISED OCTOBER 2011 www.ti.com Additionally some bulk capacitance may be needed, especially if the TPS5450 circuit is not located within about 2 inches from the input voltage source. The value for this capacitor is not critical but it also should be rated to handle the maximum input voltage including ripple voltage and should filter the output so that input ripple voltage is acceptable.
PAGE 14
TPS5450-Q1 SLVS834A – JULY 2008 – REVISED OCTOBER 2011 www.ti.com For the output filter inductor it is important that the RMS current and saturation current ratings not be exceeded. The RMS inductor current can be found from Equation 5: I L(RMS) + Ǹ 1 I2 ) OUT(MAX) 12 ǒ V V OUT ǒVIN(MAX) * VOUTǓ L IN(MAX) OUT F Ǔ 2 SW(MIN) (5) and the peak inductor current can be determined with Equation 6: V I L(PK) + I OUT(MAX) ) 1.
PAGE 15
TPS5450-Q1 SLVS834A – JULY 2008 – REVISED OCTOBER 2011 www.ti.com For this design example, a single 330-μF output capacitor is chosen for C3. The calculated RMS ripple current is 143 mA and the maximum ESR required is 40 mΩ. A capacitor that meets these requirements is a Sanyo Poscap 10TPB330M, rated at 10 V with a maximum ESR of 35 mΩ and a ripple current rating of 3 A. An additional small 0.1-μF ceramic bypass capacitor, C6 is also used in this design.
PAGE 16
TPS5450-Q1 SLVS834A – JULY 2008 – REVISED OCTOBER 2011 www.ti.com Where VINMIN = minimum input voltage IOMAX = maximum load current VD = catch diode forward voltage. RL= output inductor series resistance. This equation assumes maximum on resistance for the internal high side FET. The lower limit is constrained by the minimum controllable on time, which may be as high as 200 ns. The approximate minimum output voltage for a given input voltage and minimum load current is given by: V OUTMIN + 0.
PAGE 17
TPS5450-Q1 SLVS834A – JULY 2008 – REVISED OCTOBER 2011 www.ti.com PERFORMANCE GRAPHS The performance graphs (Figure 12 through Figure 18) are applicable to the circuit in Figure 11. Ta = 25 °C. unless otherwise specified. 0.3 100 0.2 VI = 12 V 95 Output Regulation - % Efficiency - % VI = 15 V 90 VI = 24 V 85 VI = 28 V 80 0.1 0 -0.1 -0.2 75 0 1 2 3 4 IO - Output Current - A 5 6 Figure 12. Efficiency vs. Output Current -0.3 0 0.5 1 1.5 2 2.5 3 3.5 IO - Output Current - A 4 4.
PAGE 18
TPS5450-Q1 SLVS834A – JULY 2008 – REVISED OCTOBER 2011 www.ti.com VOUT = 50 mV/div (AC Coupled, 20 MHz BWL) VOUT = 50 mV/div (AC Coupled, 20 MHz BWL) VPH = 10 V/div IOUT = 1 A/div t - Time = 1 ms/div t - Time = 100 ms/div Figure 16. Output Voltage Ripple and PH Node, Io =5A Figure 17. Transient Response, Io Step 1.25 to 3.75 A. TJ - Junction Temperature - °C 125 100 75 50 25 0 0.5 1 1.5 2 2.5 IC Power Dissipation - W 3 3.5 Figure 18. TPS5450 Power Dissipation vs Junction Temperature.
PAGE 19
TPS5450-Q1 SLVS834A – JULY 2008 – REVISED OCTOBER 2011 www.ti.com REVISION HISTORY Changes from Original (July 2008) to Revision A • Page Added Thermal Table ...........................................................................................................................................................
PAGE 20
PACKAGE OPTION ADDENDUM www.ti.com 5-Feb-2014 PACKAGING INFORMATION Orderable Device Status (1) TPS5450QDDARQ1 Package Type Package Pins Package Drawing Qty ACTIVE SO PowerPAD DDA 8 2500 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Green (RoHS & no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR Op Temp (°C) Device Marking (4/5) -40 to 125 5450Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 22
PACKAGE MATERIALS INFORMATION www.ti.com 14-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS5450QDDARQ1 Package Package Pins Type Drawing SO Power PAD DDA 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.8 Pack Materials-Page 1 6.4 B0 (mm) K0 (mm) P1 (mm) 5.2 2.1 8.0 W Pin1 (mm) Quadrant 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS5450QDDARQ1 SO PowerPAD DDA 8 2500 366.0 364.0 50.
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