Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - DC/DC voltage regulator Holder WQFN 16

Efficiency - %

I - Output Current - A

100

0 1 2 3 4 5 6

3 Vin

5 Vin

f = 500kHz

Vout = 1.8V

VIN

POWERPAD

BOOT

VSENSE

COMP

TPS54618

RT /CLK

SS/TR

PWRGD

BOOT

VOUT

VIN

AGND

GND

TPS54618

www.ti.com

SLVSAE9D –NOVEMBER 2010–REVISED DECEMBER 2013

2.95-V to 6-V Input, 6-A Output, 2-MHz, Synchronous Step-Down

SWIFT™ Switcher

Check for Samples: TPS54618

FEATURES

DESCRIPTION

The TPS54618 device is a full-featured 6-V, 6-A,

• Two 12-mΩ (typical) MOSFETs for High

synchronous step-down current-mode converter with

Efficiency at 6-A Loads

two integrated MOSFETs.

• 300-kHz to 2-MHz Switching Frequency

The TPS54618 enables small designs by integrating

• 0.8-V ±1% Voltage Reference Over

the MOSFETs, implementing current-mode control to

Temperature (–40°C to 150°C)

reduce external component count, reducing inductor

• Synchronizes to External Clock

size by enabling up to 2-MHz switching frequency,

and minimizing the IC footprint with a small 3-mm ×

• Adjustable Slow-Start and Sequencing

3-mm thermally enhanced QFN package.

• UV and OV Power-Good Output

The TPS54618 provides accurate regulation for a

• –40°C to 150°C Operating Junction

variety of loads with an accurate ±1% voltage

Temperature Range

reference (VREF) over temperature.

• Thermally Enhanced 3-mm × 3-mm 16-pin QFN

Efficiency is maximized through the integrated 12-mΩ

• Pin-Compatible to TPS54418

MOSFETs and 515-μA typical supply current. Using

the enable pin, shutdown supply current is reduced to

APPLICATIONS

5.5-µA by entering a shutdown mode.

• Low-Voltage, High-Density Power Systems

Undervoltage lockout is internally set at 2.6 V, but

• Point-of-Load Regulation for High-

can be increased by programming the threshold with

Performance DSPs, FPGAs, ASICs, and

a resistor network on the enable pin. The output-

Microprocessors

voltage startup ramp is controlled by the slow-start

pin. An open-drain power-good signal indicates the

• Broadband, Networking, and Optical

output is within 93% to 107% of its nominal voltage.

Communications Infrastructure

Frequency foldback and thermal shutdown protect the

SIMPLIFIED SCHEMATIC

device during an overcurrent condition.

vertical spacer

The TPS54618 is supported in the SwitcherPro™

software tool at www.ti.com/switcherpro.

vertical spacer

For more SWIFT

documentation, see the TI Web

site at www.ti.com/swift.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2SWIFT, SwitcherPro are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (38 pages)

PAGE 1
TPS54618 www.ti.com SLVSAE9D – NOVEMBER 2010 – REVISED DECEMBER 2013 2.95-V to 6-V Input, 6-A Output, 2-MHz, Synchronous Step-Down SWIFT™ Switcher Check for Samples: TPS54618 FEATURES DESCRIPTION • The TPS54618 device is a full-featured 6-V, 6-A, synchronous step-down current-mode converter with two integrated MOSFETs. 1 2 • • • • • • • • Two 12-mΩ (typical) MOSFETs for High Efficiency at 6-A Loads 300-kHz to 2-MHz Switching Frequency 0.
PAGE 2
TPS54618 SLVSAE9D – NOVEMBER 2010 – REVISED DECEMBER 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
PAGE 3
TPS54618 www.ti.com SLVSAE9D – NOVEMBER 2010 – REVISED DECEMBER 2013 Thermal Information TPS54618 THERMAL METRIC (1) RTE UNITS 16 PINS Junction-to-ambient thermal resistance (2) θJA 44.38 (3) θJCtop Junction-to-case (top) thermal resistance θJB Junction-to-board thermal resistance (4) 15.96 ψJT Junction-to-top characterization parameter (5) 0.69 ψJB Junction-to-board characterization parameter (6) 15.91 θJCbot Junction-to-case (bottom) thermal resistance (7) 4.
PAGE 4
TPS54618 SLVSAE9D – NOVEMBER 2010 – REVISED DECEMBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) TJ = –40°C to 150°C, VIN = 2.95 to 6 V (unless otherwise noted) DESCRIPTION CONDITIONS MIN TYP MAX VIN = 6 V, 25°C < TJ < 150°C 7.46 10.6 15.3 VIN = 2.95 V, 25°C < TJ < 150°C 7.68 10.2 13.
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TPS54618 www.ti.com SLVSAE9D – NOVEMBER 2010 – REVISED DECEMBER 2013 DEVICE INFORMATION PIN CONFIGURATION VIN 1 VIN 2 VIN EN PWRGD BOOT QFN16 RTE Package (Top View) 16 15 14 13 12 PH 11 PH Exposed Thermal Pad (17) PH GND 4 9 SS/TR 6 7 8 RT/CLK 5 COMP 10 VSENSE 3 AGND GND PIN FUNCTIONS PIN NAME DESCRIPTION NO. AGND 5 Analog Ground should be electrically connected to GND close to the device. BOOT 13 A bootstrap capacitor is required between BOOT and PH.
PAGE 6
TPS54618 SLVSAE9D – NOVEMBER 2010 – REVISED DECEMBER 2013 www.ti.
PAGE 7
TPS54618 www.ti.com SLVSAE9D – NOVEMBER 2010 – REVISED DECEMBER 2013 TYPICAL CHARACTERISTICS CURVES FREQUENCY vs TEMPERATURE 525 520 0.023 High Side Rdson Vin = 3.3 V 0.021 Low Side Rdson Vin = 3.3 V 0.019 0.017 0.015 0.013 High Side Rdson Vin = 5 V 0.011 Low Side Rdson Vin = 5 V 0.009 RT = 400 kW, Vin = 5 V 515 fs - Switching Frequency - kHz RDSON - Static Drain-Source On-State Resistance - W HIGH SIDE AND LOW SIDE RDS(ON) vs TEMPERATURE 0.025 510 505 500 495 490 485 480 0.007 0.
PAGE 8
TPS54618 SLVSAE9D – NOVEMBER 2010 – REVISED DECEMBER 2013 www.ti.com TYPICAL CHARACTERISTICS CURVES (continued) TRANSCONDUCTANCE (SLOW START) vs JUNCTION TEMPERATURE TRANSCONDUCTANCE vs TEMPERATURE 105 310 Vin = 3.3 V 100 Vin = 3.3 V EA - Transconductance - mA/V EA - Transconductance - mA/V 290 270 250 230 210 95 90 85 80 75 70 65 190 60 170 -50 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 55 -50 150 -25 0 25 50 75 100 TJ - Junction Temperature - °C Figure 7.
PAGE 9
TPS54618 www.ti.com SLVSAE9D – NOVEMBER 2010 – REVISED DECEMBER 2013 TYPICAL CHARACTERISTICS CURVES (continued) INPUT VOLTAGE vs TEMPERATURE SHUTDOWN SUPPLY CURRENT vs TEMPERATURE 2.8 8 2.7 7 Shutdown Supply Current - mA Vin = 3.3 V VI - Input Voltage - V 2.6 UVLO Stop Switching 2.5 2.4 2.3 UVLO Start Switching 2.2 6 5 4 3 2 1 2.1 2 -50 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 0 -50 150 -25 0 Figure 13. 125 150 Figure 14.
PAGE 10
TPS54618 SLVSAE9D – NOVEMBER 2010 – REVISED DECEMBER 2013 www.ti.com TYPICAL CHARACTERISTICS CURVES (continued) SS/TR to VSENSE OFFSET vs TEMPERATURE 100 100 Vin = 3.3 V 90 Vin = 5 V, SS = 0.
PAGE 11
TPS54618 www.ti.com SLVSAE9D – NOVEMBER 2010 – REVISED DECEMBER 2013 OVERVIEW The TPS54618 is a 6-V, 6-A, synchronous step-down (buck) converter with two integrated n-channel MOSFETs. To improve performance during line and load transients the device implements a constant frequency, peak current mode control which reduces output capacitance and simplifies external frequency compensation design.
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TPS54618 SLVSAE9D – NOVEMBER 2010 – REVISED DECEMBER 2013 www.ti.com BOOTSTRAP VOLTAGE (BOOT) AND LOW DROPOUT OPERATION The TPS54618 has an integrated boot regulator and requires a small ceramic capacitor between the BOOT and PH pin to provide the gate drive voltage for the high side MOSFET. The value of the ceramic capacitor should be 0.1 μF.
PAGE 13
TPS54618 www.ti.com SLVSAE9D – NOVEMBER 2010 – REVISED DECEMBER 2013 ENABLE AND ADJUSTING UNDER-VOLTAGE LOCKOUT The TPS54618 is disabled when the VIN pin voltage falls below 2.28 V. If an application requires a higher undervoltage lockout (UVLO), use the EN pin as shown in Figure 26 to adjust the input voltage UVLO by using two external resistors. It is recommended to use the EN resistors to set the UVLO falling threshold (VSTOP) above 2.6V.
PAGE 14
TPS54618 SLVSAE9D – NOVEMBER 2010 – REVISED DECEMBER 2013 www.ti.com SEQUENCING Many of the common power supply sequencing methods can be implemented using the SS/TR, EN and PWRGD pins. The sequential method can be implemented using an open drain or collector output of a power on reset pin of another device. Figure 27 shows the sequential method. The power good is coupled to the EN pin on the TPS54618 which enables the second power supply once the primary supply reaches regulation.
PAGE 15
TPS54618 www.ti.com SLVSAE9D – NOVEMBER 2010 – REVISED DECEMBER 2013 Ratio-metric and simultaneous power supply sequencing can be implemented by connecting the resistor network of R1 and R2 shown in Figure 31 to the output of the power supply that needs to be tracked or another voltage reference source. Using Equation 5 and Equation 6, the tracking resistors can be calculated to initiate the Vout2 slightly before, after or at the same time as Vout1.
PAGE 16
TPS54618 SLVSAE9D – NOVEMBER 2010 – REVISED DECEMBER 2013 www.ti.com CONSTANT SWITCHING FREQUENCY and TIMING RESISTOR (RT/CLK Pin) The switching frequency of the TPS54618 is adjustable over a wide range from 300 kHz to 2000 kHz by placing a maximum of 700 kΩ and minimum of 85 kΩ, respectively, on the RT/CLK pin. An internal amplifier holds this pin at a fixed voltage when using an external resistor to ground to set the switching frequency. The RT/CLK is typically 0.5 V.
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TPS54618 www.ti.com SLVSAE9D – NOVEMBER 2010 – REVISED DECEMBER 2013 TPS54618 SYNC Clock PLL RT/CLK Clock Source RT PH Figure 33. Synchronizing to a System Clock Figure 34.
PAGE 18
TPS54618 SLVSAE9D – NOVEMBER 2010 – REVISED DECEMBER 2013 www.ti.com POWER GOOD (PWRGD PIN) The PWRGD pin output is an open drain MOSFET. The output is pulled low when the VSENSE voltage enters the fault condition by falling below 91% or rising above 109% of the nominal internal reference voltage. There is a 2% hysteresis on the threshold voltage, so when the VSENSE voltage rises to the good condition above 93% or falls below 107% of the internal voltage reference the PWRGD output MOSFET is turned off.
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TPS54618 www.ti.com SLVSAE9D – NOVEMBER 2010 – REVISED DECEMBER 2013 SIMPLE SMALL SIGNAL MODEL FOR PEAK CURRENT MODE CONTROL Figure 35 is a simple small signal model that can be used to understand how to design the frequency compensation. The TPS54618 power stage can be approximated to a voltage controlled current source (duty cycle modulator) supplying current to the output capacitor and load resistor.
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TPS54618 SLVSAE9D – NOVEMBER 2010 – REVISED DECEMBER 2013 www.ti.com VO R1 VSENSE COMP gmea R2 Vref RO CO 5pF Type 2A R3 C2 Type 2B R3 C1 C1 Figure 37. Types of Frequency Compensation The design guidelines for TPS54618 loop compensation are as follows: 1. The modulator pole, fpmod, and the esr zero, fz1 must be calculated using Equation 15 and Equation 16. Derating the output capacitor (COUT) may be needed if the output voltage is a high percentage of the capacitor rating.
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TPS54618 www.ti.com SLVSAE9D – NOVEMBER 2010 – REVISED DECEMBER 2013 APPLICATION INFORMATION DESIGN GUIDE – STEP-BY-STEP DESIGN PROCEDURE This example details the design of a high frequency switching regulator design using ceramic output capacitors. This design is available as the HPA606 evaluation module (EVM). A few parameters must be known in order to start the design process. These parameters are typically determined on the system level.
PAGE 22
TPS54618 SLVSAE9D – NOVEMBER 2010 – REVISED DECEMBER 2013 www.ti.com The current flowing through the inductor is the inductor ripple current plus the output current. During power up, faults or transient load conditions, the inductor current can increase above the calculated peak inductor current level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of the device.
PAGE 23
TPS54618 www.ti.com SLVSAE9D – NOVEMBER 2010 – REVISED DECEMBER 2013 allowable change in the output voltage. (27) vertical spacer Equation 28 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple specification. Equation 28 indicates the ESR should be less than 18 mΩ. In this case, the ESR of the ceramic capacitor is much less than 18 mΩ. Additional capacitance de-ratings for aging, temperature and DC bias should be factored in which increases this minimum value.
PAGE 24
TPS54618 SLVSAE9D – NOVEMBER 2010 – REVISED DECEMBER 2013 www.ti.com The slow start capacitor value can be calculated using Equation 32. For the example circuit, the slow start time is not too critical since the output capacitor value is 110 μF which does not require much current to charge to 1.8 V. The example circuit has the slow start time set to an arbitrary value of 4ms which requires a 10 nF capacitor. In TPS54618, Iss is 2.2 μA and Vref is 0.799 V.
PAGE 25
TPS54618 www.ti.com SLVSAE9D – NOVEMBER 2010 – REVISED DECEMBER 2013 To get started, the modulator pole, fpmod, and the esr zero, fz1 must be calculated using Equation 36 and Equation 37. For Cout, the derated capacitance value is 82.5 µF. Use Equation 38 and Equation 39 to estimate a starting point for the crossover frequency, fc. For the example design, fpmod is 6.43 kHz and fzmod is 643 kHz.
PAGE 26
TPS54618 SLVSAE9D – NOVEMBER 2010 – REVISED DECEMBER 2013 www.ti.com EFFICIENCY vs LOAD CURRENT EFFICIENCY vs LOAD CURRENT 100 100 90 90 70 Efficiency - % 70 Efficiency - % Vin = 3.3 V 80 Vin = 5 V Vin = 3 V 80 60 50 40 60 Vin = 5 V 50 40 30 30 20 20 10 10 0 0 1 2 3 4 5 6 0 0.01 0.1 Output Current - A Figure 39. Iout = 2 A / div (1.5 A to 4.5 A load step) 10 Figure 40. TRANSIENT RESPONSE, 1.
PAGE 27
TPS54618 www.ti.com SLVSAE9D – NOVEMBER 2010 – REVISED DECEMBER 2013 CLOSED LOOP RESPONSE, VIN (5 V), 3 A Gain - dB Vin = 100 mV / div (ac coupled) PH = 2 V / div 60 180 50 150 40 120 30 90 20 60 10 30 0 0 –10 –30 –20 –60 –30 –90 –40 –120 –50 –60 100 Time = 500 nsec / div Gain Phase 1000 Figure 45. –150 10k Frequency - Hz –180 1M 100k Figure 46. LOAD REGULATION vs LOAD CURRENT REGULATION vs INPUT VOLTAGE 0.4 0.4 0.3 0.
PAGE 28
TPS54618 SLVSAE9D – NOVEMBER 2010 – REVISED DECEMBER 2013 www.ti.com So Ptot = Pcon + Pd + Psw + Pgd + Pq For given TA, TJ = TA + Rth × Ptot For given TJMAX = 150°C TAmax = TJ max – Rth × Ptot Where: Ptot is the total device power dissipation (W). TA is the ambient temperature (°C). TJ is the junction temperature (°C). Rth is the thermal resistance of the package (°C/W). TJMAX is maximum junction temperature (°C). TAMAX is maximum ambient temperature (°C).
PAGE 29
TPS54618 www.ti.com SLVSAE9D – NOVEMBER 2010 – REVISED DECEMBER 2013 VIA to Ground Plane UVLO SET RESISTORS VIN INPUT BYPASS CAPACITOR BOOT PWRGD EN VIN VIN BOOT CAPACITOR VIN OUTPUT INDUCTOR PH VIN PH EXPOSED POWERPAD AREA GND PH GND VOUT OUTPUT FILTER CAPACITOR PH SLOW START CAPACITOR RT/CLK COMP VSENSE AGND SS FEEDBACK RESISTORS ANALOG GROUND TRACE FREQUENCY SET RESISTOR COMPENSATION NETWORK TOPSIDE GROUND AREA VIA to Ground Plane Figure 49.
PAGE 30
TPS54618 SLVSAE9D – NOVEMBER 2010 – REVISED DECEMBER 2013 www.ti.com REVISION HISTORY Changes from Original (November 2010) to Revision A Page • Changed SWITCHING FREQUENCY vs RT RESISTANCE LOW FREQUENCY RANGE Typical Characteristics curve. .................................................................................................................................................................................... 7 • Changed Equation 9. ...........................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 23-Feb-2014 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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PACKAGE MATERIALS INFORMATION www.ti.com 5-Dec-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS54618RTER WQFN RTE 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS54618RTER WQFN RTE 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS54618RTET WQFN RTE 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 5-Dec-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS54618RTER WQFN RTE 16 3000 338.0 355.0 50.0 TPS54618RTER WQFN RTE 16 3000 367.0 367.0 35.0 TPS54618RTET WQFN RTE 16 250 210.0 185.0 35.0 TPS54618RTET WQFN RTE 16 250 338.0 355.0 50.
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