Datasheet

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100

Efficiency-%

0 1 2 3 4 5 6

LoadCurrent- A

8V

12V

17V

VOUT =3.3V

Fsw=480kHz

PVIN

GND

BOOT

VSENSE

COMP

TPS54620

RT/CLK

SS/TR

Exposed

Thermal

Pad

Css

Rrt

Cboot

Cin

VIN

VOUT

PWRGD

TPS54620

www.ti.com

SLVS949C –MAY 2009– REVISED MAY 2011

4.5V to 17V Input, 6A Synchronous Step Down SWIFT™ Converter

Check for Samples: TPS54620

FEATURES

• Adjustable Input Undervoltage Lockout

• Supported by SwitcherPro™ Software Tool

• Integrated 26mΩ / 19mΩ MOSFETs

• For SWIFT™ Documentation and

• Split Power Rail: 1.6V to 17V on PVIN

SwitcherPro™, visit http://www.ti.com/swift

• 200kHz to 1.6MHz Switching Frequency

• Synchronizes to External Clock

APPLICATIONS

• 0.8V ±1% Voltage Reference Over Temperature

• High Density Distributed Power Systems

• Low 2uA Shutdown Quiescent Current

• High Performance Point of Load Regulation

• Monotonic Start-Up into Pre-biased Outputs

• Broadband, Networking and Optical

• –40°C to 150°C Operating Junction

Communications Infrastructure

Temperature Range

• Adjustable Slow Start/Power Sequencing

• Power Good Output Monitor for Undervoltage

and Overvoltage

DESCRIPTION

The TPS54620 in thermally enhanced 3.5mm x 3.5mm QFN package is a full featured 17V, 6A synchronous step

down converter which is optimized for small designs through high efficiency and integrating the high-side and

low-side MOSFETs. Further space savings are achieved through current mode control, which reduces

component count, and by selecting a high switching frequency, reducing the inductor's footprint.

The output voltage startup ramp is controlled by the SS/TR pin which allows operation as either a stand alone

power supply or in tracking situations. Power sequencing is also possible by correctly configuring the enable and

the open drain power good pins.

Cycle by cycle current limiting on the high-side FET protects the device in overload situations and is enhanced

by a low-side sourcing current limit which prevents current runaway. There is also a low-side sinking current limit

which turns off the low-side MOSFET to prevent excessive reverse current. Thermal shutdown disables the part

when die temperature exceeds thermal shutdown temperature.

WHITE SPACE

SIMPLIFIED SCHEMATIC

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (44 pages)

PAGE 1
TPS54620 SLVS949C – MAY 2009 – REVISED MAY 2011 www.ti.com 4.5V to 17V Input, 6A Synchronous Step Down SWIFT™ Converter Check for Samples: TPS54620 FEATURES 1 • • • • • • • • • • Integrated 26mΩ / 19mΩ MOSFETs Split Power Rail: 1.6V to 17V on PVIN 200kHz to 1.6MHz Switching Frequency Synchronizes to External Clock 0.
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TPS54620 SLVS949C – MAY 2009 – REVISED MAY 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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TPS54620 SLVS949C – MAY 2009 – REVISED MAY 2011 www.ti.com PACKAGE DISSIPATION RATINGS (1) (1) (2) (3) (4) (2) (3) (4) PACKAGE THERMAL IMPEDANCE JUNCTION TO AMBIENT θJP THERMAL IMPEDANCE JUNCTION TO EXPOSED THERMAL PAD ψ JT THERMAL CHARACTERISTIC JUNCTION TO TOP RHL/RGY 32°C/W 5.2°C/W 5°C/W Maximum power dissipation may be limited by overcurrent protection Power rating at a specific ambient temperature TA should be determined with a junction temperature of 150°C.
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TPS54620 SLVS949C – MAY 2009 – REVISED MAY 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) TJ = –40°C to 150°C, VIN = 4.5V to 17V, PVIN = 1.
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TPS54620 SLVS949C – MAY 2009 – REVISED MAY 2011 www.ti.com DEVICE INFORMATION PIN ASSIGNMENTS RHL and RGY PACKAGE (TOP VIEW) RT/CLK 1 PWRGD 14 GND 2 13 BOOT GND 3 PVIN 4 PVIN 5 12 PH Exposed Thermal Pad (15) VIN 6 11 PH 10 EN 9 SS/TR 7 VSENSE 8 COMP PIN FUNCTIONS PIN NAME RT/CLK DESCRIPTION No. 1 Automatically selects between RT mode and CLK mode. An external timing resistor adjusts the switching frequency of the device; In CLK mode, the device synchronizes to an external clock.
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TPS54620 SLVS949C – MAY 2009 – REVISED MAY 2011 www.ti.
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TPS54620 SLVS949C – MAY 2009 – REVISED MAY 2011 www.ti.com TYPICAL CHARACTERISTICS CHARACTERISTIC CURVES HIGH-SIDE RDS(on) vs TEMPERATURE LOW-SIDE RDS(on) vs TEMPERATURE 30 40 VIN = 12 V RDS(on) − On Resistance − mΩ RDS(on) − On Resistance − mΩ VIN = 12 V 35 30 25 20 −50 −25 0 25 50 75 100 125 27 24 21 18 15 −50 150 −25 TJ − Junction Temperature − °C 0 75 100 125 150 Figure 2. VOLTAGE REFERENCE vs TEMPERATURE OSCILLATOR FREQUENCY vs TEMPERATURE 0.
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TPS54620 SLVS949C – MAY 2009 – REVISED MAY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) PIN PULL-UP CURRENT vs TEMPERATURE PIN UVLO THRESHOLD vs TEMPERATURE 1.220 μ En Pin UVLO Threshold − V VIN = 12 V 1.215 1.210 1.205 1.200 −50 −25 25 50 75 100 125 150 TJ − Junction Temperature − °C °C Figure 7. Figure 8. NON-SWITCHING OPERATING QUIESCENT CURRENT (VIN) vs INPUT VOLTAGE SLOW START CHARGE CURRENT vs TEMPERATURE 2.
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TPS54620 SLVS949C – MAY 2009 – REVISED MAY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) HIGH-SIDE CURRENT LIMIT THRESHOLD vs INPUT VOLTAGE MINIMUM CONTROLLABLE ON TIME vs TEMPERATURE 120 Minimum Controllable On Time − ns IcI − Current Limit Threshold − A 13 12 11 10 TJ = −40°C 9 TJ = 25°C TJ = 150°C 8 7 6 5 9 13 110 100 90 80 70 −50 5 1 VIN = 12 V IOUT = 2A 17 −25 0 25 50 75 100 125 150 TJ − Junction Temperature − °C VI − Input Voltage − V Figure 14.
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TPS54620 SLVS949C – MAY 2009 – REVISED MAY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) The device reduces the external component count by integrating the boot recharge circuit. The bias voltage for the integrated high-side MOSFET is supplied by a capacitor between the BOOT and PH pins. The boot capacitor voltage is monitored by a BOOT to PH UVLO (BOOT-PH UVLO) circuit allowing PH pin to be pulled low to recharge the boot capacitor.
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TPS54620 www.ti.com SLVS949C – MAY 2009 – REVISED MAY 2011 Adjusting the Output Voltage The output voltage is set with a resistor divider from the output (VOUT) to the VSENSE pin. It is recommended to use 1% tolerance or better divider resistors. Referring to the application schematic of Figure 34, start with a 10 kΩ for R6 and use Equation 1 to calculate R5. To improve efficiency at light loads consider using larger value resistors.
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TPS54620 SLVS949C – MAY 2009 – REVISED MAY 2011 www.ti.com TPS54620 VIN ip ih R1 R2 EN Figure 17. Adjustable VIN Under Voltage Lock Out TPS54620 PVIN ip ih R1 R2 EN Figure 18. Adjustable PVIN Under Voltage Lock Out, VIN ≥ 4.5V TPS54620 PVIN VIN ip ih R1 R2 EN Figure 19.
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TPS54620 SLVS949C – MAY 2009 – REVISED MAY 2011 www.ti.com In RT mode, a resistor (RT resistor) is connected between the RT/CLK pin and GND. The switching frequency of the device is adjustable from 200 kHz to 1600 kHz by placing a maximum of 240 kΩ and minimum of 29 kΩ respectively. In CLK mode, an external clock is connected directly to the RT/CLK pin. The device is synchronized to the external clock frequency with PLL. The CLK mode overrides the RT mode.
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TPS54620 SLVS949C – MAY 2009 – REVISED MAY 2011 www.ti.com Slow Start (SS/TR) The device uses the lower voltage of the internal voltage reference or the SS/TR pin voltage as the reference voltage and regulates the output accordingly. A capacitor on the SS/TR pin to ground implements a slow start time. The device has an internal pull-up current source of 2.3μA that charges the external slow start capacitor.
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TPS54620 SLVS949C – MAY 2009 – REVISED MAY 2011 www.ti.com PWRGD = 2 V / div TPS54620 TPS54620 PWRGD EN EN SS/TR SS/TR EN = 2 V / div Vout1 = 1 V / div Vout2 = 1 v / div PWRGD Time = 20 msec / div Figure 22. Sequential Start Up Sequence Figure 23. Sequential Start Up using EN and PWRGD Figure 24 shows the method implementing ratio-metric sequencing by connecting the SS/TR pins of two devices together. The regulator outputs ramp up and reach regulation at the same time.
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TPS54620 SLVS949C – MAY 2009 – REVISED MAY 2011 www.ti.com To ensure proper operation of the device, the calculated R1 value from Equation 6 must be greater than the value calculated in Equation 9. R1 = Vout2 + D V Vssoffset ´ Vref Iss (6) Vref ´ R1 R2 = Vout2 + DV - Vref DV = Vout1 - Vout2 R1 > 2800 ´ Vout1- 180 ´ DV (7) (8) (9) TPS54620 EN VOUT1 SS/TR PWRGD TPS54620 EN VOUT 2 R1 SS/TR R2 PWRGD R4 R3 Figure 26.
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TPS54620 SLVS949C – MAY 2009 – REVISED MAY 2011 www.ti.com EN = 2 V / div Vout1 = 1 V / div Vout2 = 1 V / div Time = 20 msec / div Figure 28. Ratio-metric Startup with Vout2 Leading Vout1 EN = 2 V / div Vout1 = 1 V / div Vout2 = 1 V / div Time = 20 msec / div Figure 29. Simultaneous Startup Output Overvoltage Protection (OVP) The device incorporates an output overvoltage protection (OVP) circuit to minimize output voltage overshoot.
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TPS54620 SLVS949C – MAY 2009 – REVISED MAY 2011 www.ti.com While the low-side MOSFET is turned on its conduction current is monitored by the internal circuitry. During normal operation the low-side MOSFET sources current to the load. At the end of every clock cycle, the low-side MOSFET sourcing current is compared to the internally set low-side sourcing current limit. If the low-side sourcing current is exceeded the high-side MOSFET is not turned on and the low-side MOSFET stays on for the next cycle.
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TPS54620 SLVS949C – MAY 2009 – REVISED MAY 2011 www.ti.com VOUT VC RESR RL gm ps CO Figure 31. Simplified Small Signal Model for Peak Current Mode Control VOUT Adc VC RESR fp RL gm ps CO fz Figure 32.
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TPS54620 SLVS949C – MAY 2009 – REVISED MAY 2011 www.ti.com Small Signal Model for Frequency Compensation The device uses a transconductance amplifier for the error amplifier and readily supports two of the commonly used Type II compensation circuits and a Type III frequency compensation circuit, as shown in Figure 33. In Type 2A, one additional high frequency pole, C6, is added to attenuate high frequency noise.
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TPS54620 SLVS949C – MAY 2009 – REVISED MAY 2011 www.ti.com APPLICATION INFORMATION Design Guide – Step-By-Step Design Procedure This example details the design of a high frequency switching regulator design using ceramic output capacitors. A few parameters must be known in order to start the design process. These parameters are typically determined at the system level. For this example, we start with the following known parameters: Table 1. Parameter Value Output Voltage 3.
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TPS54620 SLVS949C – MAY 2009 – REVISED MAY 2011 L1 = www.ti.com Vinm ax - Vout Vout × Io × Kind Vinm ax × f sw (18) For this design example, use KIND = 0.3 and the inductor value is calculated to be 3.08 µH. For this design, a nearest standard value was chosen: 3.3 µH. For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded. The RMS and peak inductor current can be found from Equation 20 and Equation 21.
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TPS54620 SLVS949C – MAY 2009 – REVISED MAY 2011 www.ti.com Equation 24 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple specification. Equation 24 indicates the ESR should be less than 19.7 mΩ. In this case, the ceramic caps’ ESR is much smaller than 19.7 mΩ. Voripple Resr < Iripple (24) Additional capacitance de-ratings for aging, temperature and DC bias should be factored in which increases this minimum value. For this example, a 47 μF 6.
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TPS54620 SLVS949C – MAY 2009 – REVISED MAY 2011 www.ti.com Bootstrap Capacitor Selection A 0.1 µF ceramic capacitor must be connected between the BOOT to PH pin for proper operation. It is recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have 10V or higher voltage rating. Under Voltage Lockout Set Point The Under Voltage Lock Out (UVLO) can be adjusted using the external voltage divider network of R3 and R4.
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TPS54620 SLVS949C – MAY 2009 – REVISED MAY 2011 www.ti.com f zm od = 1 2 × p × RESR × Cout f co = f pmod × f zmod f co = f pmod × (32) (33) f sw 2 (34) Now the compensation components can be calculated. First calculate the value for R2 which sets the gain of the compensated network at the crossover frequency. Use Equation 35 to determine the value of R2. 2p × f c × Vout × Cout R2 = gmea × Vref × gmps (35) Next calculate the value of C3.
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TPS54620 SLVS949C – MAY 2009 – REVISED MAY 2011 SHUTDOWN with VIN Vin = 10 V / div www.ti.com SHUTDOWN with EN Vin = 10 V / div EN = 2 V / div EN = 2 V / div SS/TR = 1 V / div SS/TR = 1 V / div Vout = 2 V / div Vout = 2 V / div Time = 2 msec / div Figure 39. OUTPUT VOLTAGE RIPPLE with NO LOAD Vout = 10 mV / div (ac coupled) PH = 5 V / div Time = 1 μsec / div Figure 41. INPUT VOLTAGE RIPPLE with NO LOAD Time = 2 msec / div Figure 40.
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TPS54620 SLVS949C – MAY 2009 – REVISED MAY 2011 www.ti.com CLOSED LOOP RESPONSE LINE REGULATION 0.05 180 60 150 50 40 0.04 120 Phase 60 Gain 10 30 0 0 -30 -10 -60 -20 -30 -90 -40 -120 -50 -150 -60 -180 Percent Regulation - % 90 20 Phase - Deg Gain - dB 0.03 30 0.02 0.01 0 Io = 3A Io = 0A -0.01 -0.02 -0.03 Io = 6A -0.04 1000000 100000 10000 1000 100 10 Frequency - Hz -0.05 8 9 10 11 12 13 14 15 16 17 Input Voltage - V Figure 45. Figure 46.
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TPS54620 SLVS949C – MAY 2009 – REVISED MAY 2011 www.ti.com JUNCTION TEMPERATURE vs IC POWER DISSIPATION EFFICIENCY vs LOAD CURRENT 150 100 95 125 90 85 Efficiency - % TJ - Junction Temperature - °C TA = room temperature, no air flow 100 75 80 VOUT = 5 V 75 VOUT = 3.3 V 70 VOUT = 1.8 V 65 VOUT = 1.2 V 50 60 VIN = 12 V Fsw = 500 kHz 55 25 0 0.5 1 1.5 2 2.5 3 3.5 Pic - IC Power Dissipation - W Figure 51. 4 50 0 1 VOUT = 0.8 V 3 2 4 Load Current - A 5 6 Figure 52.
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TPS54620 SLVS949C – MAY 2009 – REVISED MAY 2011 www.ti.com Figure 54. 3.3V Output Power Supply Design (PMP4854-2) with Fast Transients Figure 55. Closed Loop Response for PMP4854-2 PCB Layout Guidelines Layout is a critical portion of good power supply design. See Figure 56 for a PCB layout example. The top layer contains the main power traces for VIN, VOUT, and VPHASE. Also on the top layer are connections for the remaining pins of the TPS54620 and a large top side area filled with ground.
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TPS54620 SLVS949C – MAY 2009 – REVISED MAY 2011 www.ti.com adequate width. The small signal components should be grounded to the analog ground path as shown. The RT/CLK pin is sensitive to noise so the RT resistor should be located as close as possible to the IC and routed with minimal lengths of trace. The additional external components can be placed approximately as shown.
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TPS54620 SLVS949C – MAY 2009 – REVISED MAY 2011 www.ti.com Figure 57. Ultra-Small PCB layout Using TPS54620 (PMP4854-2) Estimated Circuit Area The estimated printed circuit board area for the components used in the design of Figure 34 is 0.58. in2 (374 mm2). This area does not include test points or connectors. The board area can be further reduced if size is a big concern in an application.
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TPS54620 SLVS949C – MAY 2009 – REVISED MAY 2011 www.ti.com REVISION HISTORY Changes from Original (May 2009) to Revision A Page • Changed title from 17V Input, 6A Output, Synchronous Step Down Switcher with Integrated FET (SWIFT) ...................... 1 • Changed EN max value from 3V to 6V ................................................................................................................................ 2 • Added thermal impedance junction to power pad parameter ......................
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PACKAGE OPTION ADDENDUM 11 – February – 2011 PACKAGING INFORMATION Orderable Device Status (1) Pack Type Pack Drawing Pins Pack Qty TPS54620RGYR ACTIVE VQFN RGY 14 3000 TPS54620RGYT ACTIVE VQFN RGY 14 250 TPS54620RHLR ACTIVE QFN RHL 14 3000 TPS54620RHLT ACTIVE QFN RHL 14 250 Eco Plan (2) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Lead/ Ball Finish MSL Peak Temp (3) CU NIPDAU Level-2-260C-1 YEAR CU NIPDAU Level-2-26
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PACKAGE OPTION ADDENDUM 11 – February – 2011 TAPE AND REEL INFORMATION *All dimensions are normal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) TPS54620RGYR TPS54620RGYT TPS54620RHLR TPS54620RHLT VQFN VQFN QFN VQFN RGZ RGZ RHL RGZ 14 14 14 14 3000 250 3000 250 330.0 180.0 330.0 180.0 Reel Width W1 (mm) 12.4 12.4 12.4 12.4 Addendum Page 2 A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant 3.75 3.75 3.75 3.75 3.75 3.75 3.75 3.75 1.15 1.15 1.15 1.15 8.0 8.0 8.0 8.
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PACKAGE OPTION ADDENDUM 11 – February – 2011 TAPE AND REEL BOX DIMENSIONS *All dimensions are normal Device Package Type TPS54620RGYR VQFN TPS54620RGYT VQFN TPS54620RHLR QFN TPS54620RHLT QFN Package Drawing RGY RGY RGY RGY Pins 14 14 14 14 SPQ 3000 250 3000 250 Length (mm) 346.0 250 346.0 190.5 Addendum Page 3 Width (mm) 346.0 190.5 346.0 212.7 Height (mm) 29.0 31.8 29.0 31.
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PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS54620RGYR VQFN RGY 14 3000 330.0 12.4 3.75 3.75 1.15 8.0 12.0 Q1 TPS54620RGYR VQFN RGY 14 3000 330.0 12.4 3.75 3.75 1.15 8.0 12.0 Q1 TPS54620RGYT VQFN RGY 14 250 180.0 12.4 3.75 3.75 1.15 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS54620RGYR VQFN RGY 14 3000 367.0 367.0 35.0 TPS54620RGYR VQFN RGY 14 3000 367.0 367.0 35.0 TPS54620RGYT VQFN RGY 14 250 210.0 185.0 35.0 TPS54620RGYT VQFN RGY 14 250 210.0 185.0 35.0 TPS54620RHLR VQFN RHL 14 3000 367.0 367.0 35.0 TPS54620RHLR VQFN RHL 14 3000 367.0 367.0 35.
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