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

SLVS397C − JULY 2001 − REVISED FEBRUARY 2005

      

    

Typical Size

(6,4 mm X 9,7 mm )

FEATURES

D Tracks Externally Applied Reference Voltage

D 30-mΩ, 12-A Peak MOSFET Switches for High

Efficiency at 6-A Continuous Output Source

or Sink Current

D 6% to 90% VIN Output Tracking Range

D PWM Frequency Range:

Fixed 350 kHz or Adjustable 280 to 700 kHz

D Load Protected by Peak Current Limit and

Thermal Shutdown

D Integrated Solution Reduces Board Area and

Component Count

APPLICATIONS

D DDR Memory Termination Voltage

D Active Termination of GTL and STL

High-Speed Logic Families

D DAC Controlled High Current Output Stage

D Precision Point of Load Power Supply

DESCRIPTION

As a member of the SWIFT family of dc/dc regulators, the

TPS54672 active bus termination synchronous PWM

converter integrates all required active components.

Included on the substrate with the listed features are a true,

high performance, voltage error amplifier that enables

maximum performance and flexibility in choosing the

output filter L and C components; an under-voltage-

lockout circuit to prevent start-up until the input voltage

reaches 3 V; a slow-start control to limit in-rush currents;

and a status output to indicate valid operating conditions.

The TPS54672 is available in a thermally enhanced 28-pin

TSSOP (PWP) PowerPAD package, which eliminates

bulky heatsinks. TI provides evaluation modules and the

SWIFT designer software tool to aid in quickly achieving

high-performance power supply designs to meet

aggressive equipment development cycles.

SIMPLIFIED SCHEMATIC

VIN PH

BOOT

OUT

BOOT

PGND

VSENSE

0.56 µH

VTTQ

COMPAGND

VBIAS

BIAS

Input Voltage

3 V − 6 V

TPS54672

Typical DDR Memory Termination Regulator Circuit

REFIN

VDDQ

ENA

LOAD TRANSIENT RESPONSE

10 µs/div

Output Voltage

(50 mV/div AC Coupled)

Output Current

(2A/div)

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

www.ti.com

PowerPAD and SWIFT are trademarks of Texas Instruments.

Summary of content (20 pages)

PAGE 1
Typical Size (6,4 mm X 9,7 mm ) www.ti.
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www.ti.com SLVS397C − JULY 2001 − REVISED FEBRUARY 2005 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION TA −40°C to 85°C REFIN VOLTAGE PACKAGE PART NUMBER Plastic HTSSOP (PWP)(1) 0.2 V to 1.75 V TPS54672PWP (1) The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e.
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www.ti.com SLVS397C − JULY 2001 − REVISED FEBRUARY 2005 ELECTRICAL CHARACTERISTICS TJ = –40°C to +125°C, VI = 3 V to 6 V over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE, VIN Input voltage range, VIN VID I(Q) Differential voltage, AGND to PGND Quiescent current 3.0 6.0 V −0.30 0.30 V Switching freq. = 350 kHz, RT open 10 Switching freq. = 500 kHz, RT = 100 kΩ 16 24 1 1.4 2.95 3.
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www.ti.com SLVS397C − JULY 2001 − REVISED FEBRUARY 2005 ELECTRICAL CHARACTERISTICS Continued TJ = –40°C to +125°C, VI = 3 V to 6 V over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OSCILLATOR (CONTINUED) Output saturation voltage, STATUS Leakage current, STATUS Current limit trip point I(sink) = 2.5 mA VI = 5.5 V VIN = 3 V (1) 0.
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www.ti.com SLVS397C − JULY 2001 − REVISED FEBRUARY 2005 TERMINAL FUNCTIONS TERMINAL NAME NO. DESCRIPTION AGND 1 Analog ground. Return for compensation network/output divider, VBIAS capacitor, and RT resistor. Connect PowerPAD to AGND. BOOT 5 Bootstrap output. 0.022 µF to 0.1 µF low-ESR capacitor connected from BOOT to PH generates floating drive for the high-side FET driver. COMP 3 Error amplifier output.
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www.ti.com SLVS397C − JULY 2001 − REVISED FEBRUARY 2005 INTERNAL BLOCK DIAGRAM VBIAS AGND Enable Comparator Falling Edge Deglitch ENA 1.2 V Hysteresis: 0.03 V 2.5 µs VIN UVLO Comparator 2.95 V Hysteresis: 0.16 V VDDQ VIN ILIM Comparator Thermal Shutdown 150°C VIN Leading Edge Blanking Falling and Rising Edge Deglitch VIN REG VBIAS SHUTDOWN 100 ns BOOT 30 mΩ 2.5 µs SS_DIS SHUTDOWN PH REFIN Slow-start (0.
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www.ti.com SLVS397C − JULY 2001 − REVISED FEBRUARY 2005 TYPICAL CHARACTERISTICS DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE IO = 6 A 50 40 IO = 3 A 30 20 10 0 25 85 TJ − Junction Temperature − °C f − Internally Set Oscillator Frequency − kHz VIN = 3.3 V 0 −40 VIN = 5 V 50 IO = 6 A 40 30 IO = 3 A 20 10 0 −40 125 0 25 85 TJ − Junction Temperature − °C Figure 1 125 600 500 400 300 1.255 1.250 1.245 85 1 2 3 4 5 3.
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www.ti.com SLVS397C − JULY 2001 − REVISED FEBRUARY 2005 APPLICATION INFORMATION FEEDBACK CIRCUIT Figure 9 shows the schematic diagram for a typical DDR memory or GTL bus termination application using the TPS54672. The TPS54672 (U1) can provide greater than 6 A of output current. For proper operation, the exposed thermal PowerPAD underneath the integrated circuit package needs to be soldered to the printed-circuit board.
PAGE 9
www.ti.com SLVS397C − JULY 2001 − REVISED FEBRUARY 2005 OUTPUT FILTER The output filter is composed of a 0.56-µH Coilcraft inductor (D01813P−561HC) and two 150-µF Cornell Dublier capacitors (ESRD151M06R). The inductor is a low dc resistance type. The capacitors used are 4 V POSCAP types with a maximum ESR of 0.040 Ω. PCB LAYOUT Figure 10 shows a generalized PCB layout guide for the TPS54672.
PAGE 10
www.ti.com SLVS397C − JULY 2001 − REVISED FEBRUARY 2005 ANALOG GROUND TRACE AGND RT COMPENSATION NETWORK TRACKING VOLTAGE ENA VSENSE COMP REFIN RESISTOR DIVIDER BIAS CAPACITOR PWRGD BOOT CAPACITOR BOOT PH VOUT PH OUTPUT INDUCTOR OUTPUT FILTER CAPACITOR VBIAS VIN EXPOSED POWERPAD AREA VIN PH VIN PH VIN PH VIN PH PGND PH PGND PH PGND PH PGND PH PGND VIN INPUT BYPASS CAPACITOR INPUT BULK FILTER TOPSIDE GROUND AREA VIA to Ground Plane Figure 10.
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www.ti.com SLVS397C − JULY 2001 − REVISED FEBRUARY 2005 LAYOUT CONSIDERATIONS FOR THERMAL PERFORMANCE For operation at full rated load current, the analog ground plane must provide adequate heat dissipating area. A 3 inch by 3 inch plane of 1 ounce copper is recommended, though not mandatory, depending on ambient temperature and airflow. Most applications have larger areas of internal ground plane available, and the PowerPAD should be connected to the largest area available.
PAGE 12
www.ti.com SLVS397C − JULY 2001 − REVISED FEBRUARY 2005 2.8 V. Note that hysteresis in the UVLO comparator and a 2.5-µs rising and falling edge deglitch circuit reduce the likelihood of shutting the device down due to noise on VIN. Enable (ENA) The enable pin, ENA, provides a digital control to enable or disable (shutdown) the TPS54672. An input voltage of 1.4 V or greater ensures that the TPS54672 is enabled. An input of 0.82 V or less ensures that device operation is disabled.
PAGE 13
www.ti.com SLVS397C − JULY 2001 − REVISED FEBRUARY 2005 If the current limit comparator trips for longer than 100 ns, the PWM latch resets before the PWM ramp exceeds the error amplifier output. The high-side FET turns off and low-side FET on to decrease the output current. This process is repeated each cycle in which the current limit comparator is tripped.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS54672PWPR Package Package Pins Type Drawing SPQ HTSSOP 2000 PWP 28 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 16.4 Pack Materials-Page 1 6.9 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.2 1.8 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS54672PWPR HTSSOP PWP 28 2000 367.0 367.0 38.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.