User’s Guide November 2002 PMP EVMs SLVU076
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
EVM IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not considered by TI to be fit for commercial use.
EVM WARNINGS AND RESTRICTIONS It is important to operate this EVM within the input and output voltage range specified in the EVM User’s Guide. Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions concerning the input range, please contact a TI field representative prior to connecting the input power. Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM.
Information About Cautions and Warnings Preface About This Manual This user’s guide describes the characteristics, operation, and the use of the TPS54672EVM−222, TPS54872EVM−222, and TPS54972EVM−222 evaluation modules. It covers all pertinent areas involved to properly use this EVM board along with the devices that it supports. The physical PCB layout, schematic diagram and circuit descriptions are included.
Trademarks The information in a caution or a warning is provided for your protection. Please read each caution and warning carefully. Related Documentation From Texas Instruments To obtain a copy of any of the following TI documents, call the Texas Instruments Literature Response Center at (800) 477 – 8924 or the Product Information Center (PIC) at (972) 644 – 5580. When ordering, identify this manual by its title and literature number. Updated documents can also be obtained through our website at www.ti.
Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Performance Specification Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Modifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents 1−1 2−1 2−2 2−3 2−4 2−5 2−6 2−7 2−8 2−9 2−10 2−11 2−12 2−13 2−14 2−15 2−16 2−17 2−18 2−19 2−20 2−21 2−22 2−23 2−24 2−25 2−26 3−1 3−2 3−3 3−4 3−5 3−6 4−1 vi Frequency Trimming Resistor Selection Graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Measured Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents 1−1 1−2 1−3 1−4 4−1 Input Voltage and Output Current Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TPS54672EVM-222 Performance Specification Summary . . . . . . . . . . . . . . . . . . . . . . . . . . TPS54872EVM-222 Performance Specification Summary . . . . . . . . . . . . . . . . . . . . . . . . . . TPS54972EVM-222 Performance Specification Summary . . . . . . . . . . . . . . . . . . . . . . . . . . TPS54x72EVM-222 Bill of Materials . . . . . . . . .
Chapter 1 This chapter contains background information for the TPS54672, TPS54872, and TPS54972 as well as support documentation for the TPS54672EVM-222, TPS54872EVM-222, and TPS54972EVM-222 evaluation modules (SLVP222). The TPS54x72EVM−222 performance specifications are given, as well as the schematic and bill of material for the TPS54x72EVM−222. Topic Page 1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.
Background 1.1 Background The TPS54x72EVM−222 evaluation modules use the TPS54672, TPS54872, or TPS54972 synchronous buck tracking/termination regulators to provide an output voltage of from 0.46 V to 1.75 V from a nominal 3.3 V input or 0.7 V to 1.75 V for a nominal 5-V input. Rated input voltage and output current range is given in . These evaluation modules are designed to demonstrate the small PCB areas that may be achieved when designing with the TPS54x72 family of regulators.
Performance Specification Summary 1.2 Performance Specification Summary A summary of the TPS54x72EVM−222 performance specifications is provided by Table 1−2, Table 1−3, and Table 1−4. All specifications are given for an an output voltage of 1.25 V and an ambient temperature of 25°C, unless otherwise noted. Table 1−2. TPS54672EVM-222 Performance Specification Summary Specification Test Conditions Min Input voltage range Output voltage set point Output current range Line regulation Load regulation 3.
Modifications Table 1−4. TPS54972EVM-222 Performance Specification Summary Specification Input voltage range Output voltage set point Output current range Line regulation Load regulation Test Conditions Min 3.0 0.42 −9 VI = 3 V to 4 V IO = 4.5 A VI = 5 V, IO = 0 A to 9 A IO = 2.25 A to 6.75 A, tr = 40 µs IO = 6.75 A to 2.
Modifications Figure 1−1. Frequency Trimming Resistor Selection Graph 750 700 Switching Frequency − kHz 650 600 550 500 450 400 350 300 250 60 70 80 90 100 110 120 130 140 150 160 170 180 R − Resistance − kΩ The slow start time is typically 3.6 ms, and is controlled internally. The slow start time cannot be made faster than 3.6 ms. The TPS54x72EVM−222 EVM also supports alternate output filter configurations by means of pads located on the back side of the PCB.
1-6
Chapter 2 This chapter describes how to properly connect, set up, and use the TPS54x72EVM−222 evaluation module. The chapter also includes test results typical for the TPS54x72EVM−222 and covers efficiency, output voltage regulation, load transients, loop response, output ripple, input ripple, and start-up. Topic Page 2.1 Input/Output Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 Efficiency . . . . . . . . . . . . . . . . . . . . . .
Input/Output Connections 2.1 Input/Output Connections The TPS54x72EVM−222 has the following four input/output connections: input, input return, output, and output return. A diagram showing the connection points is shown in Figure 2−1. A power supply capable of supplying 6 A should be connected to J1 through a pair of 20 AWG wires. The load should be connected to J2 through a pair of 16 AWG wires. The maximum load current may be reduced from 9 A if 6 A or 8 A versions of the TPS54x72EVM−222 are used.
Efficiency 2.2 Efficiency The TPS54x72EVM−222 efficiency peaks at load current of about 2 A, and then decreases as the load current increases towards full load. The efficiency shown in Figure 2−2 is for 5-V (TPS54672, TPS54872) and 3.3 V (TPS54972) inputs at an ambient temperature of 25°C. The efficiency is lower at higher ambient temperatures, due to temperature variation in the drain-to-source resistance of the MOSFETs.
Power Dissipation 2.3 Power Dissipation The low junction-to-case thermal resistance of the PWP package, along with a good board layout, allows the TPS54x72EVM−222 EVMs to output full rated load current while maintaining safe junction temperatures. With a 3.3-V input source and a 6-A load, the junction temperture is approximately 60°C, while the case temperature is approximately 55°C. The total circuit losses at 25°C are shown in Figure 2−3. The input voltage for the TPS54972 is 3.
Output Voltage Regulation 2.4 Output Voltage Regulation The output voltage load regulation of the TPS54x72EVM−222 is shown in Figure 2−4, while the output voltage line regulation is shown in Figure 2−5. Measurements are given for an ambient temperature of 25°C. Figure 2−4. Load Regulation OUTPUT VOLTAGE vs OUTPUT CURRENT 1.26 1.258 VO − Output Voltage − V 1.256 1.254 1.252 1.25 TPS54972 1.248 TPS54672 1.246 1.244 1.242 TPS54872 1.24 0 1 2 3 4 5 6 7 IO − Output Current − A 8 9 10 Figure 2−5.
Load Transients 2.5 Load Transients The TPS54x72EVM−222 response to load transients is shown in Figure 2−6, Figure 2−7, and Figure 2−8. The current step is from 25 to 75 percent of maximum rated load. Total peak-to-peak voltage variation is as shown, including ripple and noise on the output. Figure 2−6. Load Transient Response, TPS54672 VO (ac) 50 mV/div IO 2 A/div Time Scale 250 µs/div Figure 2−7.
Load Transients Figure 2−8.
Source-Sink Transient Response 2.6 Source-Sink Transient Response The TPS54x72EVM−222 response to source-sink current transients is shown in Figure 2−9, Figure 2−10, and Figure 2−11. The current step is from –50% to 50% of maximum rated load. Total peak-to-peak voltage variation is as shown, including ripple and noise on the output. Figure 2−9. Source-Sink Current Transient Response, TPS54672 VO (ac) 50 mV/div IO 2 A/div Time Scale 250 µs/div Figure 2−10.
Source-Sink Transient Response Figure 2−11.
Loop Characteristics 2.7 Loop Characteristics The TPS54x72EVM−222 loop respnse characteristics are shown in Figure 2−12 through Figure 2−17. Gain and phase plots are shown for each device at minimum and maximum operating voltage. Figure 2−12.
Loop Characteristics Figure 2−14. Measured Loop Response, TPS54872, VI = 4 V MEASURED LOOP RESPONSE 180 60 VI = 4 V 50 40 150 120 Phase 30 Gain − dB 60 10 30 0 0 −10 −30 −20 −60 −30 −90 −40 −120 −50 −150 −60 100 1k Phase − Degrees 90 Gain 20 −180 1M 10 k 100 k f − Frequency − Hz Figure 2−15.
Loop Characteristics Figure 2−16. Measured Loop Response, TPS54972, VI = 3 V MEASURED LOOP RESPONSE 180 60 VI = 3 V 50 40 120 Phase 20 90 60 Gain 10 30 0 0 Phase − Degrees 30 Gain − dB 150 −10 −30 −20 −60 −30 −90 −40 −120 −50 −150 −60 100 1k 10 k 100 k f − Frequency − Hz −180 1M Figure 2−17.
Output Voltage Ripple 2.8 Output Voltage Ripple The TPS54x72EVM−222 output voltage ripple is shown in Figure 2−18, Figure 2−19, and Figure 2−20 for each device type. The input voltage is 3.3 V for the TPS54672 and TPS54972. The input voltage is 5 V for the TPS54872. Output current for each device is the rated full load. Voltage is measured directly across output capacitors. Figure 2−18. Measured Output Voltage Ripple, TPS54672 VO (ac) 10 mV/div Time Scale 1 µs/div Figure 2−19.
Output Voltage Ripple Figure 2−20.
Input Voltage Ripple 2.9 Input Voltage Ripple The TPS54x72EVM−222 output voltage ripple is shown in Figure 2−21, Figure 2−22, and Figure 2−23 for each device type. The input voltage is 3.3 V for the TPS54672 and TPS54972. The input voltage is 5 V for the TPS54872. Output current for each device is rated full load. Figure 2−21. Input Voltage Ripple, TPS54672 VO (ac) 100 mV/div Time Scale 1 µs/div Figure 2−22.
Input Voltage Ripple Figure 2−23.
Start-Up 2.10 Start-Up The start-up voltage waveform of the TPS54x72EVM−222 is shown in Figure 2−24, Figure 2−25, and Figure 2−26. There is approximately a 3.6-ms delay after the input voltage rises above the 2.9 V (3.8 V for the TPS54872) startup voltage threshold until the output voltage begins to ramp up to the final value of 1.25 V. The output voltage tracks the greater of the internal and external slow start voltages, accounting for the change in ramp rates. Figure 2−24.
Start-Up Figure 2−26. Measured Start-Up Waveform, TPS54972 VI 1 V/div VO 500 mV/div Time Scale 2.
Chapter 3 This chapter provides a description of the TPS54x72EVM−222 board layout and layer illustrations. Topic 3.1 Page Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Layout 3.1 Layout The board layout for the TPS54x72EVM−222 is shown in Figure 3−1 through Figure 3−6. The top side layer of the TPS54x72EVM−222 is laid out in a manner typical of a user application. The bottom layer of the TPS54x72EVM−222 is designed to accommodate an optional alternate output filter configuration. The top and bottom layers are 1.5 oz. copper, while the two internal layers are 0.5 oz. copper. The top layer contains the main power traces for VI, VO, and V(phase).
Layout Figure 3−2. Internal Layer 1 Layout Figure 3−3.
Layout Figure 3−4. Bottom Side Layout (Looking From Top Side) Figure 3−5.
Layout Figure 3−6.
3-6
Chapter 4 The TPS54x72EVM−222 schematic and bill of materials are presented in this chapter. Topic Page 4.1 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Schematic 4.1 Schematic The schematic for the TPS54x72EVM−222 is shown in Figure 4−1. Figure 4−1. TPS54x72EVM−222 Schematic TP2 J1 VI 2 1 GND TP1 R2 10 kΩ TP9 TP3 C4 10 µF U1 TPS54672PWP (1) 28 1 AGND RT 2 27 VSENSE ENA 26 3 COMP REFIN 4 25 STATUS VBIAS 5 24 BOOT VIN 6 23 PH VIN 7 22 PH VIN 8 21 VIN PH 9 20 VIN PH 10 19 PGND PH 11 18 PH PGND 12 17 PGND PH 13 16 PH PGND 14 15 PH PGND C2 470 pF C6 0.047 µF C1 12 pF R3 301 Ω R9 OPEN R1 10 kΩ C3 470 pF 1 2 R5 71.5 kΩ C10 1 µF R6 10 kΩ C13 0.
Bill of Materials 4.2 Bill of Materials The bill of materials for the TPS54x72EVM−222 is shown in Table 4−1. Table 4−1. TPS54x72EVM−222 Bill of Materials Count −001 −002 −003 RefDes Description SIZE MFR Part Number 1 1 1 C1 Capacitor, ceramic, 12 pF, 50 V, C0G, 5% 603 Murata GRM1885C1H120JZ01 1 1 1 C10 Capacitor, ceramic, 1.0 µF, 10 V, X5R, 20% 603 TDK C1608X5R1A105K 1 1 1 C12 Capacitor, ceramic, 1.
Bill of Materials 1 1 1 TP7 Adaptor, 3,5-mm probe clip ( or 131−5031−00) 72900 Tektronix 131−4244−00 1 − − U1 IC, tracking/termination synch. PWM switcher. PWP28 TI TPS54672PWP − 1 − U1 IC, tracking/termination synch. PWM switcher. PWP28 TI TPS54872PWP − − 1 U1 IC, tracking/termination synch. PWM switcher. PWP28 TI TPS54972PWP 1 1 1 − PCB, 3 in. × 3 in. × 0.063 in.
