E ! " # $ % &' " & ( & % User’s Guide September 2003 PMP Systems Power SLVU091
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
EVM IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not considered by TI to be fit for commercial use.
EVM WARNINGS AND RESTRICTIONS It is important to operate this EVM within the input and output voltage ranges specified in the EVM User’s Guide. Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions concerning the input range, please contact a TI field representative prior to connecting the input power. Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM.
Trademarks Preface About This Manual This user’s guide describes the characteristics, operation, and the use of the TPS54973EVM-017 evaluation module. It covers all pertinent areas involved to properly use this EVM board along with the devices that it supports. The physical PCB layout, schematic diagram, and circuit descriptions are included.
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Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Performance Specification Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Modifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents 1−1 2−1 2−2 2−3 2−4 2−5 2−6 2−7 2−8 2−9 2−10 2−11 2−12 2−13 2−14 2−15 3−1 3−2 3−3 3−4 3−5. 3−6 4−1 Frequency Trimming Resistor Selection Graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Measured Efficiency, TPS54973 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 1 This chapter contains background information for the TPS54973 as well as support documentation for the TPS54973EVM-017 evaluation module (HPA0017). The TPS54973EVM-017 performance specifications are given, as well as modifications. Topic Page 1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Performance Specification Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.3 Modifications . . .
Background 1.1 Background The TPS54973EVM−017 evaluation module uses the TPS54973 synchronous buck regulator with disabled sink during startup (DSDS) to provide an output voltage from 0.9 V to 2.5 V from a nominal 3.3-V input. Rated input voltage and output current ranges are listed in Table 1−1. This evaluation module is designed to demonstrate the small PCB areas that may be achieved when designing with the TPS54973 regulator.
Performance Specification Summary 1.2 Performance Specification Summary A summary of the TPS54973EVM−017 performance specifications is provided in Table 1−2. Specifications are given for an input voltage of 3.3 V and an output voltage of 1.8 V unless otherwise specified. The ambient temperature is 25°C for all measurements, unless otherwise noted. The data presented in Table 1−2 was compiled with no precharge on the output (J3 open, no voltage source present on J4).
Modifications 1.3 Modifications The TPS54973EVM-017 is designed to demonstrate the small size that can be attained when designing with the TPS54973, so many of the features which allow for extensive modifications have been omitted from this EVM. 1.3.1 Output Voltage By changing the value of R2, the output voltage can be set to a value in the range of 0.9 V to 2.5 V. The value of R2 for a specific output voltage can be calculated by using Equation 1−1.
Modifications Figure 1−1. Frequency Trimming Resistor Selection Graph 750 700 Switching Frequency − kHz 650 600 550 500 450 400 350 300 250 60 1.3.3 80 100 120 140 R − Resistance − kΩ 160 180 Alternate Output Filters The TPS54973EVM-017 EVM also supports alternate output filter configurations by means of pads located on the back side of the PCB.
Modifications connector terminals, while leaving J3 open. Headers J5 and J6 are provided to select two, three, or four series diodes. Install a jumper across the header to bypass the adjacent diode. Care must be taken to use the correct number of diodes for the application. Under no circumstances can the output voltage be allowed to precharge to a level higher than the preset output voltage. If this condition occurs during startup, the TPS54973 device does not begin switching.
Chapter 2 This chapter describes how to properly connect, setup, and use the TPS54973EVM-017 evaluation module. The chapter also includes test results typical for the TPS54973EVM-017 and covers efficiency, output voltage regulation, load transients, loop response, output ripple, input ripple, and startup. Topic Page 2.1 Input/Output Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 Efficiency . . . . . . . . . . . . . . . . . . . . . . .
Input/Output Connections 2.1 Input/Output Connections The TPS54973EVM−017 has the following three input/output connectors: VIN J2, VOUT J1, and PRECHG_IN J4. A diagram showing the connection points is shown in Figure 2−1. A power supply capable of supplying 8 A should be connected to J2 through a pair of 20 AWG wires. The load should be connected to J1 through a pair of 20 AWG wires. The maximum load current capability should be 9 A. Wire lengths should be minimized to reduce losses in the wires.
Input/Output Connections Figure 2−1.
Efficiency 2.2 Efficiency The TPS54973EVM−017 efficiency peaks at a load current of about 1 A to 2 A and then decreases as the load current increases towards full load. Figure 2−2 shows the efficiency of the TPS54973 at an ambient temperature of 25°C. The efficiency is lower at higher ambient temperatures due to temperature variation in the drain-to-source resistance of the MOSFETs.
Power Dissipation 2.3 Power Dissipation The low junction-to-case thermal resistance of the PWP package, along with a well designed board layout, allows the TPS54973EVM−017 EVM to output full rated load current while maintaining safe junction temperatures. With a 3.3-V input source and a 9-A load, the junction temperature is approximately 60°C, while the case temperature is approximately 55°C. The total circuit losses at 25°C are shown in Figure 2−3. Power dissipaton is shown for an input voltage of 3.3 V.
Output Voltage Regulation 2.4 Output Voltage Regulation The output voltage load regulation of the TPS54973EVM−017 is shown in Figure 2−4, while the output voltage line regulation is shown in Figure 2−5. Measurements are shown for an ambient temperature of 25°C Figure 2−4. Load Regulation OUTPUT VOLTAGE vs OUTPUT CURRENT 0.5 VO − Output Voltage Change − % 0.4 VI = 3.3 V 0.3 0.2 0.1 0 −0.1 −0.2 −0.3 −0.4 −0.5 0 1 2 3 4 5 6 7 IO − Output Current − A 8 9 10 Figure 2−5.
Load Transients 2.5 Load Transients The TPS54973EVM−017 response to load transients is shown in Figure 2−6. The current step is from 25 to 75 percent of maximum rated load. Total peak-to-peak voltage variation is as shown, including ripple and noise on the output. Figure 2−6. Load Transient Response, TPS54973 VO (ac) 50 mV/div IO 2 A/div t − Time − 200 µs/div 2.6 Loop Characteristics The TPS54973EVM−017 loop response characteristics are shown in Figure 2−7 and Figure 2−8.
Output Voltage Ripple Figure 2−8. Measured Loop Response, TPS54973, VI = 4 V MEASURED LOOP RESPONSE 180 Gain − dB 50 Phase 150 40 120 30 90 20 60 30 10 Gain 0 0 −10 −30 −20 −60 −30 −90 −40 −120 −50 −150 −60 100 1k 10 k 100 k f − Frequency − Hz Phase − deg 60 −180 1M 2.7 Output Voltage Ripple The TPS54973EVM−017 output voltage ripple is shown in Figure 2−9. The input voltage is 3.3 V for the TPS54973. Output current is the rated full load of 9 A.
Input Voltage Ripple 2.8 Input Voltage Ripple The TPS54973EVM−017 output voltage ripple is shown in Figure 2−10. The input voltage is 3.3 V for the TPS54973. Output current for each device is the rated full load of 9 A. Figure 2−10.
Start Up 2.9 Start Up The startup voltage waveforms of the TPS54973EVM−017 are shown in Figure 2−11 through Figure 2−15. Figure 2−11 shows the start up waveform with no precharge on the output. When VI reaches the nominal 2.95-V UVLO threshold, the slow start capacitor C5 begins to charge. When the voltage on the SS/ENA pin reaches the enable threshold of 1.2 V, the internal reference begins to ramp up at the slow start rate.
Start Up Figure 2−12. Measured Start Up Waveform, Two Diode Precharge VI 500 mV/div VO 500 mV/div t − Time − 5 ms/div Figure 2−13.
Start Up Figure 2−14. Measured Start Up Waveform, Four Diode Precharge VI 500 mV/div VO 500 mV/div t − Time − 5 ms/div Figure 2−15 shows the start up waveform with the output precharged through four diodes and no load. Compare the precharge level to that in Figure 2−14 to see how start up load current affects the voltage drop across the diodes and the final precharge voltage.
Chapter 3 This chapter provides a description of the TPS54973EVM-017 board layout and layer illustrations. Topic 3.1 Page Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Layout 3.1 Layout The board layout for the TPS54973EVM−017 is shown in Figure 3−1 through Figure 3−6. The topside layer of the TPS54973EVM−017 is laid out in a manner typical of a user application. The bottom layer of the TPS54973EVM−017 is designed to accommodate optional alternate output filter capacitors. The top and bottom layers are 1.5-oz. copper. The top layer contains the main power traces for VI, VO, and Vphase.
Layout Figure 3−2. Internal Layer 2 Figure 3−3.
Layout Figure 3−4. Bottom Side Layout Figure 3−5.
Layout Figure 3−6.
Chapter 4 The TPS54973EVM-017 schematic and bill of materials are presented in this chapter. Topic Page 4.1 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Schematic 4.1 Schematic The schematic for the TPS54973EVM−017 is shown in Figure 4−1. Figure 4−1. TPS54973EVM-017 Schematic U1 TPS54973 R4 28 RT 71.5 kΩ 27 TP9 C5 26 0.047 µF C4 1 µF TP4 R1 R3 10 kΩ 4.02 kΩ R5 C8 1200 pF 10 kΩ R6 VIN 25 4 3 C6 22 VIN 21 VIN 20 SYNCH SS/ENA R2 9.76 kΩ C11 22 µF 22 µF 22 µF PH PH VSENSE BOOT PGND PGND PGND TP5 PGND AGND PGND PGND PwrPad J1 VOUT GND 0Ω 9 8 7 D1 6 5 19 18 17 16 15 PH C3 0.
Bill of Materials 4.2 Bill of Materials The bill of materials for the TPS54973EVM−017 is listed in Table 4−1. Table 4−1. TPS54973EVM-017 Bill of Materials Count Ref Des Description Size MFR Part Number − C1 Capacitor, POSCAP, 220 µF, 10 V, 40 mΩ, 20% 7343 (D) Sanyo 10TPB220M 1 C14 Capacitor, ceramic, 0.1 µF, 25 V, X7R, 10% 603 Std Std 3 C16, C17, C18 Open 62100 6 C2, C9, C10, C11, C12, C13 Capacitor, ceramic, 22 µF, 6.
