Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - DC/DC voltage regulator Boost, Flyback, SEPIC WQFN 16

100

0 0.4 0.8 1.2 1.6 2 2.4

Output Current (A)

Efficiency (%)

= 15 V

= 12 V

= 5 V

OUT

= 24 V

= 600 kHz

G031

TPS55340

VIN

FREQ

COMP

SYNC

PGND

OUT

FREQ

AGND

TPS55340

www.ti.com

SLVSBD4B –MAY 2012–REVISED OCTOBER 2012

Integrated 5-A 40-V Wide Input Range Boost/SEPIC/Flyback DC-DC Regulator

Check for Samples: TPS55340

FEATURES

DESCRIPTION

The TPS55340 is a monolithic non-synchronous

• Internal 5-A, 40-V Low-Side MOSFET Switch

switching regulator with integrated 5-A, 40-V power

• 2.9-V to 32-V Input Voltage Range

switch. It can be configured in several standard

• ±0.7% Reference Voltage

switching-regulator topologies, including boost,

SEPIC and isolated flyback. The device has a wide

• 0.5mA Operating Quiescent Current

input voltage range to support applications with input

• 2.7µA Shutdown Supply Current

voltage from multi-cell batteries or regulated 3.3-V, 5-

• Fixed Frequency Current Mode PWM Control

V, 12-V, and 24-V power rails.

• Frequency Adjustable from 100kHz to 1.2MHz

The TPS55340 regulates the output voltage with

• Synchronization Capability to External Clock

current mode PWM (pulse width modulation) control,

and has an internal oscillator. The switching

• Adjustable Soft-Start Time

frequency of PWM is set by either an external resistor

• Pulse-Skipping for Higher Efficiency at Light

or by synchronizing to an external clock signal. The

Loads

user can program the switching frequency from 100

• Cycle-by-Cycle Current Limit, Thermal

kHz to 1.2 MHz.

Shutdown, and UVLO Protection

The device features a programmable soft-start

• QFN-16 (3mmx3mm) and HTSSOP-14

function to limit inrush current during start-up and has

Packages with PowerPad™

other built-in protection features including cycle-by-

cycle over current limit and thermal shutdown.

• Wide –40°C to 150°C Operating T

Range

The TPS55340 is available in a small 3mm x 3mm

APPLICATIONS

16-pin QFN as well as 14-pin HTSSOP packages

with PowerPad™ for enhanced thermal performance.

• 3.3-V, 5-V, 12-V, 24-V Power Conversion

The 5-A, 40-V TPS55340 Boost Converter in the

• Boost, SEPIC, and Flyback Topologies

HTSSOP-14 package is pin-to-pin compatible with

• Thunderbolt Port, Power Docking for Tablets

the 3-A, 40-V TPS61175 and it extends the maximum

and Portable PCs

input voltage from 18 V to 32 V.

• Industrial Power Systems

• ADSL Modems

TYPICAL APPLICATION (BOOST)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PowerPad is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (38 pages)

PAGE 1
TPS55340 www.ti.com SLVSBD4B – MAY 2012 – REVISED OCTOBER 2012 Integrated 5-A 40-V Wide Input Range Boost/SEPIC/Flyback DC-DC Regulator Check for Samples: TPS55340 FEATURES DESCRIPTION • • • • • • • • • • The TPS55340 is a monolithic non-synchronous switching regulator with integrated 5-A, 40-V power switch. It can be configured in several standard switching-regulator topologies, including boost, SEPIC and isolated flyback.
PAGE 2
TPS55340 SLVSBD4B – MAY 2012 – REVISED OCTOBER 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
PAGE 3
TPS55340 www.ti.com SLVSBD4B – MAY 2012 – REVISED OCTOBER 2012 FUNCTIONAL BLOCK DIAGRAM VIN SW FB Error Amp EN 1.229V Reference COMP PWM Control Ramp Generator Gate Driver Lossless Current Sense S Oscillator SS SYNC FREQ AGND PGND ABSOLUTE MAXIMUM RATINGS (1) over operating temperature range (unless otherwise noted) VALUE UNIT MIN MAX Supply voltages on pin VIN (2) –0.3 34 V Voltage on pin EN (2) –0.3 34 V Voltage on pins FB, FREQ, and COMP (2) –0.
PAGE 4
TPS55340 SLVSBD4B – MAY 2012 – REVISED OCTOBER 2012 www.ti.com THERMAL INFORMATION TPS55340 THERMAL METRIC (1) QFN (16-PINS) HTSSOP (14PINS) θJA Junction-to-ambient thermal resistance 43.3 43.2 θJCtop Junction-to-case (top) thermal resistance 38.7 33.3 θJB Junction-to-board thermal resistance 14.5 28.3 ψJT Junction-to-top characterization parameter 0.4 1.3 ψJB Junction-to-board characterization parameter 14.5 28.1 θJCbot Junction-to-case (bottom) thermal resistance 3.5 3.
PAGE 5
TPS55340 www.ti.com SLVSBD4B – MAY 2012 – REVISED OCTOBER 2012 ELECTRICAL CHARACTERISTICS (continued) Vin=5V, TJ = –40°C to +150°C, unless otherwise noted. Typical values are at TA = 25°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V ENABLE AND REFERENCE CONTROL VEN EN threshold voltage 0.9 1.08 1.30 VENh EN threshold hysteresis EN rising input 0.1 0.16 0.
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TPS55340 SLVSBD4B – MAY 2012 – REVISED OCTOBER 2012 www.ti.com TYPICAL CHARACTERISTICS Vin = 5 V, TA = 25°C (unless otherwise noted) 8 Current Limit Threshold (A) Transconductance (µA/V) 400 380 360 340 320 7 6 5 4 3 2 300 −50 −25 0 25 50 75 Temperature (°C) 100 125 1 −50 150 Figure 1. Error Amplifier Transconductance vs Temperature 125 150 G002 VIN = 3 V Resistance (mΩ) Voltage Reference (V) 100 100 1.228 1.226 1.224 80 60 VIN = 12 V 40 VIN = 5 V 20 1.
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TPS55340 www.ti.com SLVSBD4B – MAY 2012 – REVISED OCTOBER 2012 TYPICAL CHARACTERISTICS (continued) Vin = 5 V, TA = 25°C (unless otherwise noted) 700 3.5 RFREQ = 80 kΩ 3 500 COMP Voltage (V) Frequency (kHz) 600 400 Non-Foldback Foldback 300 200 2.5 1.5 1 100 0 −50 −25 0 25 50 75 Temperature (°C) 100 125 0.5 −50 150 0 25 50 75 Temperature (°C) 100 125 150 G008 Figure 8. COMP Clamp Voltage vs Temperature 2.7 1.3 EN Voltage Rising EN Voltage Falling 1.2 Enable Voltage (V) 2.66 2.
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TPS55340 SLVSBD4B – MAY 2012 – REVISED OCTOBER 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) 8 2.1 7 1.8 Supply Current (mA) Shutdown Current (µA) Vin = 5 V, TA = 25°C (unless otherwise noted) 6 5 4 3 Switching Non-Switching 1.2 0.9 0.6 2 1 −50 −25 0 25 50 75 Temperature (°C) 100 125 150 0.3 −50 −25 G013 Figure 13. Shutdown Current vs Temperature 8 1.5 0 25 50 75 Temperature (°C) 100 125 150 G014 Figure 14.
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TPS55340 www.ti.com SLVSBD4B – MAY 2012 – REVISED OCTOBER 2012 DETAILED DESCRIPTION OPERATION The TPS55340 integrates a 5 A, 40 V low side n-channel MOSFET for boost converter output up to 38V. The TPS55340 regulates the output with current mode PWM (pulse width modulation) control. The PWM control circuitry turns on the switch at the beginning of each oscillator clock cycle. The input voltage is applied across the inductor and stores the energy as inductor current ramps up.
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TPS55340 SLVSBD4B – MAY 2012 – REVISED OCTOBER 2012 www.ti.com SLOPE COMPENSATION The TPS55340 has internal slope compensation to prevent sub-harmonic oscillations. The sensed current slope of boost converter can be expressed as Equation 4: V Sn = IN ´ RSENSE (4) L The slope compensation dv/dt can be calculated using Equation 5. 0.32 V RFREQ 0.
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TPS55340 www.ti.com SLVSBD4B – MAY 2012 – REVISED OCTOBER 2012 MINIMUM ON TIME AND PULSE SKIPPING The TPS55340 PWM control system has a minimum PWM pulse width of 77ns (typical). This minimum on-time determines the minimum duty cycle of the PWM, for any set switching frequency. When the voltage regulation loop of the TPS55340 requires a minimum on-time pulse width less than 77ns, the IC enters pulse-skipping mode.
PAGE 12
TPS55340 SLVSBD4B – MAY 2012 – REVISED OCTOBER 2012 www.ti.com DESIGN GUIDE-STEP-BY-STEP DESIGN PROCEDURE OF BOOST CONVERTER The following section provides a step-by-step design approach for configuring the TPS55340 as a voltage regulating boost converter, as shown in Figure 15. When configured as SEPIC or flyback converter, a different design approach is required. A design example of SEPIC converter is provided in the next section. 100 pF Figure 15.
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TPS55340 www.ti.com SLVSBD4B – MAY 2012 – REVISED OCTOBER 2012 DETERMINING THE DUTY CYCLE The input to output voltage conversion ratio of the TPS55340 is limited by the worst case maximum duty cycle of 89% and the minimum duty cycle which is determined by the minimum on-time of 77 ns and the switching frequency. The minimum duty cycle can be estimated with Equation 7. With a 600 kHz switching frequency the minimum duty cycle is 4%.
PAGE 14
TPS55340 SLVSBD4B – MAY 2012 – REVISED OCTOBER 2012 www.ti.com The minimum value of the inductor should be able to meet inductor current ripple (ΔIL) requirement at worst case. In a boost converter, maximum inductor current ripple occurs at 50% duty cycle. For the applications where duty cycle is always smaller or larger than 50%, Equation 12 should be used with the duty cycle closest to 50% and corresponding input voltage to calculate the minimum inductance.
PAGE 15
TPS55340 www.ti.com SLVSBD4B – MAY 2012 – REVISED OCTOBER 2012 COMPUTING THE MAXIMUM OUTPUT CURRENT The over-current limit for the integrated power MOSFET limits the maximum input current and thus the maximum input power for a given input voltage. Maximum output power is less than maximum input power due to power conversion losses. Therefore, the current limit setting, input voltage, output voltage and efficiency can all change maximum current output (IOUTmax).
PAGE 16
TPS55340 SLVSBD4B – MAY 2012 – REVISED OCTOBER 2012 www.ti.com SELECTING THE INPUT CAPACITORS (C2, C7) At least 4.7µF of ceramic input capacitance is recommended. Additional input capacitance may be required to meet ripple and/or transient requirements. High quality ceramic, type X5R or X7R are recommended to minimize capacitance variations over temperature. The capacitor must also have an RMS current rating greater than the maximum RMS input current of the TPS55340 calculated with Equation 22.
PAGE 17
TPS55340 www.ti.com SLVSBD4B – MAY 2012 – REVISED OCTOBER 2012 The following equations summarize the loop equations for the TPS55340 configured as a CCM boost converter. They include the power stage output pole (ƒOUT) and the right-half-plane zero (ƒRHPZ) of a boost converter calculated with Equation 27 and Equation 28 respectively. When calculating ƒOUT it is important to include the derating of ceramic output capacitors. In the example with an estimated 10.
PAGE 18
TPS55340 SLVSBD4B – MAY 2012 – REVISED OCTOBER 2012 CFF = www.ti.com 1 2p ´ R1´ ¦ ZFF ´ VREF VOUT (37) where RESR is the ESR of the output capacitor. If a network measurement tool is available, the most accurate compensation design can be achieved following this procedure. The power stage frequency response is first measured using a network analyzer at the minimum 5 V input and maximum 800 mA load. This measurement is shown in Figure 16.
PAGE 19
TPS55340 www.ti.com SLVSBD4B – MAY 2012 – REVISED OCTOBER 2012 100 95 VOUT (ac coupled) = 500mV/div Efficiency (%) 90 85 80 75 IOUT = 200mA/div 70 65 60 VIN = 5 V VIN = 12 V 55 50 0 0.4 0.8 1.2 Output Current (A) 1.6 2 Time - 1ms/div G017 Figure 17. Efficiency vs Output Current IL = 1A/div Figure 18. Load Transient Response IL = 1A/div VOUT (ac coupled) = 100mV/div VOUT (ac coupled) = 10mV/div SW = 20V/div SW = 20V/div Time - 1ms/div Time - 1ms/div Figure 19.
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TPS55340 SLVSBD4B – MAY 2012 – REVISED OCTOBER 2012 www.ti.com 180 60 40 120 20 60 0 0 −60 −20 −40 −60 100 Phase (°) Gain (dB) IOUT = 800 mA 5 V Gain 5 V Phase 15 V Gain 15 V Phase −120 1k 10k Frequency (Hz) −180 100k G023 Figure 23.
PAGE 21
TPS55340 www.ti.com SLVSBD4B – MAY 2012 – REVISED OCTOBER 2012 DESIGN GUIDE-STEP-BY-STEP DESIGN PROCEDURE OF SEPIC CONVERTER Lb TP4 VIN La VIN 6-18V 12V, 1A 1 TP5 49.9 TP2 VIN 86.6k SYNC SYNC 1 TP3 Not Populated Figure 24. SEPIC Converter Application Schematic The following parameters are used for a SEPIC converter design. These calculations are performed only for CCM operation, and the use of a coupled inductor is assumed. Table 2.
PAGE 22
TPS55340 SLVSBD4B – MAY 2012 – REVISED OCTOBER 2012 www.ti.com SELECTING THE INDUCTOR (L1) With an estimated 85% efficiency, the input current is calculated with Equation 9 to be 2.35 A. With KIND of 0.3 and the maximum 18 V input the minimum inductance is calculated to be 10.5µH using Equation 41. The nearest standard value of 12µH is used. As mentioned previously, this equation assumes a coupled inductor is used.
PAGE 23
TPS55340 www.ti.com VIripple = ICIrms = SLVSBD4B – MAY 2012 – REVISED OCTOBER 2012 DIL 4 ´ ¦ SW ´ CIN (49) DIL 12 (50) SELECTING THE SCHOTTKY DIODE (D1) The selected diode must have a minimum breakdown voltage (VBR) calculated with Equation 51 which is 30.5 V in this design. The average current rating is recommended to be greater than the maximum output current. With the maximum 18 V input, average current is calculated to be 2.6 A using Equation 17.
PAGE 24
TPS55340 SLVSBD4B – MAY 2012 – REVISED OCTOBER 2012 www.ti.com 180 60 6 V Input Gain 6 V Input Phase 40 120 0 0 Phase (°) 60 Gain (dB) 20 −20 −60 −40 −120 −60 100 1k −180 100k 10k Frequency (Hz) G025 Figure 25. SEPIC Power Stage Gain and Phase As there are no changes in the transconductance amplifier, the equations used to calculate the external compensation components in a boost design can be used in the SEPIC design.
PAGE 25
TPS55340 SLVSBD4B – MAY 2012 – REVISED OCTOBER 2012 60 180 40 120 20 60 0 0 −60 −20 −40 −60 100 Phase (°) Gain (dB) www.ti.com 6 V Gain 6 V Phase 18 V Gain 18 V Phase −120 1k 10k Frequency (Hz) −180 100k G030 Figure 30.
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TPS55340 SLVSBD4B – MAY 2012 – REVISED OCTOBER 2012 www.ti.com REVISION HISTORY Changes from Original (May 2012) to Revision A Page • Added PWP package ............................................................................................................................................................ 1 • Added HTSSOP-14 package to FEATURES ........................................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 25-Oct-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) TPS55340PWPR HTSSOP PWP 14 2000 330.0 12.4 TPS55340RTER WQFN RTE 16 3000 330.0 TPS55340RTET WQFN RTE 16 250 180.0 6.9 5.6 1.6 8.0 12.0 Q1 12.4 3.3 3.3 1.1 8.0 12.0 Q2 12.4 3.3 3.3 1.1 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 25-Oct-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS55340PWPR HTSSOP PWP 14 2000 367.0 367.0 35.0 TPS55340RTER WQFN RTE 16 3000 367.0 367.0 35.0 TPS55340RTET WQFN RTE 16 250 210.0 185.0 35.
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