Datasheet

TPS56221
SLUSAH5B –MARCH 2011–REVISED SEPTEMBER 2012 www.ti.com
An overcurrent (OC) condition is detected by sensing voltage drop across the low-side FET and across the high-
side FET. If the voltage drop across either FET exceeds OC threshold, a count increments one count. If no OC
condition is detected on either FET, the fault counter decrements by one counter. If three OC pulses are
summed, a fault condition is declared which cycles the soft-start function in a hiccup mode. Hiccup mode is
defined as four dummy soft-start timeouts followed by a real one if overcurrent condition is encountered during
normal operation; or five dummy soft-start timeouts followed by a real one if overcurrent condition occurs from
the beginning during start. This cycle continues indefinitely until the fault condition is removed.
Switching Node (SW)
The SW pin connects to the switching node of the power conversion stage. It acts as the return path for the
highside gate driver. When configured as a synchronous buck stage, the voltage swing on SW normally
traverses from below ground to well above the input voltage. Parasitic inductance in the high-side FET and the
output capacitance (COSS) of both power FETs form a resonant circuit that can produce high frequency ( > 100
MHz) ringing on this node. The voltage peak of this ringing, if not controlled, can be significantly higher than the
input voltage. Ensure that the peak ringing amplitude does not exceed the absolute maximum rating limit for the
pin.
In many cases, a series resistor and capacitor snubber network connected from the switching node to PGND can
be helpful in damping the ringing and decreasing the peak amplitude. Provide provisions for snubber network
components in the layout of the printed circuit board. If testing reveals that the ringing amplitude at the SW pin
exceeds the limit, then include snubber components.
Placing a BOOT resistor with a value between 5 Ω and 10 Ω in series with the BOOT capacitor slows down the
turn-on of the high-side FET and can help to reduce the peak ringing at the switching node as well.
Input Undervoltage Lockout (UVLO)
The TPS56221 has fixed input under-voltage lockout (UVLO). In order for the device to turn on, the following
conditions must be met:
• the EN/SS pin voltage must be greater than V
IH
• the input voltage must exceed UVLO on voltage V
UVLO
The UVLO has a minimum of 500 mV hysteresis built-in.
Pre-Bias Startup
The TPS56221 contains a unique circuit to prevent current from being pulled from the output during startup in the
condition the output is pre-biased. There are no PWM pulses until the internal soft-start voltage rises above the
error amplifier input (FB pin), if the output is pre-biased. Once the soft-start voltage exceeds the error amplifier
input, the controller slowly initiates synchronous rectification by starting the synchronous rectifier with a narrow
on time. It then increments the on-time on a cycle-by-cycle basis until it coincides with the time dictated by (1-D),
where D is the duty cycle of the converter.
This approach prevents the sinking of current from a pre-biased output, and ensures the output voltage startup
and ramp to regulation is smooth and controlled.
Power Good
The TPS56221 provides an indication that output is good for the converter. This is an open drain signal and pulls
low when any condition exists that would indicate that the output of the supply might be out of regulation. These
conditions include:
• V
FB
is more than ±12.5% from nominal
• soft-start is active
• a short circuit condition has been detected
NOTE
When there is no power to the device, PGOOD is not able to pull close to GND if an
auxiliary supply is used for the power good indication. In this case, a built in resistor
connected from drain to gate on the PGOOD pull down device makes the PGOOD pin
look approximately like a diode to GND.
12 Copyright © 2011–2012, Texas Instruments Incorporated
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