Datasheet

T
I
EXAS
NSTRUMENTS
TPS56221
www.ti.com SLUSAH5B –MARCH 2011–REVISED SEPTEMBER 2012
Layout Recommendations
• Place input capacitors next to the VIN pin and on the same side as the device. Use wide and short traces or
copper planes for the connection from the VIN pin to the input capacitor and from the input capacitor to the
power pad of the device.
• Place the BP decoupling capacitor close to the BP pin and on the same side as the device in order to avoid
the use of vias. Use wide and short traces for the connection from the BP pin to the capacitor and from the
capacitor to the power pad. If vias are not evitable, use at least three vias to reduce the parasitic inductance.
• Include a Kelvin VDD connection, or separate from VIN connection (bypass input capacitors); add a
placeholder for a filter resistor between the VDD pin and the input bus. Place the VDD decoupling capacitor
near the VDD pin and on the same side as the device to avoid the use of vias. Use wide and short traces for
the connection from the VDD pin to the capacitor and from the capacitor to the power pad of the device. If
vias are not avoidable, use at least three vias to reduce the parasitic inductance.
• Maintain the FB trace away from BOOT and SW traces.
• Minimize the area of switch node.
• Use a single ground.Do not use separate signal and power ground.
• Use 3 × 7 thermal vias as suggested in the LAND PATTERN DATA section of this datasheet.
EVM Layout
The TPS56221EVM layout is shown in Figure 24 through Figure 29 for reference.
Figure 24. TPS56221EVM Top Assembly Drawing Figure 25. TPS56221EVM Bottom Assembly
(Top view) Drawing (Bottom view)
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