Datasheet

COMP
FB
GND
1
2
3
4
5
6
7
8
9
10
11 12
13
14
15
16
17
GND
(Thermal Pad)
18
19
20
21
22
BOOT
EN/SS
VDD
GND
SW
SW
SW
SW
SW
SW
PGD
BP
ILIM
VIN
VIN
VIN
VIN
VIN
VIN
TPS56221
www.ti.com SLUSAH5B –MARCH 2011–REVISED SEPTEMBER 2012
DEVICE INFORMATION
DQP PACKAGE
PQFN-22
(TOP VIEW)
Note: The thermal pad is also an electrical ground connection.
PIN FUNCTIONS
PIN I/O DESCRIPTION
NAME NO.
Gate drive voltage for the high-side FET. A 100-nF capacitor (typical) must be connected between this pin
BOOT 4 O and the SW pin. To reduce a voltage spike at SW, a BOOT resistor between 5 Ω to 10 Ω may be placed in
series with the BOOT capacitor to slow down turn-on of the high-side FET.
Output bypass for the internal regulator. Connect a low-ESR bypass ceramic capacitor of 1 µF or greater
BP 19 O
from this pin to GND.
Output of the error amplifier and connection node for loop feedback components. Optionally, a 40.2 kΩ
COMP 1 O resistor from this pin to GND sets switching frequency to 300KHz instead of the default value of 500KHz;
while a 13.3 kΩ resistor from this pin to GND sets switching frequency to 1 MHz.
Logic-level input starts or stops the controller via an external user command. Allowing this pin to float turns
the controller on. Pulling this pin low disables the controller. This is also the soft-start programming pin. A
capacitor connected from this pin to GND programs the soft-start time. The capacitor is charged with an
EN/SS 21 I internal current source of 10 µA. The resulting voltage ramp of this pin is also used as a second non-
inverting input to the error amplifier after a 0.8 V (typical) level shift downwards. Output regulation is
controlled by the internal level shifted voltage ramp until that voltage reaches the internal reference voltage
of 600 mV. The voltage ramp of this pin reaches 1.4 V (typical).
Inverting input to the error amplifier. In normal operation, the voltage on this pin is equal to the internal
FB 2 I
reference voltage.
3 –
GND Ground reference for the device
5
Ground reference for the device. This is also the thermal pad used to conduct heat from the device. This
Thermal connection serves two purposes. The first is to provide an electrical ground connection for the device. The
GND –
Pad second is to provide a low thermal impedance path from the device die to the PCB. This pad should be tied
externally to a ground plane.
ILIM 18 I A resistor connected from this pin to GND sets the overcurrent threshold for the device (the low-side FET).
PGD 22 O Open drain power good output.
6
7
8
Switching node of the power conversion stage. Sense line for the adaptive anti-cross conduction circuitry.
SW I
Acts as the common connection for the flying high-side FET driver.
9
10
11
Power input to the controller. A low-ESR bypass ceramic capacitor of 1 µF should be connected from this
VDD 20 I
pin close to GND.
Copyright © 2011–2012, Texas Instruments Incorporated 5
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