Datasheet

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VIN

GND

BOOT

VSENSE

COMP

TPS57040-Q1

RT /CLK

SS /TR

PWRGD

EFFICIENCY

LOADCURRENT

0 0.1 0.2 0.3 0.4

LoadCurrent- A

Efficiency-%

100

0.5

V =12V,

V =5.0V,

f =700kHz

TPS57040-Q1

www.ti.com

SLVSAP4C –DECEMBER 2010–REVISED OCTOBER 2012

0.5-A 42-V STEP-DOWN SWIFT™ DC/DC CONVERTER WITH Eco-mode™

Check for Samples: TPS57040-Q1

FEATURES

• Qualified for Automotive Applications

• Adjustable Undervoltage Lockout Voltage and

Hysteresis

• 3.5-V to 42-V Input Voltage Range

• 0.8-V Internal Voltage Reference

• 200-mΩ High-Side MOSFET

• Supported by SwitcherPro™ Software Tool

• High Efficiency at Light Loads with a Pulse

(http://focus.ti.com/docs/toolsw/folders/print/s

Skipping Eco-mode™ Control Scheme

witcherpro.html)

• 116-μA Operating Quiescent Current

• For SWIFT™ Documentation, See the TI

• 1.5-μA Shutdown Current

Website at http://www.ti.com/swift

• 100-kHz to 2.5-MHz Switching Frequency

• Synchronizes to External Clock

APPLICATIONS

• Adjustable Slow Start/Sequencing

• 12-V and 24-V Industrial and Commercial Low

• Undervoltage and Overvoltage Power-good

Power Systems

Output

• Aftermarket Auto Accessories: Video, GPS,

Entertainment

DESCRIPTION

The TPS57040-Q1 device is a 42-V 0.5-A step-down regulator with an integrated high-side MOSFET. Current

mode control provides simple external compensation and flexible component selection. A low-ripple pulse-skip

mode reduces the no load, input supply current to 116 μA. Using the enable pin, shutdown supply current is

reduced to 1.5 μA, when the enable pin is low.

Undervoltage lockout is internally set at 2.5 V, but can be increased using the enable pin. The output voltage

startup ramp is controlled by the slow start pin that can also be configured for sequencing/tracking. An open

drain power-good signal indicates the output is within 92% to 109% of its nominal voltage.

A wide switching frequency range allows efficiency and external component size to be optimized. Frequency fold

back and thermal shutdown protects the part during an overload condition.

The TPS57040-Q1 is available in a 10-pin thermally enhanced MSOP PowerPAD™ package (DGQ) and a 10-

pin SON package (DRC).

SIMPLIFIED SCHEMATIC

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2Eco-mode, SwitcherPro, SWIFT, PowerPAD are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (55 pages)

PAGE 1
TPS57040-Q1 www.ti.com SLVSAP4C – DECEMBER 2010 – REVISED OCTOBER 2012 0.5-A 42-V STEP-DOWN SWIFT™ DC/DC CONVERTER WITH Eco-mode™ Check for Samples: TPS57040-Q1 FEATURES 1 • • • • 2 • • • • • • Qualified for Automotive Applications 3.5-V to 42-V Input Voltage Range 200-mΩ High-Side MOSFET High Efficiency at Light Loads with a Pulse Skipping Eco-mode™ Control Scheme 116-μA Operating Quiescent Current 1.5-μA Shutdown Current 100-kHz to 2.
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TPS57040-Q1 SLVSAP4C – DECEMBER 2010 – REVISED OCTOBER 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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TPS57040-Q1 www.ti.com SLVSAP4C – DECEMBER 2010 – REVISED OCTOBER 2012 THERMAL INFORMATION TPS54040-Q1 THERMAL METRIC (1) (2) θJA DGQ DRC 10 PINS 10 PINS 62.5 56.5 Junction-to-ambient thermal resistance (standard board) (3) θJA Junction-to-ambient thermal resistance (custom board) 57 61.5 θJCtop Junction-to-case (top) thermal resistance 83 52.1 θJB Junction-to-board thermal resistance 28 20.6 ψJT Junction-to-top characterization parameter 1.7 0.
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TPS57040-Q1 SLVSAP4C – DECEMBER 2010 – REVISED OCTOBER 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) TJ = –40°C to 150°C, VIN = 3.5 to 42V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 0.6 0.
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TPS57040-Q1 www.ti.com SLVSAP4C – DECEMBER 2010 – REVISED OCTOBER 2012 DEVICE INFORMATION PIN CONFIGURATION DRC PACKAGE (TOP VIEW) DGQ PACKAGE (TOP VIEW) BOOT VIN EN SS/TR RT/CLK 10 1 2 3 4 Thermal Pad (11) 5 9 8 7 6 PH GND COMP VSENSE PWRGD BOOT VIN EN SS/TR RT/CLK 1 10 PH 2 9 GND COMP VSENSE PWRGD 3 4 5 Thermal Pad (11) 8 7 6 PIN FUNCTIONS PIN I/O DESCRIPTION NAME NO. BOOT 1 O A bootstrap capacitor is required between BOOT and PH.
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TPS57040-Q1 SLVSAP4C – DECEMBER 2010 – REVISED OCTOBER 2012 www.ti.
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TPS57040-Q1 www.ti.com SLVSAP4C – DECEMBER 2010 – REVISED OCTOBER 2012 TYPICAL CHARACTERISTICS VOLTAGE REFERENCE vs JUNCTION TEMPERATURE 0.816 VI = 12 V VI = 12 V 375 Vref - Voltage Reference - V RDSON - Static Drain-Source On-State Resistance - mW ON RESISTANCE vs JUNCTION TEMPERATURE 500 BOOT-PH = 3 V 250 BOOT-PH = 6 V 125 0 -50 0.808 0.800 0.792 0.784 -50 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 -25 0 150 25 50 75 100 TJ - Junction Temperature - °C 125 150 Figure 1.
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TPS57040-Q1 SLVSAP4C – DECEMBER 2010 – REVISED OCTOBER 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) EA TRANSCONDUCTANCE DURING SLOW START vs JUNCTION TEMPERATURE EA TRANSCONDUCTANCE vs JUNCTION TEMPERATURE 150 40 VI = 12 V VI = 12 V 130 gm - mA/V gm - mA/V 30 110 90 20 70 10 -50 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 50 -50 150 -25 0 25 50 75 100 125 150 TJ - Junction Temperature - °C Figure 7. Figure 8.
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TPS57040-Q1 www.ti.com SLVSAP4C – DECEMBER 2010 – REVISED OCTOBER 2012 TYPICAL CHARACTERISTICS (continued) SS/TR DISCHARGE CURRENT vs JUNCTION TEMPERATURE SWITCHING FREQUENCY vs VSENSE 120 100 VI = 12 V VI = 12 V, TJ = 25°C 80 % of Nominal fsw II(SS/TR) - mA 115 110 60 40 105 20 100 -50 0 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 150 0 SHUTDOWN SUPPLY CURRENT vs INPUT VOLTAGE (Vin) 2 TJ = 25°C I(VIN) - mA 1.5 1 0.5 1 0.
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TPS57040-Q1 SLVSAP4C – DECEMBER 2010 – REVISED OCTOBER 2012 www.ti.
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TPS57040-Q1 www.ti.com SLVSAP4C – DECEMBER 2010 – REVISED OCTOBER 2012 OVERVIEW The TPS57040-Q1 device is a 42-V, 0.5-A, step-down (buck) regulator with an integrated high side n-channel MOSFET. To improve performance during line and load transients the device implements a constant frequency, current mode control which reduces output capacitance and simplifies external frequency compensation design.
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TPS57040-Q1 SLVSAP4C – DECEMBER 2010 – REVISED OCTOBER 2012 www.ti.com DETAILED DESCRIPTION Fixed Frequency PWM Control The TPS57040-Q1 uses an adjustable fixed frequency, peak current mode control. The output voltage is compared through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives the COMP pin. An internal oscillator initiates the turn on of the high side power switch. The error amplifier output is compared to the high side power switch current.
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TPS57040-Q1 www.ti.com SLVSAP4C – DECEMBER 2010 – REVISED OCTOBER 2012 DETAILED DESCRIPTION (continued) VOUT(ac) IL PH Figure 25. Pulse Skip Mode Operation Low Dropout Operation and Bootstrap Voltage (BOOT) The TPS57040-Q1 has an integrated boot regulator, and requires a small ceramic capacitor between the BOOT and PH pins to provide the gate drive voltage for the high side MOSFET. The BOOT capacitor is refreshed when the high side MOSFET is off and the low-side diode conducts.
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TPS57040-Q1 SLVSAP4C – DECEMBER 2010 – REVISED OCTOBER 2012 www.ti.com DETAILED DESCRIPTION (continued) voltage is greater than 2.1 V, at which point the BOOT UVLO threshold is exceeded, and the device starts switching again until the desired output voltage is reached. This operating condition persists until the input voltage and/or the load current increases.
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TPS57040-Q1 www.ti.com SLVSAP4C – DECEMBER 2010 – REVISED OCTOBER 2012 DETAILED DESCRIPTION (continued) Enable and Adjusting Undervoltage Lockout The TPS57040-Q1 is disabled when the VIN pin voltage falls below 2.5 V. If an application requires a higher undervoltage lockout (UVLO), use the EN pin as shown in Figure 28 to adjust the input voltage UVLO by using the two external resistors.
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TPS57040-Q1 SLVSAP4C – DECEMBER 2010 – REVISED OCTOBER 2012 www.ti.
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TPS57040-Q1 www.ti.com SLVSAP4C – DECEMBER 2010 – REVISED OCTOBER 2012 DETAILED DESCRIPTION (continued) Slow Start/Tracking Pin (SS/TR) The TPS57040-Q1 effectively uses the lower voltage of the internal voltage reference or the SS/TR pin voltage as the power-supply's reference voltage and regulates the output accordingly. A capacitor on the SS/TR pin to ground implements a slow start time. The TPS57040-Q1 has an internal pullup current source of 2 μA that charges the external slow start capacitor.
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TPS57040-Q1 SLVSAP4C – DECEMBER 2010 – REVISED OCTOBER 2012 www.ti.com DETAILED DESCRIPTION (continued) Sequencing Many of the common power supply sequencing methods can be implemented using the SS/TR, EN and PWRGD pins. The sequential method can be implemented using an open drain output of a power on reset pin of another device. The sequential method is illustrated in Figure 31 using two TPS57040-Q1 devices.
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TPS57040-Q1 www.ti.com SLVSAP4C – DECEMBER 2010 – REVISED OCTOBER 2012 DETAILED DESCRIPTION (continued) Figure 33 shows a method for ratio-metric start up sequence by connecting the SS/TR pins together. The regulator outputs will ramp up and reach regulation at the same time. When calculating the slow start time the pull up current source must be doubled in Equation 6. Figure 34 shows the results of Figure 33.
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TPS57040-Q1 SLVSAP4C – DECEMBER 2010 – REVISED OCTOBER 2012 www.ti.com DETAILED DESCRIPTION (continued) deltaV = Vout1 - Vout2 R1 > 2800 ´ Vout1 - 180 ´ deltaV (9) (10) EN EN VOUT1 VOUT1 VOUT2 Figure 36. Ratiometric Startup With VOUT2 Leading VOUT1 VOUT2 Figure 37. Ratiometric Startup With VOUT1 Leading VOUT2 EN VOUT1 VOUT2 Figure 38.
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TPS57040-Q1 www.ti.com SLVSAP4C – DECEMBER 2010 – REVISED OCTOBER 2012 DETAILED DESCRIPTION (continued) Constant Switching Frequency and Timing Resistor (RT/CLK Pin) The switching frequency of the TPS57040-Q1 is adjustable over a wide range from approximately 100 kHz to 2500 kHz by placing a resistor on the RT/CLK pin. The RT/CLK pin voltage is typically 0.5 V and must have a resistor to ground to set the switching frequency.
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TPS57040-Q1 SLVSAP4C – DECEMBER 2010 – REVISED OCTOBER 2012 www.ti.com DETAILED DESCRIPTION (continued) Selecting the Switching Frequency The switching frequency that is selected should be the lower value of the two equations, Equation 12 and Equation 13. Equation 12 is the maximum switching frequency limitation set by the minimum controllable on time. Setting the switching frequency above this value will cause the regulator to skip switching pulses.
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TPS57040-Q1 www.ti.com SLVSAP4C – DECEMBER 2010 – REVISED OCTOBER 2012 DETAILED DESCRIPTION (continued) How to Interface to RT/CLK Pin The RT/CLK pin can be used to synchronize the regulator to an external system clock. To implement the synchronization feature connect a square wave to the RT/CLK pin through the circuit network shown in Figure 42. The square wave amplitude must transition lower than 0.5 V and higher than 2.
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TPS57040-Q1 SLVSAP4C – DECEMBER 2010 – REVISED OCTOBER 2012 www.ti.com DETAILED DESCRIPTION (continued) PH PH EXT EXT IL IL Figure 43. Plot of Synchronizing in CCM Figure 44. Plot of Synchronizing in DCM PH EXT IL Figure 45. Plot of Synchronizing in PSM Power-good (PWRGD Pin) The PWRGD pin is an open drain output. Once the VSENSE pin is between 94% and 107% of the internal voltage reference the PWRGD pin is deasserted and the pin floats.
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TPS57040-Q1 www.ti.com SLVSAP4C – DECEMBER 2010 – REVISED OCTOBER 2012 DETAILED DESCRIPTION (continued) The PWRGD pin is pulled low when the VSENSE is lower than 92% or greater than 109% of the nominal internal reference voltage. Also, the PWRGD is pulled low, if the UVLO or thermal shutdown are asserted or the EN pin pulled low.
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TPS57040-Q1 SLVSAP4C – DECEMBER 2010 – REVISED OCTOBER 2012 www.ti.com DETAILED DESCRIPTION (continued) PH VO Power Stage gmps 1.9 A/V a b R1 RESR RL COMP c 0.8 V CO R3 C2 RO VSENSE gmea 97 mA/V C1 COUT R2 Figure 46. Small Signal Model for Loop Response Simple Small Signal Model for Peak Current Mode Control Figure 47 describes a simple small signal model that can be used to understand how to design the frequency compensation.
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TPS57040-Q1 www.ti.com SLVSAP4C – DECEMBER 2010 – REVISED OCTOBER 2012 DETAILED DESCRIPTION (continued) VO Adc VC RESR fp RL gmps COUT fz Figure 47.
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TPS57040-Q1 SLVSAP4C – DECEMBER 2010 – REVISED OCTOBER 2012 www.ti.com DETAILED DESCRIPTION (continued) VO R1 VSENSE gmea Type 2A COMP Type 2B Type 1 Vref R2 RO R3 CO C2 C1 R3 C2 C1 Figure 48. Types of Frequency Compensation Aol A0 P1 Z1 P2 A1 BW Figure 49.
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TPS57040-Q1 www.ti.
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TPS57040-Q1 SLVSAP4C – DECEMBER 2010 – REVISED OCTOBER 2012 www.ti.com APPLICATION INFORMATION Design Guide — Step-By-Step Design Procedure This example details the design of a high frequency switching regulator design using ceramic output capacitors. A few parameters must be known in order to start the design process. These parameters are typically determined at the system level. For this example, we will start with the following known parameters: Output Voltage 5V Transient Response 0 to 1.
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TPS57040-Q1 www.ti.com SLVSAP4C – DECEMBER 2010 – REVISED OCTOBER 2012 Output Inductor Selection (LO) To calculate the minimum value of the output inductor, use Equation 28. KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. The inductor ripple current will be filtered by the output capacitor.
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TPS57040-Q1 SLVSAP4C – DECEMBER 2010 – REVISED OCTOBER 2012 www.ti.com to see the change in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor must be sized to supply the extra current to the load until the control loop responds to the load change. The output capacitance must be large enough to supply the difference in current for 2 clock cycles while only allowing a tolerable amount of droop in the output voltage.
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TPS57040-Q1 www.ti.com SLVSAP4C – DECEMBER 2010 – REVISED OCTOBER 2012 V RESR < ORIPPLE IRIPPLE Icorms = (35) Vout ´ (Vin max - Vout) 12 ´ Vin max ´ Lo ´ ¦ sw (36) Catch Diode The TPS57040-Q1 requires an external catch diode between the PH pin and GND. The selected diode must have a reverse voltage rating equal to or greater than Vinmax. The peak current rating of the diode must be greater than the maximum inductor current. The diode should also have a low forward voltage.
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TPS57040-Q1 SLVSAP4C – DECEMBER 2010 – REVISED OCTOBER 2012 Icirms = Iout ´ Vout ´ Vin min www.ti.com (Vin min - Vout ) Vin min (38) Iout max ´ 0.25 ΔVin = Cin ´ ¦ sw (39) Table 1. Capacitor Types VENDOR VALUE (μF) 1 to 2.2 Murata 1 to 4.7 1 1 to 2.2 1 10 1.8 Vishay 1 to 1.2 1 to 3.9 1 to 1.8 1 to 2.2 TDK 1.5 to 6.8 1 to 2.2 1 to 3.3 1 to 4.7 AVX 1 1 to 4.7 1 to 2.
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TPS57040-Q1 www.ti.com SLVSAP4C – DECEMBER 2010 – REVISED OCTOBER 2012 Undervoltage Lock Out Set Point The undervoltage lock out (UVLO) can be adjusted using an external voltage divider on the EN pin of the TPS57040-Q1. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or brown outs when the input voltage is falling. For the example design, the supply should turn on and start switching once the input voltage increases above 8.9 V (enabled).
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TPS57040-Q1 SLVSAP4C – DECEMBER 2010 – REVISED OCTOBER 2012 www.ti.com Use the larger value of Equation 47 and Equation 48 to calculate the C6, to set the compensation pole. Equation 48 yields 5.9 pF so the nearest standard of 5.6 pF is used. C6 = C o ´ Re sr R4 (47) 1 C6 = R4 ´ f sw ´ p (48) Discontinuous Mode and Eco-mode Boundary With an input voltage of 34 V, the power supply enters discontinuous mode when the output current is less than 50 mA.
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TPS57040-Q1 www.ti.com SLVSAP4C – DECEMBER 2010 – REVISED OCTOBER 2012 Figure 55. Output Ripple, PSM Figure 56. Input Ripple CCM 100 90 80 VIN = 24 V Efficiency - % 70 VIN = 15 V VIN = 12 V VIN = 34 V 60 VIN = 42 50 40 30 20 10 VOUT = 5.0 V 0 0 Figure 57. Input Ripple DCM 0.05 0.10 0.15 0.20 0.25 0.30 0.35 IO - Output Current - A 0.40 0.45 Figure 58.
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TPS57040-Q1 SLVSAP4C – DECEMBER 2010 – REVISED OCTOBER 2012 www.ti.com 0.1 0.1 0.08 VI = 24 V IO = 0.2 A 0.06 0.06 0.04 0.04 Regulation (%) Regulation (%) 0.08 0.02 0 -0.02 0.02 0 -0.02 -0.04 -0.04 -0.06 -0.06 -0.08 -0.08 -0.1 0.00 -0.1 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 12 24 30 36 42 VI - Input Voltage - V Load Current - A Figure 61. Regulation vs Load Current 38 18 Figure 62.
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TPS57040-Q1 www.ti.com SLVSAP4C – DECEMBER 2010 – REVISED OCTOBER 2012 Power Dissipation Estimate The following formulas show how to estimate the IC power dissipation under continuous conduction mode (CCM) operation. These equations should not be used if the device is working in discontinuous conduction mode (DCM). The power dissipation of the IC includes conduction loss (Pcon), switching loss (Psw), gate drive loss (Pgd) and supply current (Pq).
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TPS57040-Q1 SLVSAP4C – DECEMBER 2010 – REVISED OCTOBER 2012 www.ti.com Layout Layout is a critical portion of good power supply design. There are several signals paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help eliminate these problems, the VIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor with X5R or X7R dielectric.
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TPS57040-Q1 www.ti.com SLVSAP4C – DECEMBER 2010 – REVISED OCTOBER 2012 VIN + CIN Cboot Lo BOOT VIN PH GND R1 Cd + Co GND R2 VOUT VSENSE EN SS/TR COMP Rcomp RT/CLK Css Cpole RT Czero Figure 64.
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TPS57040-Q1 SLVSAP4C – DECEMBER 2010 – REVISED OCTOBER 2012 www.ti.com REVISION HISTORY Changes from Revision B (August 2012) to Revision C • 42 Page Manually inserted optional DGQ land pattern. ....................................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS57040QDGQRQ1 MSOPPower PAD DGQ 10 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 TPS57040QDRCRQ1 SON DRC 10 3000 330.0 12.4 3.3 3.3 1.0 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS57040QDGQRQ1 MSOP-PowerPAD DGQ 10 2500 370.0 355.0 55.0 TPS57040QDRCRQ1 SON DRC 10 3000 370.0 355.0 55.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.