Datasheet

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TPS57040-Q1
SLVSAP4C –DECEMBER 2010–REVISED OCTOBER 2012 www.ti.com
DETAILED DESCRIPTION (continued)
Figure 43. Plot of Synchronizing in CCM Figure 44. Plot of Synchronizing in DCM
Figure 45. Plot of Synchronizing in PSM
Power-good (PWRGD Pin)
The PWRGD pin is an open drain output. Once the VSENSE pin is between 94% and 107% of the internal
voltage reference the PWRGD pin is deasserted and the pin floats. It is recommended to use a pullup resistor
between the values of 1 kΩ and 100 kΩ to a voltage source that is 5.5 V or less. The PWRGD is in a defined
state once the V
IN
input voltage is greater than 1.5 V but with reduced current sinking capability. The PWRGD
will achieve full current sinking capability as V
IN
input voltage approaches 3 V.
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