TPS57160-Q1 www.ti.com SLVSAP1C – DECEMBER 2010 – REVISED AUGUST 2012 1.5-A 60-V STEP-DOWN SWIFT™ DC/DC CONVERTER WITH Eco-mode™ CONTROL Check for Samples: TPS57160-Q1 FEATURES • • • • • • • 1 2 • • • • • • Qualified for Automotive Applications 3.5-V to 60-V Input Voltage Range 200-mΩ High-Side MOSFET High Efficiency at Light Loads With PulseSkipping Eco-mode™ Control Scheme 116-μA Operating Quiescent Current 1.5-μA Shutdown Current 100-kHz to 2.
TPS57160-Q1 SLVSAP1C – DECEMBER 2010 – REVISED AUGUST 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
TPS57160-Q1 www.ti.com SLVSAP1C – DECEMBER 2010 – REVISED AUGUST 2012 THERMAL INFORMATION TPS57160-Q1 THERMAL METRIC (1) (2) θJA Junction-to-ambient thermal resistance (standard board) (3) DGQ DRC 10 PINS 10 PINS 62.5 56.5 θJA Junction-to-ambient thermal resistance (custom board) 57 61.5 θJCtop Junction-to-case (top) thermal resistance 83 52.1 θJB Junction-to-board thermal resistance 28 20.6 ψJT Junction-to-top characterization parameter 1.7 0.
TPS57160-Q1 SLVSAP1C – DECEMBER 2010 – REVISED AUGUST 2012 www.ti.com PACKAGE DISSIPATION RATINGS (1) θJA, THERMAL IMPEDANCE, JUNCTION TO AMBIENT PACKAGE (1) DGQ (MSOP) 57°C/W DRC (SON) 56.5°C/W Test board conditions: A. 3 inch × 3 inch, two layers, 0.062-inch thickness B. 2-ounce copper traces located on the top and bottom of the PCB C. Six (13-mil diameter) thermal vias located under the device package ELECTRICAL CHARACTERISTICS TJ = –40°C to 150°C, VIN = 3.
TPS57160-Q1 www.ti.com SLVSAP1C – DECEMBER 2010 – REVISED AUGUST 2012 ELECTRICAL CHARACTERISTICS (continued) TJ = –40°C to 150°C, VIN = 3.
TPS57160-Q1 SLVSAP1C – DECEMBER 2010 – REVISED AUGUST 2012 www.ti.com DEVICE INFORMATION PIN CONFIGURATION DRC PACKAGE (TOP VIEW) DGQ PACKAGE (TOP VIEW) BOOT VIN EN SS/TR RT/CLK 10 1 2 3 4 5 Exposed Thermal Pad 9 8 7 6 PH GND COMP VSENSE PWRGD BOOT VIN EN SS/TR RT/CLK 1 10 2 4 Exposed 9 Thermal 8 Pad 7 5 6 3 PH GND COMP VSENSE PWRGD PIN FUNCTIONS PIN I/O DESCRIPTION NAME NO. BOOT 1 O A bootstrap capacitor is required between BOOT and PH.
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TPS57160-Q1 SLVSAP1C – DECEMBER 2010 – REVISED AUGUST 2012 www.ti.com TYPICAL CHARACTERISTICS VOLTAGE REFERENCE vs JUNCTION TEMPERATURE 0.816 VI = 12 V VI = 12 V 375 BOOT-PH = 3 V 250 BOOT-PH = 6 V 125 0 -50 0.808 Vref - Voltage Reference - V RDSON - Static Drain-Source On-State Resistance - mW ON RESISTANCE vs JUNCTION TEMPERATURE 500 0.800 0.792 0.784 -50 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 -25 0 150 25 50 75 100 TJ - Junction Temperature - °C 125 150 Figure 1.
TPS57160-Q1 www.ti.com SLVSAP1C – DECEMBER 2010 – REVISED AUGUST 2012 TYPICAL CHARACTERISTICS (continued) EA TRANSCONDUCTANCE DURING SLOW START vs JUNCTION TEMPERATURE EA TRANSCONDUCTANCE vs JUNCTION TEMPERATURE 150 40 VI = 12 V VI = 12 V 130 110 gm - mA/V gm - mA/V 30 90 20 70 10 -50 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 50 -50 150 -25 0 25 50 75 100 125 150 TJ - Junction Temperature - °C Figure 7. Figure 8.
TPS57160-Q1 SLVSAP1C – DECEMBER 2010 – REVISED AUGUST 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) SS/TR DISCHARGE CURRENT vs JUNCTION TEMPERATURE SWITCHING FREQUENCY vs VSENSE 120 100 VI = 12 V VI = 12 V, TJ = 25°C 80 % of Nominal fsw II(SS/TR) - mA 115 110 60 40 105 20 100 -50 0 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 150 0 SHUTDOWN SUPPLY CURRENT vs INPUT VOLTAGE (VIN) 2 TJ = 25°C I(VIN) - mA 1.5 1 0.5 1 0.
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TPS57160-Q1 SLVSAP1C – DECEMBER 2010 – REVISED AUGUST 2012 www.ti.com OVERVIEW The TPS57160-Q1 device is a 60-V 1.5-A step-down (buck) regulator with an integrated high-side n-channel MOSFET. To improve performance during line and load transients the device implements a constant frequency, current mode control which reduces output capacitance and simplifies external frequency compensation design.
TPS57160-Q1 www.ti.com SLVSAP1C – DECEMBER 2010 – REVISED AUGUST 2012 DETAILED DESCRIPTION Fixed Frequency PWM Control The TPS57160-Q1 uses an adjustable fixed frequency, peak current mode control. The output voltage is compared through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives the COMP pin. An internal oscillator initiates the turn on of the high-side power switch. The error amplifier output is compared to the high-side power switch current.
TPS57160-Q1 SLVSAP1C – DECEMBER 2010 – REVISED AUGUST 2012 www.ti.com DETAILED DESCRIPTION (continued) Low Dropout Operation and Bootstrap Voltage (BOOT) The TPS57160-Q1 has an integrated boot regulator, and requires a small ceramic capacitor between the BOOT and PH pins to provide the gate drive voltage for the high-side MOSFET. The BOOT capacitor is refreshed when the high-side MOSFET is off and the low side diode conducts. The value of this ceramic capacitor should be 0.1 μF.
TPS57160-Q1 www.ti.com SLVSAP1C – DECEMBER 2010 – REVISED AUGUST 2012 DETAILED DESCRIPTION (continued) Error Amplifier The TPS57160-Q1 has a transconductance amplifier for the error amplifier. The error amplifier compares the VSENSE voltage to the lower of the SS/TR pin voltage or the internal 0.8-V voltage reference. The transconductance (gm) of the error amplifier is 97 μA/V during normal operation. During the slow start operation, the transconductance is a fraction of the normal operating gm.
TPS57160-Q1 SLVSAP1C – DECEMBER 2010 – REVISED AUGUST 2012 www.ti.com DETAILED DESCRIPTION (continued) Another technique to add input voltage hysteresis is shown in Figure 29. This method may be used, if the resistance values are high from the previous method and a wider voltage hysteresis is needed. The resistor R3 sources additional hysteresis current into the EN pin. TPS57160 VIN Ihys R1 I1 0.9 mA 2.9 mA + EN R2 1.25 V - VOUT R3 Figure 29.
TPS57160-Q1 www.ti.com SLVSAP1C – DECEMBER 2010 – REVISED AUGUST 2012 DETAILED DESCRIPTION (continued) Slow Start/Tracking Pin (SS/TR) The TPS57160-Q1 effectively uses the lower voltage of the internal voltage reference or the SS/TR pin voltage as the power-supply's reference voltage and regulates the output accordingly. A capacitor on the SS/TR pin to ground implements a slow start time. The TPS57160-Q1 has an internal pullup current source of 2 μA that charges the external slow start capacitor.
TPS57160-Q1 SLVSAP1C – DECEMBER 2010 – REVISED AUGUST 2012 www.ti.com DETAILED DESCRIPTION (continued) Sequencing Many of the common power supply sequencing methods can be implemented using the SS/TR, EN, and PWRGD pins. The sequential method can be implemented using an open drain output of a power-on reset pin of another device. The sequential method is illustrated in Figure 32 using two TPS57160-Q1 devices.
TPS57160-Q1 www.ti.com SLVSAP1C – DECEMBER 2010 – REVISED AUGUST 2012 DETAILED DESCRIPTION (continued) Figure 34 shows a method for ratiometric start-up sequence by connecting the SS/TR pins together. The regulator outputs ramp up and reach regulation at the same time. When calculating the slow start time, the pullup current source must be doubled in Equation 6. Figure 35 shows the results of Figure 34. TPS57160 EN VOUT 1 SS/TR PWRGD TPS57160 VOUT 2 EN R1 SS/ TR R2 PWRGD R3 R4 Figure 36.
TPS57160-Q1 SLVSAP1C – DECEMBER 2010 – REVISED AUGUST 2012 www.ti.com DETAILED DESCRIPTION (continued) DV = VOUT1 - VOUT2 (9) R1 > 2800 ? VOUT1 - 180 ? DV (10) EN EN VOUT1 VOUT1 VOUT2 Figure 37. Ratiometric Startup With VOUT2 Leading VOUT1 VOUT2 Figure 38. Ratiometric Startup With VOUT1 Leading VOUT2 EN VOUT1 VOUT2 Figure 39.
TPS57160-Q1 www.ti.com SLVSAP1C – DECEMBER 2010 – REVISED AUGUST 2012 DETAILED DESCRIPTION (continued) Constant Switching Frequency and Timing Resistor (RT/CLK Pin) The switching frequency of the TPS57160-Q1 is adjustable over a wide range from approximately 100 kHz to 2500 kHz by placing a resistor on the RT/CLK pin. The RT/CLK pin voltage is typically 0.5 V and must have a resistor to ground to set the switching frequency.
TPS57160-Q1 SLVSAP1C – DECEMBER 2010 – REVISED AUGUST 2012 www.ti.com DETAILED DESCRIPTION (continued) Selecting the Switching Frequency The switching frequency that is selected should be the lower value of the two equations, Equation 12 and Equation 13. Equation 12 is the maximum switching frequency limitation set by the minimum controllable on time. Setting the switching frequency above this value causes the regulator to skip switching pulses.
TPS57160-Q1 www.ti.com SLVSAP1C – DECEMBER 2010 – REVISED AUGUST 2012 DETAILED DESCRIPTION (continued) How to Interface to RT/CLK Pin The RT/CLK pin can be used to synchronize the regulator to an external system clock. To implement the synchronization feature connect a square wave to the RT/CLK pin through the circuit network shown in Figure 43. The square wave amplitude must transition lower than 0.5 V and higher than 2.
TPS57160-Q1 SLVSAP1C – DECEMBER 2010 – REVISED AUGUST 2012 www.ti.com DETAILED DESCRIPTION (continued) EXT EXT VOUT IL PH PH IL Figure 44. Plot of Synchronizing in CCM Figure 45. Plot of Synchronizing in DCM EXT IL PH Figure 46. Plot of Synchronizing in PSM Power-good (PWRGD Pin) The PWRGD pin is an open drain output. Once the VSENSE pin is between 94% and 107% of the internal voltage reference the PWRGD pin is de-asserted and the pin floats.
TPS57160-Q1 www.ti.com SLVSAP1C – DECEMBER 2010 – REVISED AUGUST 2012 DETAILED DESCRIPTION (continued) The PWRGD pin is pulled low when the VSENSE is lower than 92% or greater than 109% of the nominal internal reference voltage. Also, PWRGD is pulled low if the UVLO or thermal shutdown are asserted or EN is pulled low.
TPS57160-Q1 SLVSAP1C – DECEMBER 2010 – REVISED AUGUST 2012 www.ti.com DETAILED DESCRIPTION (continued) PH VO Power Stage gmps 6 A/V a b R1 RESR RL COMP c 0.8 V R3 C2 CO RO VSENSE COUT gmea 97 mA/V R2 C1 Figure 47. Small Signal Model for Loop Response Simple Small Signal Model for Peak Current Mode Control Figure 48 describes a simple small signal model that can be used to understand how to design the frequency compensation.
TPS57160-Q1 www.ti.com SLVSAP1C – DECEMBER 2010 – REVISED AUGUST 2012 DETAILED DESCRIPTION (continued) VO Adc VC RESR fp RL gmps COUT fz Figure 48.
TPS57160-Q1 SLVSAP1C – DECEMBER 2010 – REVISED AUGUST 2012 www.ti.com DETAILED DESCRIPTION (continued) VO R1 VSENSE gmea Type 2A COMP Type 2B Type 1 Vref R2 RO R3 CO C1 C2 R3 C2 C1 Figure 49. Types of Frequency Compensation Aol A0 P1 Z1 P2 A1 BW Figure 50.
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TPS57160-Q1 SLVSAP1C – DECEMBER 2010 – REVISED AUGUST 2012 www.ti.com APPLICATION INFORMATION Design Guide — Step-By-Step Design Procedure This example details the design of a high frequency switching regulator design using ceramic output capacitors. A few parameters must be known to start the design process. These parameters are typically determined at the system level. For this example, start with the following known parameters: Output voltage 3.3 V Transient response 0 to 1.
TPS57160-Q1 www.ti.com SLVSAP1C – DECEMBER 2010 – REVISED AUGUST 2012 Output Inductor Selection (LO) To calculate the minimum value of the output inductor, use Equation 28. KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. The inductor ripple current is filtered by the output capacitor.
TPS57160-Q1 SLVSAP1C – DECEMBER 2010 – REVISED AUGUST 2012 www.ti.com Where ΔIOUT is the change in output current, ƒsw is the regulators switching frequency and ΔVOUT is the allowable change in the output voltage. For this example, the transient load response is specified as a 4% change in VOUT for a load step from 0 A (no load) to 1.5 A (full load). For this example, ΔIOUT = 1.5 – 0 = 1.5 A and ΔVOUT = 0.04 × 3.3 = 0.132 V. Using these numbers gives a minimum capacitance of 18.9 μF.
TPS57160-Q1 www.ti.com SLVSAP1C – DECEMBER 2010 – REVISED AUGUST 2012 VOUT(ripple ) RESR = IRIPPLE ICOUT(rms) = (35) ( VOUT ´ VIN(max ) - VOUT ) 12 ´ VIN(max ) ´ LO ´ fSW (36) Catch Diode The TPS57160-Q1 requires an external catch diode between the PH pin and GND. The selected diode must have a reverse voltage rating equal to or greater than VIN(max). The peak current rating of the diode must be greater than the maximum inductor current. The diode should also have a low forward voltage.
TPS57160-Q1 SLVSAP1C – DECEMBER 2010 – REVISED AUGUST 2012 www.ti.com For this example design, a ceramic capacitor with at least a 20-V voltage rating is required to support the maximum input voltage. Common standard ceramic capacitor voltage ratings include 4 V, 6.3 V, 10 V, 16 V, 25 V, 50 V or 100 V, so a 25-V capacitor should be selected. For this example, two 2.2-μF 25-V capacitors in parallel have been selected. Table 1 shows a selection of high voltage capacitors.
TPS57160-Q1 www.ti.com SLVSAP1C – DECEMBER 2010 – REVISED AUGUST 2012 Bootstrap Capacitor Selection A 0.1-μF ceramic capacitor must be connected between the BOOT and PH pins for proper operation. It is recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have a 10-V or higher voltage rating. Undervoltage Lockout (UVLO) Set Point The UVLO can be adjusted using an external voltage divider on the EN pin of the TPS57160-Q1.
TPS57160-Q1 SLVSAP1C – DECEMBER 2010 – REVISED AUGUST 2012 www.ti.com To compensate the TPS57160-Q1 using this method, first calculate the modulator pole and zero using the following equations: IOUT(max ) fP(mod) = 2 ´ p ´ VOUT ´ COUT where • • • IOUT(max) is the maximum output current COUT is the output capacitance VOUT is the nominal output voltage f Z(mod) = (41) 1 2 ´ p ´ RESR ´ COUT (42) For the example design, the modulator pole is located at 1.5 kHz and the ESR zero is located at 338 kHz.
TPS57160-Q1 www.ti.com SLVSAP1C – DECEMBER 2010 – REVISED AUGUST 2012 For the example problem, the gain of the modulator at the crossover frequency is 0.542. Next, the compensation components are calculated. A resistor in series with a capacitor is used to create a compensating zero. A capacitor in parallel to these two components forms the compensating pole. However, calculating the values of these components varies depending on if the ESR zero is located above or below the crossover frequency.
TPS57160-Q1 SLVSAP1C – DECEMBER 2010 – REVISED AUGUST 2012 www.ti.com APPLICATION CURVES VIN VO VOUT EN IO IL Figure 52. Load Transmit Figure 53. Startup With EN VOUT VOUT IL PH VIN IL Figure 54. VIN Power Up Figure 55. Output Ripple CCM VOUT VOUT IL IL PH Figure 56. Output Ripple, DCM 38 PH Figure 57.
TPS57160-Q1 www.ti.com SLVSAP1C – DECEMBER 2010 – REVISED AUGUST 2012 VIN VIN IL IL PH PH Figure 58. Input Ripple CCM Figure 59. Input Ripple DCM 95 VO = 3.3 V, fsw = 1200 kHz VI = 8 V 90 85 VIN Efficiency - % 80 IL VI = 12 V 75 VI = 16 V 70 65 PH 60 55 50 0 Figure 60. Input Ripple PSM 0.25 0.50 0.75 1 1.25 IL - Load Current - A 1.5 1.75 2 Figure 61. Efficiency vs Load Current 1.015 60 150 VI = 12 V 1.010 40 100 1.
TPS57160-Q1 SLVSAP1C – DECEMBER 2010 – REVISED AUGUST 2012 www.ti.com 1.015 IO = 0.5 A 1.010 Regulation (%) 1.005 1.000 0.995 0.990 0.985 5 10 15 20 VI - Input Voltage - V Figure 64.
TPS57160-Q1 www.ti.com SLVSAP1C – DECEMBER 2010 – REVISED AUGUST 2012 Power Dissipation The following formulas show how to estimate power dissipation under continuous conduction mode (CCM) operation. These equations should not be used if the device is working in discontinuous conduction mode (DCM). The power dissipation of the device includes conduction loss (Pcon), switching loss (Psw), gate drive loss (Pgd), and supply current loss (Pq).
TPS57160-Q1 SLVSAP1C – DECEMBER 2010 – REVISED AUGUST 2012 www.ti.com Layout Layout is a critical portion of good power supply design. There are several signals paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help eliminate these problems, the VIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor with X5R or X7R dielectric.
TPS57160-Q1 SLVSAP1C – DECEMBER 2010 – REVISED AUGUST 2012 TPS57160 www.ti.com Figure 66.
TPS57160-Q1 SLVSAP1C – DECEMBER 2010 – REVISED AUGUST 2012 www.ti.com REVISION HISTORY Changes from Revision B (March, 2011) to Revision C Page • Changed "regulated output supply current" to "input supply current .................................................................................... 1 • Updated footnote under Abs Max table. ............................................................................................................................... 2 • Changed 25°C to 125°C .........
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS57160QDGQRQ1 MSOPPower PAD DGQ 10 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 TPS57160QDRCRQ1 SON DRC 10 3000 330.0 12.4 3.3 3.3 1.0 8.0 12.
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS57160QDGQRQ1 MSOP-PowerPAD DGQ 10 2500 370.0 355.0 55.0 TPS57160QDRCRQ1 SON DRC 10 3000 370.0 355.0 55.
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