Datasheet

75 kΩ
9
10
11
12
PGOOD1
EN1
PGOOD2
EN2
TPS59124RGE
13 14 15 16
VBST1
DRVL1
LL1
DRVH1
VBST2
DRVH2
LL2
DRVL2
17
8
7
6 5 4 3 2 1
18
19
20
21
22
23
24
VO1
1.05 V/10 A
Q2
IRF8113
L1
Q1
IRF7821
VO2
1.5 V/10 A
Q4
IRF8113
L2
Q3
IRF7821
Input Voltage
3 V to 28 V
PowerPAD
TM
C7
R6
C3
C1
C6
C4
R3
6.8
C8
R7
R1
R2
75
R5
R4
V5IN
4.5 V to 5.5 V
VO2
VO1
VFB2
TONSEL
GND
VFB1
PGND2
TRIP2
V5FILT
V5IN
TRIP1
PGND1
Power
Good2
EN2
C5
C2
Power
Good1
EN1
SGND
PGNDPGND
SGND
C9
SGND PGND
PGND
73.2 kΩ
kΩ
28.7 kΩ
22 µF
2 x 330 µF
1 µH
10 µF
0.1 µF
4.7 μF
6.8 kΩ
1 μF
3.3Ω
kΩ
0.1 µF
10 µF
1 µH
2 x 330 µF
TPS59124
www.ti.com
SLUSA58 JULY 2010
Dual Synchronous Step-Down Controller
for Low-Voltage Power Rails in Embedded Computing Systems
1
FEATURES
DESCRIPTION
2
High Efficiency, Low-Power Consumption,
Shutdowns to <1 mA
The TPS59124 is a dual, adaptive on-time D-CAP™
mode synchronous buck controller. This device
Fixed Frequency Emulated On-Time Control,
enables system designers to cost effectively complete
Frequency Selectable From Three Options
the suite of embedded computer power bus
D-CAP™ Mode Enables Fast Transient
regulators with the absolute lowest external
Response
component count and lowest standby consumption.
Auto-Skip Mode
The fixed-frequency emulated adaptive on-time
control supports seamless operation between PWM
Less Than 1% Initial Reference Accuracy
mode at heavy load condition and reduced frequency
Low Output Ripple
operation at light load for high-efficiency down to
Wide Input Voltage Range: 3 V to 28 V
milliampere range. The main control loop for the
TPS59124 uses the D-CAP mode that optimized for
Output Voltage Range: 0.76 V to 5.5 V
low-ESR output capacitors such as POSCAP or
Low-Side R
DS(on)
Loss-less Current Sensing
SP-CAP promises fast transient response with no
Adaptive Gate Drivers With Integrated Boost
external compensation. Simple and separate power
Diode
good signals for each channel allow flexibility of
power sequencing. The device provides convenient
Internal 1.2-ms Voltage-Servo Soft Start
and efficient operation with supply input voltages
Power-Good Signals for Each Channel With
(V5IN, V5FILT) ranging from 4.5 V to 5.5 V,
Delay Timer
conversion voltages (drain voltage for the
Output Discharge During Disable, Fault
synchronous high-side MOSFET) from 3 V to 28 V
and output voltages from 0.76 V to 5.5 V.
APPLICATIONS
The TPS59124 is available in 24-pin QFN package
I/O and Low Voltage System Bus in Embedded
specified from –40°C to 85°C ambient temperature
Computing Systems
range.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2D-CAP, PowerPAD are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

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