Datasheet
ESR
R1
Co
+
0.758V
R2
Control
Logic
And
Driver
RL
VIN
VFB
DRVH
DRVL
PWM
SwitchingModulator
VoltageDivider
Vc
OutputCapacitor
Lx
I
L
I
C
I
O
−
+
ƒ
o
+
1
2p ESR Co
v
ƒ
sw
4
( )
æ ö
= ´
ç ÷
è ø
OUT
RIPPLE
V
V 10 mV
0.758
TPS59124
SLUSA58 –JULY 2010
www.ti.com
APPLICATION INFORMATION
LOOP COMPENSATION AND EXTERNAL PARTS SELECTION
A buck converter system using D-CAP Mode can be simplified as shown in Figure 24.
Figure 24. Simplifying the Modulator
The output voltage is compared with an internal reference voltage after divider resistors, R1 and R2. The PWM
comparator determines the timing to turn on the high-side MOSFET. The gain and speed of the comparator is
high enough to keep the voltage at the beginning of each on cycle (or the end of off cycle) substantially constant.
The DC output voltage may have line regulation due to ripple amplitude that slightly increases as the input
voltage increase.
For loop stability, the 0-dB frequency, f
0
, defined in Equation 4 needs to be lower than 1/4 of the switching
frequency.
(4)
Because f
0
is determined solely by the output capacitor’s characteristics, the loop stability of D-CAP Mode is
determined by the capacitor chemistry. For example, specialty polymer capacitors (SP-CAP) have output
capacitance, C
OUT
in the order of several 100 mF and ESR in range of 10 mΩ. These make f
0
in the order of 100
kHz or less and the loop is stable. However, ceramic capacitors have f
0
at more than 700 kHz, which is not
suitable for this operational mode.
Although D-CAP Mode provides many advantages such as ease-of-use, minimum external components
configuration, and extremely short response time, a sufficient amount of feedback signal must be provided by an
external circuit to reduce jitter level because there is no error amplifier in the loop. The required signal level is
approximately 10 mV at the comparing point (VFB terminal). This gives V
RIPPLE
at the output node as shown in
Equation 5.
(5)
The output capacitor ESR should meet this requirement.
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