Datasheet

TPS59650EVM
CPU Dynamic VID: Set VID-Decay/Fast
Test condition: 12 Vin, 1.05V/1A
CPU 2 Operation
CH1: CSW1
CH2: CSW2
CH3: 1.05Vcore
CH4: VDIO
TPS59650EVM
CPU Dynamic VID: Set VID-Slow/Slow
Test condition: 12 Vin, 1.05V/1A
CPU 2 Operation
CH1: CSW1
CH2: CSW2
CH3: 1.05Vcore
CH4: VDIO
CH3: CSW2
CH4: 1.05Vcore
TPS59650EVM
CPU Output Load Release with
OSR/USR middle level
Test condition: 12 Vin, 1.05V/0A-51A
CPU 3 Phase on board dynamic load
CH2: CSW1
CH1: DYN_C
CH3: CSW2
CH4: 1.05Vcore
TPS59650EVM
CPU Output Load Insertion with
OSR/USR middle level
Test condition: 12 Vin, 1.05V/0A-51A
CPU 3 Phase on board dynamic load
CH1: DYN_C
CH2: CSW1
www.ti.com Performance Data and Typical Characteristic Curves
Figure 26. CPU2 Dynamic VID:SetVID-Fast/Fast Figure 27. CPU2 Dynamic VID:SetVID-Decay/Fast
Figure 28. CPU2 Output Load Insertion with OSR/USR Figure 29. CPU2 Output Load Release with OSR/USR
middle level middle level
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SLUU896–March 2012 Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU
SVID Power System
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