Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - DC/DC voltage regulator Boost DSBGA 6

1 Hm

OUT

4.7 Fm

OUT

5 V

2.2 Fm

VIN

VOUT

GND

TPS61240

TPS61240, TPS61241

www.ti.com

SLVS806B –APRIL 2009– REVISED FEBRUARY 2012

3.5-MHz High Efficiency Step-Up Converter

Check for Samples: TPS61240, TPS61241

FEATURES

DESCRIPTION

• Efficiency > 90% at Nominal Operating

The TPS6124x device is a high efficient synchronous

Conditions

step up DC-DC converter optimized for products

• Total DC Output Voltage Accuracy 5.0V±2%

• Typical 30 μA Quiescent Current

NiMH, or one-cell Li-Ion or Li-Polymer battery. The

TPS6124x supports output currents up to 450mA.

• Best in Class Line and Load Transient

The TPS61240 has an input valley current limit of

• Wide V

Range From 2.3V to 5.5V

500mA, and the TPS61241 has an input valley

• Output current up to 450mA

current of 600mA.

• Automatic PFM/PWM Mode transition

With an input voltage range of 2.3V to 5.5V the

• Low Ripple Power Save Mode for Improved

device supports batteries with extended voltage

Efficiency at Light Loads

range and are ideal to power portable applications

like mobile phones and other portable equipment.

• Internal Softstart, 250μs typical Start-Up time

The TPS6124x boost converter is based on a

• 3.5MHz Typical Operating Frequency

quasi-constant on-time valley current mode control

• Load Disconnect During Shutdown

scheme.

• Current Overload and Thermal Shutdown

The TPS6124x presents a high impedance at the

Protection

OUT

pin when shut down. This allows for use in

applications that require the regulated output bus to

• Three Surface-Mount External Components

be driven by another supply while the TPS6124x is

Required (One MLCC Inductor, Two Ceramic

shut down.

Capacitors)

• Total Solution Size <13 mm

During light loads the device will automatically pulse

skip allowing maximum efficiency at lowest quiescent

• Available in a 6-pin WCSP and 2×2-SON

currents. In the shutdown mode, the current

Package

consumption is reduced to less than 1μA.

TPS6124x allows the use of small inductors and

APPLICATIONS

capacitors to achieve a small solution size. During

• USB-OTG Applications

shutdown, the load is completely disconnected from

• Portable HDMI Applications

the battery. The TPS6124x is available in a 6-pin

WCSP and 2×2 SON package.

• Cell Phones, Smart-Phones

• PDAs, Pocket PCs

• Portable Media Players

• Digital Cameras

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (26 pages)

PAGE 1
TPS61240, TPS61241 SLVS806B – APRIL 2009 – REVISED FEBRUARY 2012 www.ti.com 3.5-MHz High Efficiency Step-Up Converter Check for Samples: TPS61240, TPS61241 FEATURES 1 • • • • • • • • • • • • • • • DESCRIPTION Efficiency > 90% at Nominal Operating Conditions Total DC Output Voltage Accuracy 5.0V±2% Typical 30 μA Quiescent Current Best in Class Line and Load Transient Wide VIN Range From 2.3V to 5.
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TPS61240, TPS61241 SLVS806B – APRIL 2009 – REVISED FEBRUARY 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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TPS61240, TPS61241 SLVS806B – APRIL 2009 – REVISED FEBRUARY 2012 www.ti.com RECOMMENDED OPERATING CONDITIONS MIN VIN Input voltage range 2.3 L Inductance 0.4 CO Output capacitance TA Operating ambient temperature TJ Operating junction temperature –40 TPS61240 TPS61241 TPS61242 NOM MAX UNIT 5.5 V 1.5 µH 1 20 µF 0.8 10 µF –40 85 °C 125 °C 1 ELECTRICAL CHARACTERISTICS Over full operating ambient temperature range, typical values are at TA = 25°C.
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TPS61240, TPS61241 SLVS806B – APRIL 2009 – REVISED FEBRUARY 2012 www.ti.com PIN ASSIGNMENTS WCSP PACKAGE BOTTOM VIEW TOP VIEW A1 A2 A2 A1 B1 B2 B2 B1 C1 C2 C2 C1 QFN PACKAGE (TOP VIEW) 6 1 w Po 5 Pa er 2 d 3 4 PIN FUNCTIONS PIN NO. 4 PIN NAME QFN WCSP 2 B2 VOUT 6 A1 VIN FUNCTION REMARKS Output Connected to load Supply voltage Supply from battery 5 B1 L Boost and rectifying switch input Inductor connection to FETs 4 C1 EN Enable Positive polarity.
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TPS61240, TPS61241 SLVS806B – APRIL 2009 – REVISED FEBRUARY 2012 www.ti.com FUNCTIONAL BLOCK DIAGRAM L VOUT Gate Drive VIN FB Current Sense Error Amp. R1 Softstart R2 + Thermal Shutdown EN Int. Resistor Network - + _ VREF Control Logic GND Undervoltage Lockout GND PARAMETER MEASUREMENT INFORMATION TPS61240 L 1 mH VIN L VOUT COUT VIN FB EN GND VOUT 5 V 4.7 mF CIN 2.
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TPS61240, TPS61241 SLVS806B – APRIL 2009 – REVISED FEBRUARY 2012 www.ti.com TYPICAL CHARACTERISTICS Table of Graphs Table 1. Figure Maximum Output Current Efficiency Input Current Output Voltage Frequency Waveforms vs Input Voltage 1 vs Output Current, Vout = 5V, Vin = [2.3V; 3.0V; 3.6V; 4.2V] 2 vs Input Voltage, Vout = 5V, Iout = [100uA; 1mA; 10mA; 100mA; 200mA] 3 at No Output Load, Device Disabled 4 vs Output Current, Vout = 5V, Vin = [2.3V; 3.0V; 3.6V; 4.
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TPS61240, TPS61241 SLVS806B – APRIL 2009 – REVISED FEBRUARY 2012 www.ti.com 100 0.070 IO = 200 mA 90 -40°C 0.060 25°C II - Input Current - mA Efficiency - % 80 70 IO = 100 mA 60 IO = 10 mA 50 40 IO = 1 mA IO = 100 mA 30 85°C 0.050 0.040 0.030 0.020 20 0.010 10 0 2.3 0 2.8 3.3 3.8 4.3 VIN - Input Voltage - V 4.8 5.3 2 Figure 3. Efficiency vs Input Voltage 3 3.5 4 4.5 5 VI - Input Voltage - V 5.5 6 Figure 4. Input at No Output Load 5.10 5.10 5.08 VI = 4.2 V 5.
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TPS61240, TPS61241 SLVS806B – APRIL 2009 – REVISED FEBRUARY 2012 www.ti.com 5.5 VIN = 3.6 V, VOUT = 5 V, IOUT = 10 mA VOUT = 20 mV/div f - Frequency - MHz 5 4.5 SW = 5 V/div 5V 4 ICOIL = 200 mA/div 4V 3V 3.5 3 100 150 200 250 300 350 400 IO - Output Current - mA 450 Figure 7. Frequency vs Output Load t - Time Base - 1 ms/div 500 Figure 8. Output Voltage Ripple – PFM Mode VIN = 3.6 V, VOUT = 5 V, IOUT = 150 mA VOUT = 10 mV/div SW = 5 V/div VOUT = 100 mV/dIV VIN = 3.
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TPS61240, TPS61241 SLVS806B – APRIL 2009 – REVISED FEBRUARY 2012 www.ti.com VIN = 1 V/div VOUT = 200 mV/div VOUT = 50 mv/div VIN = 3.6 V VOUT = 5 V IOUT = 50 - 200 mA ICOIL = 200 mA/div VIN = 3.6 V - 4.2 V VOUT = 5 V IOUT = 50 mA ICOIL = 200 mA/div 200 mA 50 mA IOUT = 200 mA/div t - Time Base - 20 ms/div Figure 11. Load Transient Response 0mA–200mA and 200mA–0mA t - Time Base - 100 ms/div Figure 12. Line Transient Response 3.6V–4.
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TPS61240, TPS61241 SLVS806B – APRIL 2009 – REVISED FEBRUARY 2012 www.ti.com EN = 5 V/div EN = 5 V/div VOUT = 1 V/div VOUT = 2 V/div VIN = 3.6 V VOUT = 5 V IOUT = 150 mA VIN = 3.6 V VOUT = 5 V IOUT = 150 mA VIN = 1 V/div ICOIL = 200 mA/div ICOIL = 200 mA/div t - Time Base - 100 ms/div t - Time Base - 200 ms/div Figure 15. Startup After Enable – With Load Figure 16. Startup and Shutdown DETAILED DESCRIPTION OPERATION The TPS6124x Boost Converter operates with typically 3.
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TPS61240, TPS61241 SLVS806B – APRIL 2009 – REVISED FEBRUARY 2012 www.ti.com IPEAK IL Current Limit Threshold Rectifier Current IVALLEY = ILIM IOUT(CL) DIL IOUT(DC) Increased Load Current IIN(DC) f Inductorr Current IIN(DC) DIL ΔI L = V IN D × L f Figure 17. Inductor/Rectifier Currents in Current Limit Operation POWER-SAVE MODE The TPS6124x family of devices integrates a power save mode to improve efficiency at light load.
PAGE 12
TPS61240, TPS61241 SLVS806B – APRIL 2009 – REVISED FEBRUARY 2012 www.ti.com ENABLE The device is enabled setting EN pin to high. At first, the internal reference is activated and the internal analog circuits are settled. Afterwards, the soft start is activated and the output voltage is ramped up. The output voltages reaches its nominal value in typically 250 μs after the device has been enabled. The EN input can be used to control power sequencing in a system with various DC/DC converters.
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TPS61240, TPS61241 SLVS806B – APRIL 2009 – REVISED FEBRUARY 2012 www.ti.com APPLICATION INFORMATION TPS61240 L L 1 mH VIN VOUT COUT VIN FB EN GND VOUT 5 V 4.7 mF CIN 2.2 mF Figure 18. TPS61240 Fixed 5.0V for HDMI / USB-OTG Applications TPS61240 L 1 mH VIN L VIN FB VOUT 5 V VOUT COUT CIN GND EN 4.7 mF 2.2 mF Figure 19. TPS61240 Fixed 5.0V With Schottky Diode for Output Overvoltage Protection TPS61242 DRV2603 L 1 mH L VOUT VIN CIN VIN FB EN GND 1.5 mF 6.
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TPS61240, TPS61241 SLVS806B – APRIL 2009 – REVISED FEBRUARY 2012 www.ti.com DESIGN PROCEDURE PROGRAMMING THE OUTPUT VOLTAGE The output voltage is set by a resistor divider internally. The FB pin is used to sense the output voltage. To configure the output properly, the FB pin needs to be connected directly as shown in Figure 18 and Figure 19. INDUCTOR SELECTION To make sure that the TPS6124x devices can operate, an inductor must be connected between pin VIN and pin L.
PAGE 15
TPS61240, TPS61241 SLVS806B – APRIL 2009 – REVISED FEBRUARY 2012 www.ti.com INPUT CAPACITOR At least 2.2μF input capacitor is recommended to improve transient behavior of the regulator and EMI behavior of the total power supply circuit. It is recommended to place a ceramic capacitor as close as possible to the VIN and GND pins OUTPUT CAPACITOR For the output capacitor, it is recommended to use small ceramic capacitors placed as close as possible to the VOUT and GND pins of the IC.
PAGE 16
TPS61240, TPS61241 SLVS806B – APRIL 2009 – REVISED FEBRUARY 2012 www.ti.com LAYOUT CONSIDERATIONS As for all switching power supplies, the layout is an important step in the design, especially at high peak currents and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground tracks.
PAGE 17
TPS61240, TPS61241 SLVS806B – APRIL 2009 – REVISED FEBRUARY 2012 www.ti.com THERMAL INFORMATION Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires special attention to power dissipation. Many system-dependant issues such as thermal coupling, airflow, added heat sinks, and convection surfaces, and the presence of other heat-generating components, affect the power-dissipation limits of a given component.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 28-Oct-2013 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
PAGE 20
PACKAGE MATERIALS INFORMATION www.ti.com 4-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS61240DRVR Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2.2 1.2 4.0 8.0 Q2 SON DRV 6 3000 179.0 8.4 TPS61240DRVT SON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS61240YFFT DSBGA YFF 6 250 180.0 8.4 0.98 1.41 0.69 4.0 8.0 Q1 TPS61241YFFR DSBGA YFF 6 3000 180.0 8.
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PACKAGE MATERIALS INFORMATION www.ti.com 4-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS61240DRVR SON DRV 6 3000 203.0 203.0 35.0 TPS61240DRVT SON DRV 6 250 203.0 203.0 35.0 TPS61240YFFT DSBGA YFF 6 250 182.0 182.0 17.0 TPS61241YFFR DSBGA YFF 6 3000 182.0 182.0 17.0 TPS61241YFFT DSBGA YFF 6 250 182.0 182.0 17.
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D: Max = 1.288 mm, Min =1.228 mm E: Max = 0.886 mm, Min =0.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.