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TPS62110-Q1

www.ti.com

SLVSA54A –FEBRUARY 2010–REVISED SEPTEMBER 2012

17-V 1.5-A SYNCHRONOUS STEP-DOWN CONVERTER

Check for Samples: TPS62110-Q1

FEATURES

• Up to 1.5-A Output Current

• High Efficiency Over a Wide Load Current

• Qualified for Automotive Applications

Range Due to PFM/PWM Operation Mode

• AEC-Q100 Qualified With the Following

• 100% Maximum Duty Cycle for Lowest

Results:

Dropout

– Device Temperature Grade 1: –40°C to

• 20-µA Quiescent Current (Typical)

125°C Ambient Operating Temperature

Range

• Overtemperature and Overcurrent Protected

– Device HBM ESD Classification Level H2

• Available in 16 Pin QFN Package

– Device CDM ESD Classification Level C3B

• High-Efficiency Synchronous Step-Down

Converter With up to 95% Efficiency

• 3.1-V to 17-V Operating Input Voltage Range

• Adjustable Output Voltage Range

From 1.2 V to 16 V

• Synchronizable to External Clock Signal up to

1.4 MHz

DESCRIPTION/ORDERING INFORMATION

The TPS62110 is a low-noise synchronous step-down dc-dc converter that is ideally suited for systems powered

from a 2-cell Li-ion battery or from a 12-V or 15-V rail.

The TPS62110 is a synchronous PWM converter with integrated N-channel and P-channel power MOSFET

switches. Synchronous rectification is used to increase efficiency and to reduce external component count. To

achieve highest efficiency over a wide load current range, the converter enters a power-saving, pulse-frequency

modulation (PFM) mode at light load currents. Operating frequency is typically 1 MHz, allowing the use of small

inductor and capacitor values. The device can be synchronized to an external clock signal in the range of 0.8

MHz to 1.4 MHz. For low noise operation, the converter can be operated in PWM-only mode. In the shutdown

mode, the current consumption is reduced to less than 2 µA. The TPS62110 is available in the 16-pin (RSA)

QFN package and operates over a free-air temperature range of –40°C to 125°C.

ORDERING INFORMATION

(1)(2)

ORDERABLE PART NUMBER TOP-SIDE MARKING

–40°C to 125°C TPS62110QRSARQ1 TPS62110Q

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (25 pages)

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TPS62110-Q1 www.ti.com SLVSA54A – FEBRUARY 2010 – REVISED SEPTEMBER 2012 17-V 1.5-A SYNCHRONOUS STEP-DOWN CONVERTER Check for Samples: TPS62110-Q1 FEATURES 1 • • • • • • Qualified for Automotive Applications AEC-Q100 Qualified With the Following Results: – Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature Range – Device HBM ESD Classification Level H2 – Device CDM ESD Classification Level C3B High-Efficiency Synchronous Step-Down Converter With up to 95% Efficiency 3.
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TPS62110-Q1 SLVSA54A – FEBRUARY 2010 – REVISED SEPTEMBER 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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TPS62110-Q1 www.ti.com SLVSA54A – FEBRUARY 2010 – REVISED SEPTEMBER 2012 ELECTRICAL CHARACTERISTICS VI = 12 V, VO = 3.3 V, IO = 600 mA, EN = VI, TA = –40°C to 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT VI Input voltage range (1) I(Q) Operating quiescent current I(SD) Shutdown current 3.1 17 IO = 0 mA, SYNC = GND, VI = 7.2 V, TA = 25°C (2) 20 IO = 0 mA, SYNC = GND, VI = 17 V (2) 23 29 EN = GND 1.5 5 EN = GND, TA = 25°C, VI = 7.2 V 1.
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TPS62110-Q1 SLVSA54A – FEBRUARY 2010 – REVISED SEPTEMBER 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VI = 12 V, VO = 3.3 V, IO = 600 mA, EN = VI, TA = –40°C to 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 900 1000 1100 kHz 1400 kHz OSCILLATOR fS Oscillator frequency f(SYNC) Synchronization range VIH SYNC high-level input voltage VIL SYNC low-level input voltage Ilkg SYNC input leakage current CMOS-logic clock signal on SYNC pin 800 1.
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TPS62110-Q1 www.ti.com SLVSA54A – FEBRUARY 2010 – REVISED SEPTEMBER 2012 DEVICE INFORMATION PGND SW SW PG RSA PACKAGE (TOP VIEW) 2 3 4 16 15 14 13 12 Exposed Thermal Pad 11 10 5 6 7 8 9 GND GND FB AGND VINA 1 SYNC LBO LBI PGND VIN VIN EN TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION EN 4 I Enable. A logic high enables the converter; logic low forces the device into shutdown mode reducing the supply current to less than 2 µA.
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TPS62110-Q1 SLVSA54A – FEBRUARY 2010 – REVISED SEPTEMBER 2012 www.ti.
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TPS62110-Q1 www.ti.com SLVSA54A – FEBRUARY 2010 – REVISED SEPTEMBER 2012 TYPICAL CHARACTERISTICS Table of Graphs FIGURE Efficiency vs Output current (1.8 V) 1, 2 Efficiency vs Output current (1.5 V) 3, 4 Switching frequency vs Input voltage 5 Quiescent current vs Input voltage 16 Graphs with VO = 1.8 V were taken using the circuit according to Figure 10. EFFICIENCY vs OUTPUT CURRENT EFFICIENCY vs OUTPUT CURRENT 100 100 90 90 80 4.2 V 80 5V 70 60 Efficiency - % Efficiency - % 4.
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TPS62110-Q1 SLVSA54A – FEBRUARY 2010 – REVISED SEPTEMBER 2012 www.ti.com EFFICIENCY vs OUTPUT CURRENT 100 100 90 90 4.2 V 80 70 5V 60 4.2 V 80 Efficiency - % Efficiency - % EFFICIENCY vs OUTPUT CURRENT 8.4 V 50 40 12 V 30 70 5V 60 8.4 V 50 40 12 V 30 VO = 1.5 V o TA = 25 C PWM Mode 20 10 0 0.0001 0.001 0.01 0.1 10 0 0.0001 10 1 VO = 1.5 V o TA = 25 C PFM Mode 20 0.001 1 Figure 3. Figure 4.
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TPS62110-Q1 www.ti.com SLVSA54A – FEBRUARY 2010 – REVISED SEPTEMBER 2012 The graphs were generated using the EVM with the setup according to Figure 7 unless otherwise noted. The output voltage divider was adjusted according to Table 4. TDK 6.8 µH SLF7032T-6R8M1R6 Vbat open CI 10 µF / 25 V TDK C3225X5R1E106K TPS62110 VIN VIN EN VO SW SW 1 MW 1 MW R1 Cff PG VINA CO 22 µF / 16 V TDK C3225X7R1C226M 1 µF AGND LBO FB LBI R2 261 kW SYNC VIN or GND GND GND PwPD PGND PGND Figure 7.
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TPS62110-Q1 SLVSA54A – FEBRUARY 2010 – REVISED SEPTEMBER 2012 www.ti.com DETAILED DESCRIPTION OPERATION The TPS62110 is a synchronous step-down converter that operates with a 1-MHz fixed frequency pulse width modulation (PWM) at moderate-to-heavy load currents and enters the power save mode at light load current. During PWM operation, the converter uses a unique fast response voltage mode control scheme with input voltage feed-forward.
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TPS62110-Q1 www.ti.com SLVSA54A – FEBRUARY 2010 – REVISED SEPTEMBER 2012 1.6% 0.8% VO (nominal) -1.6% t Figure 8. Power Save Mode Output Voltage Thresholds The typical PFM (SKIP) current threshold for the TPS62110 is given by: VI I S K IP » 25 W (1) Equation 1 is valid for input voltages up to 7 V. For higher voltages, the skip current threshold is not increased further. The converter enters the fixed frequency PWM mode as soon as the output voltage falls below VO – 1.6% (nominal).
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TPS62110-Q1 SLVSA54A – FEBRUARY 2010 – REVISED SEPTEMBER 2012 www.ti.com ENABLE Logic low on EN forces the TPS62110 into shutdown. In shutdown, the power switch, drivers, voltage reference, oscillator, and all other functions are turned off. The supply current is reduced to less than 2 µA in the shutdown mode. When the device is in thermal shutdown, the bandgap is forced to be switched on even if the device is set into shutdown by pulling EN to GND.
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TPS62110-Q1 www.ti.com SLVSA54A – FEBRUARY 2010 – REVISED SEPTEMBER 2012 6.8 mH VI = 4.3 V to 17 V 2 3 4 TPS62110 VIN VIN EN SW SW 15 R3 R5 8 CI = 10 mF 25 V PG VINA 1 mF 9 7 AGND 6 FB 10 SYNC R4 Cff 10 pF R1 560 k 13 LBO LBI 5 R6 VO = 3.3 V 14 CO = 22 mF 6.3 V R2 300 k R7 GND GND PwPD PGND PGND 11 12 16 1 Figure 9.
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TPS62110-Q1 SLVSA54A – FEBRUARY 2010 – REVISED SEPTEMBER 2012 www.ti.com Table 2. Advantages and Disadvantages When Designing the Inductor and Output Capacitor INFLUENCE ON STABILITY ADVANTAGE DISADVANTAGE Less output voltage ripple Increase Cout (>22 µF) Uncritical Decrease Cout (<22 µF) Critical Increase inductor value >6.
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TPS62110-Q1 www.ti.com SLVSA54A – FEBRUARY 2010 – REVISED SEPTEMBER 2012 The overall output ripple voltage is the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charge and discharging the output capacitor: VO VI L ´ f 1 DV O = VO ´ æ 1 ´ çç + RESR 8 C ´ O ´ f è ö ÷ ÷ ø (5) Where the highest output voltage ripple occurs at the highest input voltage VI.
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TPS62110-Q1 SLVSA54A – FEBRUARY 2010 – REVISED SEPTEMBER 2012 www.ti.com APPLICATION INFORMATION 6.8 mH VI = 3.5 V to 17 V 2 TPS62110 VIN VIN EN 3 4 SW SW 15 R3 1 MW R5 8 CI = 10 mF 25 V PG VINA 1 mF 9 AGND 7 5 R6 R4 1 MW 13 LBO 6 FB 10 LBI VO = 1.8 V 14 R1 220 kW Cff 10 pF CO = 2 x 22 mF 6.3 V R2 390 kW SYNC GND GND PwPD PGND PGND 11 A. 12 1 16 For an output voltage lower than 2.5 V, an output capacitor of 33 µF or greater is recommended to improve load transient.
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TPS62110-Q1 www.ti.com SLVSA54A – FEBRUARY 2010 – REVISED SEPTEMBER 2012 REVISION HISTORY Changes from Original (February, 2010) to Revision A Page • Added AEC-Q100 info to Features ....................................................................................................................................... 1 • Removed package column in ordering information table .....................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) TPS62110QRSARQ1 ACTIVE Package Type Package Pins Package Drawing Qty QFN RSA 16 3000 Eco Plan Lead/Ball Finish (2) Green (RoHS & no Sb/Br) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) CU NIPDAU Level-2-260C-1 YEAR (4) -40 to 125 TPS 62110Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS62110QRSARQ1 Package Package Pins Type Drawing QFN RSA 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 3000 330.0 12.4 Pack Materials-Page 1 4.25 B0 (mm) K0 (mm) P1 (mm) 4.25 1.15 8.0 W Pin1 (mm) Quadrant 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS62110QRSARQ1 QFN RSA 16 3000 367.0 367.0 35.
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