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TPS65020

www.ti.com

SLVS607C –SEPTEMBER 2005– REVISED SEPTEMBER 2011

POWER MANAGEMENT IC FOR LI-ION POWERED SYSTEMS

Check for Samples: TPS65020

FEATURES

DESCRIPTION

234

• 1.2 A, 97% Efficient Step-Down Converter for

The TPS65020 is an integrated Power Management

System Voltage (VDCDC1)

IC for applications powered by one Li-Ion or

• 1 A, Up to 95% Efficient Step-Down Converter

Li-Polymer cell, and which require multiple power

for Memory Voltage (VDCDC2)

rails. The TPS65020 provides three highly efficient,

• 800 mA, 90% Efficient Step-Down Converter

step-down converters targeted at providing the core

voltage, peripheral, I/O and memory rails in a

for Processor Core (VDCDC3)

processor based system. All three step-down

• 20 mA LDO/Switch for Real Time Clock (VRTC)

converters enter a low-power mode at light load for

• 2 × 200 mA LDO for SRAM and PLL

maximum efficiency across the widest possible range

• Dynamic Voltage Management for Processor

of load currents. The TPS65020 also integrates two

200-mA LDO voltage regulators, which are enabled

Core

with an external input pin. Each LDO operates with

• Externally Adjustable Reset Delay Time

an input voltage range between 1.5 V and 6.5 V,

• Battery Backup Functionality

allowing them to be supplied from one of the

• Separate Enable Pins for Inductive Converters step-down converters or directly from the main

battery. The two 200-mA LDO voltage regulators are

• I

C™ Compatible Serial Interface

intended for use with the SDRAM and PLL power

• 85-μA Quiescent Current

supply in a Intel PXA270 based system. The serial

• Low Ripple PFM Mode

interface is used for dynamic voltage scaling of the

core voltage, masking interrupts, or for dis/enabling

• Thermal Shutdown Protection

and setting the LDO output voltages. The interface is

• Push Button I/O

compatible with the Fast/Standard mode I

C™

specification, allowing transfers at up to 400 kHz.

APPLICATIONS

The TPS65020 incorporates a push button

• PDA

debounced input and latched output for

• Cellular/Smart Phone

implementation of a push-button turn-on feature,

typically required in smartphones or wireless PDAs.

• Internet Audio Player

• Digital Still Camera

• Digital Radio Player

• Split Supply TMS320™ DSP Family and μP

Solutions:

OMAP™1610, OMAP1710, OMAP330

• Intel

PXA270, etc.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2TMS320, OMAP, PowerPAD are trademarks of Texas Instruments.

3Intel is a registered trademark of Intel Corporation.

C is a trademark of Philips Electronics.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (52 pages)

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TPS65020 SLVS607C – SEPTEMBER 2005 – REVISED SEPTEMBER 2011 www.ti.com POWER MANAGEMENT IC FOR LI-ION POWERED SYSTEMS Check for Samples: TPS65020 FEATURES 1 • 1.
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TPS65020 SLVS607C – SEPTEMBER 2005 – REVISED SEPTEMBER 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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TPS65020 SLVS607C – SEPTEMBER 2005 – REVISED SEPTEMBER 2011 www.ti.com RECOMMENDED OPERATING CONDITIONS (continued) over operating free-air temperature range (unless otherwise noted) Inductor at L1 (2) (2) CI(DCDC1) Input Capacitor at VI(DCDC1) CO(DCDC1) Output Capacitor at VDCDC1 IO(DCDC2) Output current at L2 Inductor at L2 2.2 3.3 (2) 10 2.2 (2) CO(DCDC2) Output Capacitor at VDCDC2 IO(DCDC3) Output current at L3 (2) μF μF 22 Input Capacitor at VDCDC3 (2) μF 10 22 2.2 3.
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TPS65020 SLVS607C – SEPTEMBER 2005 – REVISED SEPTEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS Resetpwron threshold VRTC falling Resetpwron threshold VRTC rising ILK 4 leakage current output inactive high Submit Documentation Feedback MIN TYP MAX –3% 2.4 3% UNIT –3% 2.52 3% V 0.
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TPS65020 SLVS607C – SEPTEMBER 2005 – REVISED SEPTEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.
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TPS65020 SLVS607C – SEPTEMBER 2005 – REVISED SEPTEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 20 33 μA 3 μA SUPPLY PINS: VBACKUP, VSYSIN, VRTC I(q) Operating quiescent current VBACKUP = 3 V, VSYSIN = 0 V; VCC = 2.
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TPS65020 SLVS607C – SEPTEMBER 2005 – REVISED SEPTEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VDCDC1 STEP-DOWN CONVERTER VI Input voltage range, VINDCDC1 IO Maximum output current I(SD) Shutdown supply current in VINDCDC1 DCDC1_EN = GND 0.
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TPS65020 SLVS607C – SEPTEMBER 2005 – REVISED SEPTEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VDCDC2 STEP-DOWN CONVERTER VI Input voltage range, VINDCDC2 IO Maximum output current 2.5 I(SD) Shutdown supply current in VINDCDC2 DCDC2_EN = GND 0.
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TPS65020 SLVS607C – SEPTEMBER 2005 – REVISED SEPTEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VDCDC3 STEP-DOWN CONVERTER VI Input voltage range, VINDCDC3 2.5 IO Maximum output current 800 I(SD) Shutdown supply current in VINDCDC3 DCDC3_EN = GND 0.
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TPS65020 SLVS607C – SEPTEMBER 2005 – REVISED SEPTEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VLDO1 and VLDO2 LOW DROPOUT REGULATORS VI Input voltage range for LDO1, 2 1.5 6.5 V VO LDO1 output voltage range 1 3.3 V VO LDO2 output voltage range 1 3.
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TPS65020 SLVS607C – SEPTEMBER 2005 – REVISED SEPTEMBER 2011 www.ti.
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TPS65020 SLVS607C – SEPTEMBER 2005 – REVISED SEPTEMBER 2011 www.ti.com TERMINAL FUNCTIONS (continued) TERMINAL NAME NO. I/O DESCRIPTION VCC 37 I Power supply for digital and analog circuitry of VDCDC1, VDCDC2, and VDCDC3 dc-dc converters. This must be connected to the same voltage supply as VINDCDC3, VINDCDC1, and VINDCDC2. Also supplies serial interface block DEFDCDC1 10 I Input signal indicating default VDCDC1 voltage, 0 = 3 V, 1 = 3.
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TPS65020 SLVS607C – SEPTEMBER 2005 – REVISED SEPTEMBER 2011 www.ti.
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TPS65020 SLVS607C – SEPTEMBER 2005 – REVISED SEPTEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS Graphs were taken using the EVM with the following inductor/output capacitor combinations: CONVERTER INDUCTOR OUTPUT CAPACITOR OUTPUT CAPACITOR VALUE VDCDC1 VLCF4020-2R2 C2012X5R0J106M 2 × 10 μF VDCDC2 VLCF4020-2R2 C2012X5R0J106M 2 × 10 μF VDCDC3 VLF4012AT-2R2M1R5 C2012X5R0J106M 2 × 10 μF Table 1.
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TPS65020 SLVS607C – SEPTEMBER 2005 – REVISED SEPTEMBER 2011 www.ti.com DCDC2: EFFICIENCY vs OUTPUT CURRENT DCDC2: EFFICIENCY vs OUTPUT CURRENT VI = 2.5 V VI = 3.8 V Efficiency - % Efficiency - % VI = 3.8 V VI = 4.2 V VI = 4.2 V VI = 2.5 V VI = 5 V VI = 5 V o o TA = 25 C VO = 1.8 V PWM Mode TA = 25 C VO = 1.8 V PWM / PFM Mode 0.01 0.1 10 1 100 1k 10 k 0.01 0.1 10 1 IO - Output Current - mA 100 1k 10 k IO - Output Current - mA Figure 3. Figure 4.
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TPS65020 SLVS607C – SEPTEMBER 2005 – REVISED SEPTEMBER 2011 www.ti.com DCDC3: EFFICIENCY vs OUTPUT CURRENT VDCDC1 LINE TRANSIENT RESPONSE Ch1 = VI Ch2 = VO Efficiency - % VI = 3 V IO = 100 mA VO = 3.3 V PWM Mode VI = 3.8 V VI = 2.5 V C1 High 4.74 V C1 Low 3.08 V VI = 4.2 V C2 PK-PK 85 mV VI = 5 V o TA = 25 C VO = 1.3 V Low Ripple PFM Mode 0.01 0.1 10 1 IO - Output Current - mA Figure 7. Figure 8.
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TPS65020 SLVS607C – SEPTEMBER 2005 – REVISED SEPTEMBER 2011 www.ti.com VDCDC1 LOAD TRANSIENT RESPONSE VDCDC2 LOAD TRANSIENT RESPONSE C4 High 1.09 A C4 High 830 mA C4 Low 120 mA C4 Low 90 mA C2 PK-PK 188 mV C2 PK-PK 80 mV VI = 3.8 V VO = 3.3 V PWM Mode Ch2 = VO Ch4 = IO VI = 3.8 V VO = 1.8 V PWM Mode Ch2 = VO Ch4 = IO Figure 11. Figure 12. VDCDC3 LOAD TRANSIENT RESPONSE VDCDC2 OUTPUT VOLTAGE RIPPLE C4 High 730 mA VI = 3.8 V VO = 1.
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TPS65020 SLVS607C – SEPTEMBER 2005 – REVISED SEPTEMBER 2011 www.ti.com VDCDC2 OUTPUT VOLTAGE RIPPLE VO = 1.8 V VI = 3.8 V IO = 1 mA o TA = 25 C Low Ripple PFM Mode VDCDC2 OUTPUT VOLTAGE RIPPLE VI = 3.8 V VO = 1.8 V IO = 1 mA TA = 25oC PWM Mode C2 PK-PK 7.7 mV Figure 15. Figure 16. STARTUP VDCDC1, VDCDC2, AND VDCDC3 STARTUP LDO1 AND LDO2 ENABLE ENABLE VDCDC1 LDO1 VDCDC2 LDO2 VDCDC3 Figure 17. 18 Figure 18.
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TPS65020 SLVS607C – SEPTEMBER 2005 – REVISED SEPTEMBER 2011 www.ti.com LDO1 LINE TRANSIENT RESPONSE Ch1 = VI Ch2 = VO Ch1 = VI Ch2 = VO IO = 25 mA VO = 1.1 V o TA = 25 C LDO2 LINE TRANSIENT RESPONSE C1 High 3.83 V Ch1 = VI Ch2 = VO IO = 25 mA VO = 3.3 V TA = 25oC C1 Low 3.29 V C1 Low 3.99 V C2 PK-PK 6.2 mV C2 PK-PK 6.1 mV Figure 19. Figure 20. VRTC LINE TRANSIENT RESPONSE LDO1 LOAD TRANSIENT RESPONSE IO = 10 mA VO = 3 V o TA = 25 C C1 High 4.51 V C1 High 3.82 V C4 High 48.9 mA C1 Low 3.
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TPS65020 SLVS607C – SEPTEMBER 2005 – REVISED SEPTEMBER 2011 www.ti.com LDO2 LOAD TRANSIENT RESPONSE VRTC LOAD TRANSIENT RESPONSE C4 High 47.8 mA C4 High 21.4 mA C4 Low -2.9 mA C4 Low -1.4 mA C2 PK-PK 40.4 mV VI = 4 V VO = 3.3 V o TA = 25 C Ch2 = VO Ch4 = IO C2 PK-PK 76 mV Ch2 = VO Ch4 = IO Figure 23. 20 VI = 3.8 V VO = 3 V o TA = 25 C Figure 24.
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TPS65020 www.ti.com SLVS607C – SEPTEMBER 2005 – REVISED SEPTEMBER 2011 DETAILED DESCRIPTION VRTC OUTPUT AND OPERATION WITH OR WITHOUT BACKUP BATTERY The VRTC pin is an always-on output, intended to supply up to 20 mA to a permanently required rail. This is the VCC_BATT rail of the Intel® PXA270 Bulverde processor for example. In applications using a backup battery, the backup voltage can be either directly connected to the TPS65020 VBACKUP pin if a Li-Ion cell is used, or via a boost converter (e.g.
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TPS65020 SLVS607C – SEPTEMBER 2005 – REVISED SEPTEMBER 2011 VSYSIN Vref V_VSYSIN priority #1 www.ti.com VCC VBACKUP Vref V_VBACKUP priority #2 V_VSYSIN V_VBACKUP EN VRTC LDO priority #3 VRTC Vref A. V_VSYSIN, V_VBACKUP thresholds: falling = 2.55 V, rising = 2.65 V ±3% B. RESPWRON thresholds: falling = 2.4 V, rising = 2.52 V ±3% RESPWRON Figure 25. STEP-DOWN CONVERTERS, VDCDC1, VDCDC2, and VDCDC3 The TPS65020 incorporates three synchronous step-down converters operating typically at 1.
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TPS65020 SLVS607C – SEPTEMBER 2005 – REVISED SEPTEMBER 2011 www.ti.com During PWM operation, the converters use a unique fast response voltage mode controller scheme with input voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch is turned on.
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TPS65020 SLVS607C – SEPTEMBER 2005 – REVISED SEPTEMBER 2011 www.ti.com If the load is below the delivered current then the output voltage rises until the same threshold is crossed in the other direction. All switching activity ceases, reducing the quiescent current to a minimum until the output voltage has again dropped below the threshold. The power save mode is exited, and the converter returns to PWM mode if either of the following conditions are met: 1.
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TPS65020 SLVS607C – SEPTEMBER 2005 – REVISED SEPTEMBER 2011 www.ti.com ACTIVE DISCHARGE WHEN DISABLED When the VDCDC1, VDCDC2, and VDCDC3 converters are disabled, due to an UVLO, DCDCx_EN or OVERTEMP condition, it is possible to actively pull down the outputs. This feature is disabled per default and is individually enabled via the CON_CTRL2 register in the serial interface.
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TPS65020 SLVS607C – SEPTEMBER 2005 – REVISED SEPTEMBER 2011 www.ti.com Table 2. Control Pins and Status Outputs for DC-DC Converters PIN NAME INPUT OUTPUT FUNCTION DEFDCDC3 I Defines the default voltage of the VDCDC3 switching converter. DEFDCDC3 = 0 defaults VDCDC3 to 1.3 V, DEFDCDC3 = VCC defaults VDCDC3 to 1.55 V. DEFDCDC2 I Defines the default voltage of the VDCDC2 switching converter. DEFDCDC2 = 0 defaults VDCDC2 to 1.8 V, DEFDCDC2 = VCC defaults VDCDC2 to 2.5 V.
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TPS65020 SLVS607C – SEPTEMBER 2005 – REVISED SEPTEMBER 2011 www.ti.com TIMING DIAGRAMS HOT_RESET tDEGLITCH RESPWRON VO DCDC3 tNRESPWRON default voltage any voltage set 2 with I C interface Figure 26. HOT_RESET Timing VCC 1.9 V 0.8 V 2.35 V 1.9 V 1.2 V 2.47 V UVLO* 2.52 V VRTC 2.4 V 3V RESPWRON tNRESPWRON DCDCx_EN Ramp Within 800 ms VODCDCx 1.8 V slope depending on load LDO_EN VOLDOx 1.5 V *... Internal Signal Figure 27.
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TPS65020 SLVS607C – SEPTEMBER 2005 – REVISED SEPTEMBER 2011 www.ti.com VCC RESPWRON T NRESPWRON DCDC1_EN DCDC2_EN 3.3 V or 3 V VODCDC1 Ramp Within 800 ms VODCDC2 Ramp Within 800 ms 2.5 V or 1.8 V Ramp Within 800 ms DEFCORE register Default Value Set Higher Output Voltage for DCDC3 GO bit in CON_CTRL2 Cleared Automatically Automatically Set to Default Value DCDC3_EN VODCDC3 1.3 V or 1.55 V Ramp Within 800 ms 1.3 V or 1.
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TPS65020 SLVS607C – SEPTEMBER 2005 – REVISED SEPTEMBER 2011 www.ti.com VCC 0.8 V Threshold Depending on External Voltage Divider Connected to VCC PWRFAIL PB_IN (GPIO1) tDEGLITCH tDEGLITCH tDEGLITCH PB_OUT (GPIO2) ON-OFF Figure 29. PB-ON-OFF Timing SERIAL INTERFACE The serial interface is compatible with the standard and fast mode I2C specifications, allowing transfers at up to 400 kHz.
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TPS65020 SLVS607C – SEPTEMBER 2005 – REVISED SEPTEMBER 2011 www.ti.com DATA CLK S P START Condition STOP Condition Figure 31. START and STOP Conditions SCLK SDAT A6 Start A5 A0 A4 R/W AC K 0 0 R6 R7 R5 R0 AC K D5 D6 D7 D0 0 0 Register Address Slave Address AC K Stop Data Note: SLAVE = TPS65020 Figure 32.
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TPS65020 SLVS607C – SEPTEMBER 2005 – REVISED SEPTEMBER 2011 www.ti.com DATA t(BUF) th(STA) t(LOW) tf tr CLK t(HIGH) th(STA) tsu(STA) STO tsu(STO) tsu(DATA) th(DATA) STA STA STO Figure 35.
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TPS65020 SLVS607C – SEPTEMBER 2005 – REVISED SEPTEMBER 2011 www.ti.com PGOODZ.
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TPS65020 SLVS607C – SEPTEMBER 2005 – REVISED SEPTEMBER 2011 www.ti.com The MASK register can be used to mask particular fault conditions from appearing at the INT pin. MASK = 1 masks PGOODZ. MASK.
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TPS65020 SLVS607C – SEPTEMBER 2005 – REVISED SEPTEMBER 2011 www.ti.com The CON_CTRL register is used to force any or all of the converters into forced PWM operation, when low output voltage ripple is vital. It is also used to control the phase shift between the three converters in order to minimize the input rms current, hence reduce the required input blocking capacitance. The DCDC1 converter is taken as the reference and consequently has a fixed zero phase shift. CON_CTRL.
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TPS65020 SLVS607C – SEPTEMBER 2005 – REVISED SEPTEMBER 2011 www.ti.com The CON_CTRL2 register can be used to take control the inductive converters. CON_CTRL.
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TPS65020 SLVS607C – SEPTEMBER 2005 – REVISED SEPTEMBER 2011 www.ti.com DEFCORE.
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TPS65020 SLVS607C – SEPTEMBER 2005 – REVISED SEPTEMBER 2011 www.ti.
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TPS65020 SLVS607C – SEPTEMBER 2005 – REVISED SEPTEMBER 2011 www.ti.com LDO_CTRL. Register Address: 08h (read/write) LDO_CTRL B7 Bit name and function B6 B5 B4 B2 B1 B0 LDO2_2 LDO2_1 LDO2_0 LDO1_2 LDO1_1 LDO1_0 0 1 0 0 1 1 UVLO UVLO UVLO UVLO UVLO UVLO R/W R/W R/W R/W R/W R/W Default Default value loaded by: Default Value: 23h Read/Write B3 The LDO_CTRL registers can be used to set the output voltage of LDO1 and LDO2.
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TPS65020 SLVS607C – SEPTEMBER 2005 – REVISED SEPTEMBER 2011 www.ti.com See Table 3 and the typical applications for possible inductors. Table 3. Tested Inductors DEVICE DCDC3 converter DCDC2 converter DCDC1 converter INDUCTOR VALUE TYPE COMPONENT SUPPLIER 3.3 μH CDRH2D14NP-3R3 Sumida 3.3 μH LPS3010-332 Coilcraft 3.3 μH VLF4012AT-3R3M1R3 TDK 2.2 μH VLF4012AT-2R2M1R5 TDK 2.2 μH NR3015T2R2 Taiyo-Yuden 3.3 μH CDRH2D18/HPNP-3R3 Sumida 3.3 μH VLF4012AT-3R3M1R3 TDK 2.
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TPS65020 SLVS607C – SEPTEMBER 2005 – REVISED SEPTEMBER 2011 www.ti.com Table 4.
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TPS65020 SLVS607C – SEPTEMBER 2005 – REVISED SEPTEMBER 2011 www.ti.com VRTC Output The VRTC output is typically connected to the Vcc_Batt pin of a Intel PXA270 processor. During power-up of the processor, the TPS65020 internally switches from the LDO or the backup battery to the system voltage connected at the VSYSIN pin (see Figure 25). It is required to add a capacitor of 4.7-μF minimum to the VRTC pin, even the output may be unused. LDO1 and LDO2 The LDOs default voltage is 1.1 V for LDO2 and 1.
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TPS65020 SLVS607C – SEPTEMBER 2005 – REVISED SEPTEMBER 2011 www.ti.com APPLICATION INFORMATION Layout Considerations As for all switching power supplies, the layout is an important step in the design. Proper function of the device demands careful attention to PCB layout. Care must be taken in board layout to get the specified performance. If the layout is not carefully done, the regulators may show poor line and/or load regulation, and stability issues as well as EMI problems.
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TPS65020 SLVS607C – SEPTEMBER 2005 – REVISED SEPTEMBER 2011 www.ti.
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TPS65020 SLVS607C – SEPTEMBER 2005 – REVISED SEPTEMBER 2011 www.ti.com TYPICAL CONFIGURATION FOR THE Intel® PXA270 BULVERDE PROCESSOR Vcc_IO Vcc 10R PWRFAIL Vcc 1 mF 10 mF 10 mF 10 mF LOW_BATT VINDCDC1 GPIOx VRTC Vcc_Batt 4.7 mF DCDC1_EN VINDCDC3 VDCDC1 TPS65020 PWRFAIL_SNS L1 HOT_RESET 2.2 mH 2.2 mH 22mF VIN_LDO VDCDC1 PB_OUT Vcc 3V backup battery 1.8 V; 2.5 V; 3 V; 3.3 V Vcc_BB 1.8 V; 2.5 V; 3 V; 3.3 V Vcc_MEM 1.8 V; 2.5 V; 3 V; 3.3 V Vcc_USIM 1.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS65020RHAT Package Package Pins Type Drawing VQFN RHA 40 SPQ 250 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 180.0 16.4 Pack Materials-Page 1 6.3 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.3 1.1 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS65020RHAT VQFN RHA 40 250 210.0 185.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.