Datasheet

t
DEGLITCH
t
DEGLITCH
t
DEGLITCH
PB_IN
(GPIO1)
PB_OUT
(GPIO2)
ON-OFF
V
CC
PWRFAIL
ThresholdDependingonExternalVoltageDividerConnectedtoV
CC
0.8V
DataLine
Stable;
DataValid
DATA
CLK
Change
ofData
Allowed
TPS65020
www.ti.com SLVS607C –SEPTEMBER 2005– REVISED SEPTEMBER 2011
Figure 29. PB-ON-OFF Timing
SERIAL INTERFACE
The serial interface is compatible with the standard and fast mode I
2
C specifications, allowing transfers at up to
400 kHz. The interface adds flexibility to the power supply solution, enabling most functions to be programmed to
new values depending on the instantaneous application requirements and charger status to be monitored.
Register contents remain intact as long as VCC remains above 2 V. The TPS65020 has a 7bit address:
1001000, other addresses are available upon contact with the factory. Attempting to read data from the register
addresses not listed in this section results in FFh being read out.
For normal data transfer, DATA is allowed to change only when CLK is low. Changes when CLK is high are
reserved for indicating the start and stop conditions. During data transfer, the data line must remain stable
whenever the clock line is high. There is one clock pulse per bit of data. Each data transfer is initiated with a start
condition and terminated with a stop condition. When addressed, the TPS65020 device generates an
acknowledge bit after the reception of each byte. The master device (microprocessor) must generate an extra
clock pulse that is associated with the acknowledge bit. The TPS65020 device must pull down the DATA line
during the acknowledge clock pulse so that the DATA line is a stable low during the high period of the
acknowledge clock pulse. The DATA line is a stable low during the high period of the acknowledge–related clock
pulse. Setup and hold times must be taken into account. During read operations, a master must signal the end of
data to the slave by not generating an acknowledge bit on the last byte that was clocked out of the slave. In this
case, the slave TPS65020 device must leave the data line high to enable the master to generate the stop
condition
Figure 30. Bit Transfer on the Serial Interface
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