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FEATURES APPLICATIONS

DESCRIPTION

TPS65050, TPS65051, TPS65052

TPS65054, TPS65056

SLVS710A – JANUARY 2007 – REVISED AUGUST 2007

www.ti.com

6-CHANNEL POWER MGMT IC WITH TWO STEP-DOWN CONVERTERS

AND 4 LOW-INPUT VOLTAGE LDOs

• Cell Phones, Smart-Phones

• Up To 95% Efficiency

• WLAN

• Output Current for DC/DC Converters:

• PDAs, Pocket PCs

– TPS65050: 2 x 0.6 A

• OMAP™ and Low-Power TMS320™ DSP

– TPS65051: DCDC1 = 1 A; DCDC2 = 0.6 A

Supply

– TPS65052: DCDC1 = 1 A; DCDC2 = 0.6 A

• Samsung S3C24xx application processor

– TPS65054: 2 x 0.6 A

Supply

– TPS65056: DCDC1 = 1 A; DCDC2 = 0.6 A

• Portable Media Players

• Output Voltages for DC/DC Converters

– TPS65050: Externally Adjustable

The TPS6505x are integrated Power Management

– TPS65051: Externally Adjustable

ICs for applications powered by one Li-Ion or

– TPS65052: DCDC1 = Fixed at 3.3 V;

Li-Polymer cell, which require multiple power rails.

DCDC2 = 1 V / 1.3 V for Samsung

The TPS6505x provides two efficient, 2.25-MHz

Application Processors

step-down converters targeted at providing the core

– TPS65054: DCDC1 = Externally Adjustable;

voltage and I/O voltage in a processor based system.

DCDC2 = 1.3 V / 1.05 V for OMAP™1710

Both step-down converters enter a low power mode

at light load for maximum efficiency across the widest

Processor

possible range of load currents.

– TPS65056: DCDC1 = Fixed at 3.3 V;

DCDC2 = 1 V / 1.3 V for Samsung

For low noise applications, the devices can be forced

Application Processors

into fixed frequency PWM mode by pulling the MODE

pin high. In the shutdown mode, the current

• V

Range for DC/DC Converters

consumption is reduced to less than 1 μ A. The

From 2.5 V to 6 V

devices allow the use of small inductors and

• 2.25-MHz Fixed Frequency Operation

capacitors to achieve a small solution size. TPS6505x

• Power Save Mode at Light Load Current provides an output current of up to 1 A on each

DC/DC converter. The TPS6505x also integrate two

• 180 ° Out-of-Phase Operation

400-mA LDO and two 200-mA LDO voltage

• Output Voltage Accuracy in PWM mode ± 1%

regulators, which can be turned on/off using separate

• Low Ripple PFM Mode

enable pins on each LDO. Each LDO operates with

an input voltage range between 1.5 V and 6.5 V

• Total Typical 32- μ A Quiescent Current for Both

allowing them to be supplied from one of the

DC/DC Converters

step-down converters or directly from the main

• 100% Duty Cycle for Lowest Dropout

battery.

• Two General-Purpose 400-mA, High PSRR

Four digital input pins are used to set the output

LDOs

voltage of the LDOs from a set of 16 different

• Two General-Purpose 200-mA, High PSRR

combinations for LDO1 to LDO4 on TPS65050 and

LDOs

TPS65052. In TPS65051, TPS65054 and TPS65056,

the LDO voltages are adjustable using external

• V

range for LDOs from 1.5 V to 6.5 V

resistor dividers.

• Digital Voltage Selection for the LDOs

The TPS6505x come in a small 32-pin leadless

• Available in a 4 mm x 4 mm 32-Pin QFN

package (4 mm x 4 mm QFN) with a 0.4 mm pitch.

Package

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2 OMAP, TMS320, PowerPAD are trademarks of Texas Instruments.

UNLESS OTHERWISE NOTED this document contains

PRODUCTION DATA information current as of publication date.

Products conform to specifications per the terms of Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (41 pages)

PAGE 1
TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710A – JANUARY 2007 – REVISED AUGUST 2007 6-CHANNEL POWER MGMT IC WITH TWO STEP-DOWN CONVERTERS AND 4 LOW-INPUT VOLTAGE LDOs FEATURES APPLICATIONS • Up To 95% Efficiency • Output Current for DC/DC Converters: – TPS65050: 2 x 0.6 A – TPS65051: DCDC1 = 1 A; DCDC2 = 0.6 A – TPS65052: DCDC1 = 1 A; DCDC2 = 0.6 A – TPS65054: 2 x 0.6 A – TPS65056: DCDC1 = 1 A; DCDC2 = 0.
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TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710A – JANUARY 2007 – REVISED AUGUST 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710A – JANUARY 2007 – REVISED AUGUST 2007 RECOMMENDED OPERATING CONDITIONS (continued) over operating free-air temperature range (unless otherwise noted) MIN VO IO NOM MAX Output voltage range for LDO1 and LDO2 1 3.6 Output voltage range for LDO3 and LDO4 1 3.
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TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710A – JANUARY 2007 – REVISED AUGUST 2007 ELECTRICAL CHARACTERISTICS (continued) VCC = VINDCDC1/2 = 3.6 V, EN = VCC, MODE = GND, L = 2.2 μH, CO = 10 μF. TA = -40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted).
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TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710A – JANUARY 2007 – REVISED AUGUST 2007 ELECTRICAL CHARACTERISTICS (continued) VCC = VINDCDC1/2 = 3.6 V, EN = VCC, MODE = GND, L = 2.2 μH, CO = 10 μF. TA = -40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted).
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TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710A – JANUARY 2007 – REVISED AUGUST 2007 ELECTRICAL CHARACTERISTICS (continued) VCC = VINDCDC1/2 = 3.6 V, EN = VCC, MODE = GND, L = 2.2 μH, CO = 10 μF. TA = -40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted).
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TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.
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TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710A – JANUARY 2007 – REVISED AUGUST 2007 TERMINAL FUNCTIONS (continued) TERMINAL I/O DESCRIPTION NAME TPS65050 TPS65051 TPS65052 TPS65054 TPS65056 PGND1 23 23 23 23 23 I GND for converter 1 PGND2 19 19 19 19 19 I GND for converter 2 AGND 2 2 2 2 2 I Analog GND, connect to PGND and PowerPad™ L2 20 20 20 20 20 O Switch Pin of converter 2. Connected to Inductor.
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TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710A – JANUARY 2007 – REVISED AUGUST 2007 FUNCTIONAL BLOCK DIAGRAM TPS65050 VINDCDC1/2 1W Vbat VCC 10 mF 1 mF 2.2 mH DCDC1 (I/O) L1 EN_DCDC1 ENABLE STEP-DOWN CONVERTER 600 mA MODE DEFLDO1 DEFLDO2 DEFLDO3 DEFLDO4 FB_DCDC1 PGND1 R1 Cff 10 mF R2 Interface L2 DCDC2 (core) STEP-DOWN CONVERTER 600 mA EN_DCDC2 ENABLE VLDO2 EN_LDO2 ENABLE PGND2 VIN_LDO3/4 VLDO3 ENABLE ENABLE R4 4.7 mF VLDO2 4.
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TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710A – JANUARY 2007 – REVISED AUGUST 2007 TPS65051 VINDCDC1/2 1W Vbat VCC 22 mF 1 mF 2.2 mH DCDC1 (I/O) ENABLE L1 EN_DCDC1 STEP-DOWN CONVERTER 1A FB_DCDC1 PGND1 R1 Cff 10 mF R2 MODE L2 DCDC2 (core) ENABLE VIN ENABLE STEP-DOWN CONVERTER 600 mA EN_DCDC2 VDCDC2 2.2 mH R3 DEFDCDC2 PGND2 10 mF R4 VLDO1 VIN_LDO1 VLDO1 EN_LDO1 400-mA LDO FB1 R5 4.7 mF R6 VIN ENABLE VIN_LDO2 VLDO2 EN_LDO2 400-mA LDO VLDO2 FB2 R7 4.
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TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710A – JANUARY 2007 – REVISED AUGUST 2007 TPS65052 VINDCDC1/2 1W Vbat VCC 10 mF 1 mF 3.3 mH DCDC1 (I/O) ENABLE MODE DEFLDO1 DEFLDO2 DEFLDO3 DEFLDO4 EN_DCDC1 STEP-DOWN CONVERTER 1A L1 FB_DCDC1 Interface L2 DCDC2 (core) 2.2 mH VDCDC2 ENABLE 1 V/1.3 V VIN ENABLE VIN ENABLE VIN ENABLE ENABLE 10 mF PGND1 STEP-DOWN CONVERTER 600 mA EN_DCDC2 DEFDCDC2 10 mF PGND2 VLDO1 VIN_LDO1 VLDO1 EN_LDO1 4.
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TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710A – JANUARY 2007 – REVISED AUGUST 2007 TPS65054 VINDCDC1/2 1W Vbat VCC 22 mF 1 mF 2.2 mH DCDC1 (I/O) ENABLE L1 EN_DCDC1 STEP-DOWN CONVERTER 600 mA FB_DCDC1 PGND1 R1 Cff 10 mF R2 MODE L2 DCDC2 (core) 2.2 mH VDCDC2 ENABLE 1.3 V/1.05 V VIN ENABLE STEP-DOWN CONVERTER 600 mA EN_DCDC2 DEFDCDC2 10 mF PGND2 VLDO1 VIN_LDO1 VLDO1 EN_LDO1 400-mA LDO FB1 R5 4.
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TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710A – JANUARY 2007 – REVISED AUGUST 2007 TPS65056 VINDCDC1/2 1W Vbat VCC 22 mF 1 mF 3.3 mH DCDC1 (I/O) ENABLE L1 EN_DCDC1 STEP-DOWN CONVERTER 1A FB_DCDC1 10 mF PGND1 MODE L2 2.2 mH DCDC2 (core) ENABLE 1 V / 1.3 V VIN ENABLE STEP-DOWN CONVERTER 600 mA EN_DCDC2 DEFDCDC2 VDCDC2 10 mF PGND2 VLDO1 VIN_LDO1 VLDO1 EN_LDO1 400-mA LDO FB1 R5 4.7 mF R6 VIN ENABLE VIN_LDO2 VLDO2 EN_LDO2 400-mA LDO VLDO2 FB2 R7 4.
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TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.
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TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710A – JANUARY 2007 – REVISED AUGUST 2007 EFFICIENCY vs OUTPUT CURRENT EFFICIENCY vs OUTPUT CURRENT 100 100 3.3 V 90 90 80 80 70 3.8 V 60 Efficiency − % 4.2 V 50 5V 40 30 3.3 V 40 4.2 V 20 VO = 1.3 V o TA = 25 C PFM Mode 10 0.1 0.001 0.01 IO − Output Current − A 10 0 0.0001 1 0.1 0.001 0.01 IO − Output Current − A Figure 3. Figure 4.
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TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710A – JANUARY 2007 – REVISED AUGUST 2007 LDO1 TO LDO4 STARTUP TIMING VI = 3.6 V CH1 (VLDO1) o TA = 25 C Mode = Low 1 V/div 1 V/div 1 V/div CH2 (VLDO2) CH3 (VLDO3) CH3 (VDCDC2 = 1.5 V) 1 V/div CH4 (VLDO1) EN 1 V/div CH1 (EN) 5 V/div 5 V/div DCDC1 STARTUP TIMING CH2 (VDCDC1 = 3.3 V) Load DCDC1 = 600 mA Load DCDC2 = 600 mA 1 V/div 1 V/div CH4 (VLDO4) t − Time = 200 ms/div Figure 7.
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TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710A – JANUARY 2007 – REVISED AUGUST 2007 CH1 (VDCDC2) VI = 3.6 V DCDC2 LOAD TRANSIENT RESPONSE 50 mV/div 50 mV/div DCDC2 LOAD TRANSIENT RESPONSE CH1 (VDCDC2) VI = 3.6 V o TA = 25 C Mode = High TA = 25oC Mode = Low VDCDC2 = 1.5 V ENDCDC1 = Low ENDCDC2 = High Load Current = 60 mA to 540 mA CH2 I(DCDC2) 200 mA/div 200 mA/div CH2 I(DCDC2) VDCDC2 = 1.
PAGE 18
TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710A – JANUARY 2007 – REVISED AUGUST 2007 LDO4 LOAD TRANSIENT RESPONSE 50 mV/div 50 mV/div LDO1 LOAD TRANSIENT RESPONSE CH1 (VLDO1) CH1 (VLDO4) VI = 3.6 V VLDO4 = 1.3 V VLDO4 = 20 mA to 180 mA o TA = 25 C VI = 3.6 V o TA = 25 C VLDO1 = 3.3 V VLDO1 = 40 mA to 360 mA CH2 I(LDO4) 200 mA/div 200 mA/div CH2 I(LDO1) t − Time = 100 ms/div t − Time = 100 ms/div Figure 15. Figure 16.
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TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710A – JANUARY 2007 – REVISED AUGUST 2007 DETAILED DESCRIPTION Operation The TPS6505x include each two synchronous step-down converters. The converters operate with 2.25-MHz (typical) fixed frequency pulse width modulation (PWM) at moderate to heavy load currents. At light load currents, the converters automatically enter Power Save Mode and operate with PFM (Pulse Frequency Modulation).
PAGE 20
TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710A – JANUARY 2007 – REVISED AUGUST 2007 Power-Save Mode The Power Save Mode is enabled with the Mode pin set to 0. If the load current decreases, the converters enters Power Save Mode operation automatically. During Power Save Mode, the converters operate with reduced switching frequency in PFM mode, and with a minimum quiescent current to maintain high efficiency.
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TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710A – JANUARY 2007 – REVISED AUGUST 2007 Soft Start The two converters have an internal soft start circuit that limits the inrush current during start-up. During soft start, the output voltage ramp up is controlled as shown in Figure 20. EN 95% 5% VOUT tStart tRAMP Figure 20.
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TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710A – JANUARY 2007 – REVISED AUGUST 2007 Pulling the MODE pin high forces both converters to operate constantly in the PWM mode even at light load currents. The advantage is the converters operate with a fixed frequency that allows simple filtering of the switching frequency for noise sensitive applications. In this mode, the efficiency is lower compared to the power save mode during light loads.
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TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710A – JANUARY 2007 – REVISED AUGUST 2007 Push-Button ON-OFF (PB-ON-OFF) The TPS65050 provides a PB-ON-OFF functionality instead of supervising a voltage with the threshold and hysteresis inputs. The output at PB_OUT is held low after voltage is applied at VCC. Only after the input at PB-IN is pulled high once, the output driver at PB_OUT goes to its inactive state, driven high with its external pullup resistor.
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TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710A – JANUARY 2007 – REVISED AUGUST 2007 Low Dropout Voltage Regulators The low dropout voltage regulators are designed to operate well with small ceramic input and output capacitors. They operate with input voltages down to 1.5 V. The LDOs offer a maximum dropout voltage of 280 mV at rated output current. Each LDO supports a current limit feature. The LDOs are enabled by the EN_LDO1, ENLDO2, EN_LDO3 and EN_LDO4 pin.
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TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710A – JANUARY 2007 – REVISED AUGUST 2007 APPLICATION INFORMATION Output Voltage Setting Converter 1 (DCDC1) The output voltage of converter 1 can be set by an external resistor network. The output voltage can be calculated using Equation 4. R1 VO = Vref x 1 + R2 (4) ( ) with an internal reference voltage Vref, 0.6 V . Setting the total resistance of R1 + R2 to less than 1 MΩ is recommended.
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TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710A – JANUARY 2007 – REVISED AUGUST 2007 V(DEFDCDC2) = 0.6 V VO = V(DEFDCDC2) x R3 + R4 R4 R3 = R4 x ( VO V(DEFDCDC2) ) - R4 (5) See Table 3 for typical resistor values: Table 3. Typical Resistor Values OUTPUT VOLTAGE R1 R2 NOMINAL VOLTAGE Typical CFF 3.3 V 680 kΩ 150 kΩ 3.32 V 47 pF 3V 510 kΩ 130 kΩ 2.95 V 47 pF 2.85 V 560 kΩ 150 kΩ 2.84 V 47 pF 2.5 V 510 kΩ 160 kΩ 2.51 V 47 pF 1.8 V 300 kΩ 150 kΩ 1.
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TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710A – JANUARY 2007 – REVISED AUGUST 2007 Table 4. Tested Inductors Inductor Type Inductor Value Supplier LPS3010 2.2 μH Coilcraft LPS3015 3.3 μH Coilcraft LPS4012 2.2 μH Coilcraft VLF4012 2.
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TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710A – JANUARY 2007 – REVISED AUGUST 2007 Low Drop Out Voltage Regulators (LDOs) The output voltage of all 4 LDOs in TPS65051, TPS65054 and TPS65056 are set by an external resistor network. The output voltage is calculated using Equation 9: R5 VO = Vref x 1 + R6 (9) ( ) with an internal reference voltage, Vref, 1 V (typical) Setting the total resistance of R5 + R6 to less than 1 MΩ is recommended.
PAGE 29
TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710A – JANUARY 2007 – REVISED AUGUST 2007 1W Vbat VINDCDC1/2 VCC Vbat 10 mF 1 mF 2.2 mH L1 GND GND GND Vbat Vbat FB_DCDC1 MODE Vout1 = 2.85 V R1 10 mF DEFLDO1 DEFLDO2 DEFLDO3 DEFLDO4 PGND1 R2 2.2 mH TPS65050 Vbat Vbat Cff L2 Vout2 = 1.575 V VDCDC2 PB_IN R3 DEFDCDC2 PGND2 PB_OUT VLDO1 10 mF R4 VLDO1 = 3.3 V 4.7 mF EN_DCDC1 EN_LDO1 VLDO2 VDCDC1 EN_DCDC2 VLDO2 = 2.5 V 4.7 mF EN_LDO2 VLDO3 EN_LDO3 VLDO3 = 1.
PAGE 30
TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710A – JANUARY 2007 – REVISED AUGUST 2007 Vbat PB_IN 32 ms EN_DCDC1 EN_LDO1 Vout1 32 ms 1.2V VLDO1 170 ms EN_DCDC2 EN_LDO3 EN_LDO4 EN_LDO2 Vout2 170 ms VLDO2 VLDO3 VLDO4 Figure 25. Power Up Timing RESET TPS65051, TPS65052, TPS65054 and TPS65056 contain a comparator that are used to supervise a voltage connected to an external voltage divider, and generate a reset signal if the voltage is lower than the threshold.
PAGE 31
TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710A – JANUARY 2007 – REVISED AUGUST 2007 ( R3 + R4 = R5 x VH Vref ) - 1 VH - VL R4 = R5 x VL 1W Vbat (11) VINDCDC1/2 VCC 2.2 mH 2.2 mH 1 mF L1 FB_DCDC1 R1 Cff Vout1 = 2.85 V 10 mF PGND1 R2 TPS65051 L2 VDCDC2 Vbat Vout1 R3 R4 1 MW 2.2 mH R3 DEFDCDC2 HYSTERESIS PGND2 THRESHOLD VLDO1 R5 10 mF R4 R5 FB1 Vout2 = 1.575 V VLDO1 = 3.3 V 4.7 mF RESET R6 Vbat VLDO2 EN_DCDC1 R7 FB2 EN_DCDC2 VLDO2 = 1.8 V 4.
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TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710A – JANUARY 2007 – REVISED AUGUST 2007 Revision History Changes from Original (January 2007) to Revision A .................................................................................................... Page • • • • • 32 Added quantities of 3000 parts to ordering information note ................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing TPS65050RSMR VQFN RSM 32 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 TPS65050RSMT VQFN RSM 32 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 TPS65051RSMR VQFN RSM 32 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS65050RSMR VQFN RSM 32 3000 367.0 367.0 35.0 TPS65050RSMT VQFN RSM 32 250 210.0 185.0 35.0 TPS65051RSMR VQFN RSM 32 3000 367.0 367.0 35.0 TPS65051RSMR VQFN RSM 32 3000 367.0 367.0 35.0 TPS65051RSMT VQFN RSM 32 250 210.0 185.0 35.0 TPS65051RSMT VQFN RSM 32 250 210.0 185.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.