TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 www.ti.com SLVS950G – JULY 2009 – REVISED MAY 2013 Single Chip Power Solution for Battery Powered Systems Check for Samples: TPS65070, TPS65072, TPS65073, TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 FEATURES 1 • 2 • • • • • Charger/Power Path Management: – 2A Output Current on the Power Path – Linear Charger; 1.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 SLVS950G – JULY 2009 – REVISED MAY 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 www.ti.com SLVS950G – JULY 2009 – REVISED MAY 2013 RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT BATTERY CHARGER AND POWER PATH VIN Input voltage for power path manager at pins AC or USB 4.30 17 Input voltage for power path manager at pins AC or USB, charger and power path active (no overvoltage lockout) 4.30 5.8 3.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 SLVS950G – JULY 2009 – REVISED MAY 2013 www.ti.com RECOMMENDED OPERATING CONDITIONS (continued) MIN NOM MAX UNIT CAC Input Capacitor at AC 1 μF CUSB Input Capacitor at USB 1 μF CBAT Capacitor at BAT pin μF 10 μF CSYS Capacitor at SYS pin 22 CBYPASS Capacitor at BYPASS pin 10 μF CINT_LDO Capacitor at INT_LDO pin 2.2 μF CAVDD6 Capacitor at AVDD6 pin 4.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 www.ti.com SLVS950G – JULY 2009 – REVISED MAY 2013 DCDC1 CONVERTER PARAMETER TEST CONDITIONS VVINDCDC1 Input voltage range IO Maximum output except TPS650701,TPS650702 IO Maximum output for TPS650701, TPS650702 RDS(ON) High side MOSFET on-resistance ILH High side MOSFET leakage current MIN Connected to SYS pin TYP 2.8 MAX V 600 mA 1200 mA VINDCDC1 = 2.8 V 150 300 VINDCDC1 = 3.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 SLVS950G – JULY 2009 – REVISED MAY 2013 www.ti.com DCDC2 CONVERTER PARAMETER VVINDCDC TEST CONDITIONS Input voltage range Connected to SYS pin MIN TYP 2.8 MAX 6.3 UNIT V 2 IO TPS65072/701/702/721/73/731/ 732 Vin > 2.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 www.ti.com SLVS950G – JULY 2009 – REVISED MAY 2013 DCDC3 CONVERTER PARAMETER VVINDCDC TEST CONDITIONS Input voltage range MIN Connected to SYS pin 2.8 TYP MAX 6.3 UNIT V 3 IO Maximum output current TPS65072, TPS650721 Vin > 2.8 V 600 mA IO Maximum output current TPS650701, TPS650702 Vin > 2.8 V 800 mA IO Maximum output current TPS65070, TPS65073, TPS650731, TPS650732 Vin > 2.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 SLVS950G – JULY 2009 – REVISED MAY 2013 www.ti.com VLDO1 and VLDO2 LOW DROPOUT REGULATORS MAX UNIT VINLDO Input voltage range for LDO1, LDO2 PARAMETER 1.8 6.3 (1) V VLDO1 LDO1 output voltage range 1.0 3.3 V VLDO2 LDO2 output voltage range 0.725 3.3 V IO Output current for LDO1 200 mA VLDO1 LDO1 default output voltage For TPS65072 1.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 www.ti.com SLVS950G – JULY 2009 – REVISED MAY 2013 wLED BOOST CONVERTER PARAMETER VL4 voltage at L4 pin Vsink1,2 Input voltage at ISINK1, ISINK2 pins VOUT Internal overvoltage protection Maximum boost factor (Vout/Vin) Tmin_off Minimum off pulse width RDS(ON) N-channel MOSFET on-resistance TEST CONDITIONS MIN Isink1 = Isink2 = 20 mA, Vin = 2.8 V N-channel leakage current 35 37 9 10 0.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 SLVS950G – JULY 2009 – REVISED MAY 2013 www.ti.com ADC CONVERTER PARAMETER VIN TEST CONDITIONS MIN TYP MAX Input voltage range at AD_IN1 to AD_IN4 pin (channel 0 to channel 3) For full scale measurement 0 2.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 www.ti.com SLVS950G – JULY 2009 – REVISED MAY 2013 POWER PATH (continued) PARAMETER TDGL(DT) Power detected deglitch VIN(OVP) Input over voltage detection threshold TEST CONDITIONS MIN AC or USB voltage increasing TYP MAX 22.5 5.8 6 UNIT ms 6.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 SLVS950G – JULY 2009 – REVISED MAY 2013 www.ti.com BATTERY CHARGER PARAMETER TEST CONDITIONS MIN TYP MAX –1% 4.10 1% –1% 4.15 1% –1% 4.20 1% –1% 4.25 1% UNIT CHARGER SECTION Battery discharge current 2 Battery charger voltage Depending on setting in CHGCONFIG2 And internal EEPROM Default = 4.20V (except TPS650721) Default = 4.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 www.ti.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 SLVS950G – JULY 2009 – REVISED MAY 2013 www.ti.com PIN FUNCTIONS (continued) PIN I/O DESCRIPTION NAME NO. SDAT 27 AD_IN1 (TSX1) 43 I Analog input1 for A/D converter; TPS65070, TPS650701, TPS650702, TPS65073, TPS650731, TPS650732 only: Input 1 to the x-plate for the touch screen.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 www.ti.com SLVS950G – JULY 2009 – REVISED MAY 2013 PIN FUNCTIONS (continued) PIN NAME NO. I/O DESCRIPTION Iset2 (AD_IN7) 36 I Connect a resistor from this pin to GND to set the full scale current for Isink1 and Isink2 with Bit Current Level in register WLED_CTRL0 set to 0. Analog input7 for the A/D converter. Isink1 34 I Input to the current sink 1. Connect the cathode of the LEDs to this pin.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 SLVS950G – JULY 2009 – REVISED MAY 2013 www.ti.com Functional Block Diagram AC SYS AC switch 22 mF SYS USB USB switch AVDD6 Iset 4.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 www.ti.com SLVS950G – JULY 2009 – REVISED MAY 2013 PARAMETER MEASUREMENT INFORMATION The data sheet graphs were taken on the TPS6507x evaluation module (EVM). Please refer to the EVM user´s guide (SLVU291) for the setup information. TYPICAL CHARACTERISTICS Table of Graphs FIGURE Efficiency DCDC1 vs Load current / PWM mode VO = 3.3V; VI = 3.0V, 3.6V, 4.2V, 5V 1 Efficiency DCDC1 vs Load current / PFM mode VO = 3.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 SLVS950G – JULY 2009 – REVISED MAY 2013 www.ti.com EFFICIENCY DCDC1 vs LOAD CURRENT/PWM MODE EFFICIENCY DCDC1 vs LOAD CURRENT/PFM MODE 100 3.4V 80 60 5V 50 40 60 50 40 30 30 20 20 10 10 100 90 0.001 0.01 0.1 IO - Output Current - A 1 VO = 3.3 V, PWM Mode 25°C 0 0.0001 10 0.001 1 Figure 2. EFFICIENCY DCDC2 vs LOAD CURRENT/PWM MODE EFFICIENCY DCDC2 vs LOAD CURRENT/PFM MODE 10 100 VO = 2.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 www.ti.com SLVS950G – JULY 2009 – REVISED MAY 2013 EFFICIENCY DCDC2 vs LOAD CURRENT/PWM MODE EFFICIENCY DCDC2 vs LOAD CURRENT/PFM MODE 100 100 VO = 1.8 V, 90 PWM Mode 25°C 80 80 3V 60 4.2V 50 5V 40 20 10 10 0.01 0.1 IO - Output Current - A 1 0 0.0001 10 0.001 0.01 0.1 IO - Output Current - A 1 Figure 6. EFFICIENCY DCDC3 vs LOAD CURRENT/PWM MODE EFFICIENCY DCDC3 vs LOAD CURRENT/PFM MODE 70 VO = 1.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 SLVS950G – JULY 2009 – REVISED MAY 2013 www.ti.com EFFICIENCY DCDC3 vs LOAD CURRENT/PWM MODE EFFICIENCY DCDC3 vs LOAD CURRENT/PFM MODE 100 90 100 VO = 1 V, PWM Mode 25°C 90 80 3.6V 70 70 3.6V 60 50 4.2V Efficiency - % Efficiency - % 3V 80 3V 5V 40 40 20 20 10 10 0.01 0.1 IO - Output Current - A 1 10 5V 50 30 0.001 4.2V 60 30 0 0.0001 0 0.0001 0.001 0.01 0.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 www.ti.com SLVS950G – JULY 2009 – REVISED MAY 2013 LOAD TRANSIENT RESPONSE CONVERTER 3 VOUT DCDC3 (Offset: 1.2 V) LINE TRANSIENT RESPONSE CONVERTER 1 VOUT DCDC1 (Offset: 3.25 V) ILoad DCDC3 VIN DCDC1 (Offset: 3 V) VIN = 3.6 V - 5 V - 3.6V, Load = 0.6 A VIN DCDC3 = 3.6 V, Load = 150 mA - 1350 mA - 150 mA Figure 13. Figure 14.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 SLVS950G – JULY 2009 – REVISED MAY 2013 www.ti.com OUTPUT VOLTAGE RIPPLE AND INDUCTOR CURRENT CONVERTER 2 – PWM MODE OUTPUT VOLTAGE RIPPLE AND INDUCTOR CURRENT CONVERTER 2 – PFM MODE VOUT DCDC2 (Offset: 1.8 V) VOUT DCDC2 (Offset: 1.78 V) IL DCDC2 IL DCDC2 VIN = 3.6 V, Load = 200 mA PWM VIN = 3.6 V, Load = 15 mA PFM Figure 17. Figure 18.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 www.ti.com SLVS950G – JULY 2009 – REVISED MAY 2013 KSET vs RISET LINE TRANSIENT RESPONSE LDO1 1200 1150 VOUT LDO1 (Offset: 1.8 V) 1100 Kset Vbat = 5 V, VIN LDO1: 3.6 V - 5 V - 3.6 V, LOAD = 40 mA VIN LDO1 (Offset: 3 V) 1050 1000 950 900 0.1 10 Figure 21. RIset - kW Figure 22.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 SLVS950G – JULY 2009 – REVISED MAY 2013 www.ti.com DETAILED DESCRIPTION BATTERY CHARGER AND POWER PATH The TPS6507x integrate a Li-ion linear charger and system power path management targeted at space-limited portable applications. The TPS6507x power the system while simultaneously and independently charging the battery.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 www.ti.com SLVS950G – JULY 2009 – REVISED MAY 2013 POWER DOWN The charger remains in a power down mode when the input voltage at the AC or USB pin is below the undervoltage lockout threshold VUVLO. During the power down mode the host commands at the control pins are not interpreted. POWER-ON RESET The charger resets when the input voltage at the AC or USB pin enters the valid range between VUVLO and VOVLO.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 SLVS950G – JULY 2009 – REVISED MAY 2013 PRECHARGE www.ti.com CC FAST CHARGE CV TAPER DONE VBAT(REG) IO(CHG) Battery Current Battery Voltage VLOWV TERM CURRENT = 1 I(PRECHG) I(TERM) Figure 27. Battery Charge In the pre-charge phase, the battery is charged at a current of IPRECHG. The battery voltage starts rising. Once the battery voltage crosses the VLOWV threshold, the battery is charged at a current of ICHG.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 www.ti.com SLVS950G – JULY 2009 – REVISED MAY 2013 If the BAT pin voltage falls below VLOWV in the battery detection test, it indicates that the battery has been removed. The device then checks for battery insertion: it turns on FET Q2 and sources IPRECHG out of the BAT pin for duration tDET. If the voltage does not rise above VRCH, it indicates that a battery has been inserted, and a new charge cycle can begin.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 SLVS950G – JULY 2009 – REVISED MAY 2013 PRECHARGE www.ti.com THERMAL REGULATION CC FAST CHARGE CV TAPER DONE VO(REG) IO(CHG) Battery Voltage Battery Current V(LOWV) TERM CURRENT = 1 I(PRECHG) I(TERM) IC junction temperature, TJ TJ(REG) Figure 28. Thermal Loop Timer Fault: The following events generate a fault status: 1. If the battery voltage does not exceed VLOWV in time tPRECHG during pre-charging 2.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 www.ti.com SLVS950G – JULY 2009 – REVISED MAY 2013 Sensor type resistor value in parallel to the NTC 10K curve 2 75k 100k curve 1 360k BATTERY CHARGER STATE DIAGRAM Wait 1 ms after EN_REF_CHG=1 At any state, exit and force EN_CHG=0 && EN_SHRT=0 && DBATSINK=0. TEMP_ERROR=0. Also register should be enabled.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 SLVS950G – JULY 2009 – REVISED MAY 2013 www.ti.com During PWM operation the converter use a unique fast response voltage mode controller scheme with input voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output capacitors. At the beginning of each clock cycle initiated by the clock signal, the High Side MOSFET switch is turned on.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 www.ti.com SLVS950G – JULY 2009 – REVISED MAY 2013 POWER SAVE MODE The Power Save Mode is enabled by default. If the load current decreases, the converter will enter Power Save Mode operation automatically. During Power Save Mode the converter skips switching and operates with reduced frequency in PFM mode and with a minimum quiescent current to maintain high efficiency.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 SLVS950G – JULY 2009 – REVISED MAY 2013 www.ti.com 100% Duty Cycle Low Dropout Operation The device starts to enter 100% duty cycle Mode once the input voltage comes close the nominal output voltage. In order to maintain the output voltage, the High Side MOSFET switch is turned on 100% for one or more cycles. With further decreasing VIN the High Side MOSFET switch is turned on completely.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 www.ti.com SLVS950G – JULY 2009 – REVISED MAY 2013 ENABLE To start up each converter independently, the device has a separate enable pin for each of the DCDC converters. In order to enable any converter with its enable pins, the TPS6507x devices need to be in ON-state by pulling PB_IN=LOW or POWER_ON=HIGH. The sequencing option programmed needs to be DCDC_SQ[2..0] = 101.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 SLVS950G – JULY 2009 – REVISED MAY 2013 www.ti.com PB_IN (Push-button IN) This pin is the ON/OFF button for the PMU to leave OFF-state and enter ON-state by pulling this pin to GND. Entering ON-state will first ramp the output voltage of the power path (SYS), load the default register settings and start up the DCDC converters and LDOs with the sequencing defined.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 www.ti.com SLVS950G – JULY 2009 – REVISED MAY 2013 PB_OUT This pin is a status output. PB_OUT is used as the wake-up interrupt to an application processor based on the status of PB_IN. If PB_IN=LOW, PB_OUT = LOW (after 50ms debounce). If PB_IN=HIGH, PB_OUT= high impedance (HIGH).
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 SLVS950G – JULY 2009 – REVISED MAY 2013 www.ti.com internal current sink at pins Isink1 and Isink2. The maximum current through the current sinks is set with two external resistors connected from pins ISET1 and ISET2 to GND. ISET1 sets the maximum current when Bit CURRENT LEVEL in register WLED_CTRL2 is set to 1.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 www.ti.com SLVS950G – JULY 2009 – REVISED MAY 2013 X-Plate TSX1 TSX2 RX1 RX2 Rcontact TSY2 RY2 Y-Plate RY1 TSY1 Figure 34. Touch Screen The touch screen interface consists of a digital state machine, a voltage reference, and an analog switch matrix which is connected to the four wire resistive touch screen inputs (TSX1, TSX2, TSY1, TSY2) and an internal 10Bit ADC.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 SLVS950G – JULY 2009 – REVISED MAY 2013 www.ti.com Table 3.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 www.ti.com SLVS950G – JULY 2009 – REVISED MAY 2013 TSX1 I L/150 TSY1 IL NMOS R X1 RY1 TGATE RC TSREF TO ADC R X2 TGATE RY2 22 kW NMOS TSY2 TSX2 PRESSURE MEASUREMET Figure 36.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 SLVS950G – JULY 2009 – REVISED MAY 2013 www.ti.com I2C Interface Specification: Serial interface The serial interface is compatible with the standard and fast mode I2C specifications, allowing transfers at up to 400kHz. The interface adds flexibility to the power supply solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements and charger status to be monitored.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 www.ti.com SLVS950G – JULY 2009 – REVISED MAY 2013 SCLK ... SDAT A6 ... A5 A4 ... A0 R/W ACK 0 R7 R6 ... R5 R0 ACK 0 D7 D5 ... D6 D0 ACK 0 Slave Address Start ... 0 Register Address Data Stop NOTE: SLAVE=TPS6507x Figure 41. Serial I/f WRITE to TPS6507x SCLK ... SDAT A6 .. ... A0 R/W ACK 0 R7 .. ... R0 A6 .. ACK 0 ...
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 SLVS950G – JULY 2009 – REVISED MAY 2013 www.ti.com DATA t( BUF) th(STA) t(LOW) tr tf CLK t h(STA) t(HIGH) th(DATA) STO STA tsu(STA) tsu(STO) tsu(DATA) STA STO Figure 44.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 www.ti.com SLVS950G – JULY 2009 – REVISED MAY 2013 REGISTERS PPATH1.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 SLVS950G – JULY 2009 – REVISED MAY 2013 www.ti.com INT.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 www.ti.com SLVS950G – JULY 2009 – REVISED MAY 2013 CHGCONFIG0.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 SLVS950G – JULY 2009 – REVISED MAY 2013 www.ti.com CHGCONFIG1.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 www.ti.com SLVS950G – JULY 2009 – REVISED MAY 2013 CHGCONFIG2.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 SLVS950G – JULY 2009 – REVISED MAY 2013 www.ti.com CHGCONFIG3.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 www.ti.com SLVS950G – JULY 2009 – REVISED MAY 2013 ADCONFIG.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 SLVS950G – JULY 2009 – REVISED MAY 2013 www.ti.com TSCMODE. Register Address: 08h TSCMODE Bit name and function Default Set by signal Default value loaded by: Read/write B7 B6 B5 B4 B3 0 B2 TSC_M2 1 B1 TSC_M1 1 BO TSC_M0 1 0 0 0 0 R R R R R UVLO R/W UVLO R/W UVLO R/W Bit 3..
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 www.ti.com SLVS950G – JULY 2009 – REVISED MAY 2013 ADRESULT_2.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 SLVS950G – JULY 2009 – REVISED MAY 2013 www.ti.com Bit 2 PGOOD VDCDC3: 0 = indicates that the VDCDC3 converter output voltage is below its target regulation voltage or disabled 1 = indicates that the VDCDC3 converter output voltage is within its nominal range.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 www.ti.com SLVS950G – JULY 2009 – REVISED MAY 2013 PGOODMASK.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 SLVS950G – JULY 2009 – REVISED MAY 2013 www.ti.com CON_CTRL1.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 www.ti.com SLVS950G – JULY 2009 – REVISED MAY 2013 Bit 4..
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 SLVS950G – JULY 2009 – REVISED MAY 2013 www.ti.com CON_CTRL2.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 www.ti.com SLVS950G – JULY 2009 – REVISED MAY 2013 CON_CTRL3.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 SLVS950G – JULY 2009 – REVISED MAY 2013 www.ti.com DEFDCDC2_LOW.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 www.ti.com SLVS950G – JULY 2009 – REVISED MAY 2013 DEFDCDC3_HIGH.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 SLVS950G – JULY 2009 – REVISED MAY 2013 www.ti.com OUTPUT VOLTAGE [V] B5 B4 B3 B2 B1 B0 1.450 0 1 1 1 0 1 1.475 0 1 1 1 1 0 1.500 0 1 1 1 1 1 1.550 1 0 0 0 0 0 1.600 1 0 0 0 0 1 1.650 1 0 0 0 1 0 1.700 1 0 0 0 1 1 1.750 1 0 0 1 0 0 1.800 1 0 0 1 0 1 1.850 1 0 0 1 1 0 1.900 1 0 0 1 1 1 1.950 1 0 1 0 0 0 2.000 1 0 1 0 0 1 2.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 www.ti.com SLVS950G – JULY 2009 – REVISED MAY 2013 The DEFSLEW register defines the slew rate of the output voltage for DCDC2 and DCDC3 in case the voltage is changed during operation. In case Bit “LDO2 tracking“ in register DEFLDO2 is set, this is also valid for LDO2.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 SLVS950G – JULY 2009 – REVISED MAY 2013 www.ti.com LDO_CTRL1. Register Address: 16h LDO_CTRL1 B7 B6 Bit name and function LDO_SQ2 LDO_SQ1 Default for –70, -701 Default for , -702 Default for See Table 9 See Table 9 –73, –731, –732, Default for –72 Default for -721 Default value loaded by: UVLO UVLO Read/write R/W R/W Bit 7..
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 www.ti.com Bit 3..0 SLVS950G – JULY 2009 – REVISED MAY 2013 LDO1(3) to LDO1(0): The Bits define the default output voltage of LDO1 according to the table below: LDO1[3] LDO1[2] LDO1[1] LDO1[0] LDO1 OUTPUT VOLTAGE 0 0 0 0 1.0 V 0 0 0 1 1.1 V 0 0 1 0 1.2 V 0 0 1 1 1.25 V 0 1 0 0 1.3 V 0 1 0 1 1.35 V 0 1 1 0 1.4 V 0 1 1 1 1.5 V 1 0 0 0 1.6 V 1 0 0 1 1.8 V 1 0 1 0 2.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 SLVS950G – JULY 2009 – REVISED MAY 2013 www.ti.com WLED_CTRL1.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 www.ti.com SLVS950G – JULY 2009 – REVISED MAY 2013 APPLICATION INFORMATION STEP-DOWN CONVERTERS OUTPUT FILTER DESIGN (INDUCTOR AND OUTPUT CAPACITOR) Inductor Selection The step-down converters operate typically with 2.2μH output inductor. Larger or smaller inductor values can be used to optimize the performance of the device for specific operation conditions.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 SLVS950G – JULY 2009 – REVISED MAY 2013 www.ti.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 www.ti.com SLVS950G – JULY 2009 – REVISED MAY 2013 OUTPUT VOLTAGE CHANGE FOR LDO1 and LDO2 The output voltage of LDO1 and LDO2 is defined in registers LDO_CTRL1 for LDO1 and in register DEFLDO2 for LDO2. The output voltage can be changed in these registers after power-up. UNUSED LDOs In case both LDOS are unused, connect VINLDO1/2 to the SYS node.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 SLVS950G – JULY 2009 – REVISED MAY 2013 www.ti.com Connecting both strings in parallel is required because the wLED converter generates its output voltage dependant on the current in ISINK1 and ISINK2. If the current falls below the target, the output voltage is increased.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 www.ti.com SLVS950G – JULY 2009 – REVISED MAY 2013 117 mA = 285 m A 2 117 mA Imin = 227 m A = 169 mA 2 Imax = 227 mA + (17) Given the values above, an inductor with a current rating greater than 290mA is needed. Plenty of margin should be kept to the rating in the inductor vendors data sheets as the maximum current is typically specified at a inductance drop of 20% or even 30%.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 SLVS950G – JULY 2009 – REVISED MAY 2013 www.ti.com Input Capacitor Selection A small ceramic input capacitor of 10 μF is needed at the input of the boost converter. If the inductor is directly connected to the SYS output of TPS6507x, the capacitor can be shared. In this case the capacitance needs to be 22μF or above. Only X5R or X7R ceramic capacitors should be used.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 www.ti.com SLVS950G – JULY 2009 – REVISED MAY 2013 Resistor RT2 in parallel to the NTC is used to linearize the resistance change with temperature of the NTC. As the NTC has a high resistance at low temperature, the resulting resistance of NTC in parallel with RT2 is lower especially for low temperatures where the NTC has a high resistance, so RT2 in parallel has a significant impact.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 SLVS950G – JULY 2009 – REVISED MAY 2013 www.ti.com 1.8 1.7 1.6 1.5 VTS (T) 1.4 1.3 1.2 1.1 1 0.9 0.8 -5 0 5 10 15 20 25 30 35 Temperature - (T) 40 45 50 Figure 48. Resulting TS Voltage As Figure 47 shows, the result is an extended charging temperature range at lower temperatures. The upper temperature limit is shifted to lower values as well resulting in a V(HOT) temperature of slightly less than 45°C.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 www.ti.com SLVS950G – JULY 2009 – REVISED MAY 2013 Table 9. Sequencing Settings (continued) DEDICATED FOR DCDC_SQ[2..0] LDO_SQ[2..0] COMMENT TPS650701 110 100 DCDC1 = 1.2V automatically enabled (1st) DCDC2 = 1.8V or 3.3V automatically enabled (2nd) DCDC3 = 1.8V or 3.3V automatically enabled (3rd) LDO1 = 1.8V (off per default) LDO2 = 2.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 SLVS950G – JULY 2009 – REVISED MAY 2013 www.ti.com Starting TPS6507x TPS6507x was developed for battery powered applications with focus on lowest shutdown and quiescent current. In order to achieve this, in shutdown all mayor blocks and the system voltage at the output of the power path (SYS) are turned off and only the input that turns on TPS6507x, pin PB_IN, is supervised.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 www.ti.com SLVS950G – JULY 2009 – REVISED MAY 2013 APPLICATION CIRCUITS TPS65070 AC BAT BAT 1 mF charger / power path USB 1 mF 10 mF NTC TS Vin DEFDCDC2 L1 SYS DCDC1 600 mA DEFDCDC3 AVDD6 EN 10 mF 2.2 mH USB0_VDDA33 (3.3 V) USB1_VDDA33 (3.3 V) VDCDC1 TPS3805H33 10 mF VDD SYS EN_DCDC1 Sense Reset VINLDO1/2 SYS RTC_CVDD (1.2V) VINDCDC3 BYPASS sets default voltage of DCDC3 to 1.0 V or 1.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 SLVS950G – JULY 2009 – REVISED MAY 2013 www.ti.com PB_IN can be released HIGH any time after POWR_ON = HIGH PB_OUT level not defined as voltage at pull-up has not ramped at that time 50ms debounce 50 ms debounce SYS POWER_ON asserted HIGH by the application processor any time while PB_IN = LOW to keep the system alive external LDO (RTC_CVDD) 1.2 V VDCDC3 (CVDD) 1.2 V 170 ms 250 ms VLDO2 (SATA_VDD) 1.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 www.ti.com SLVS950G – JULY 2009 – REVISED MAY 2013 AC BAT TPS65072 BAT 1 mF 10 mF USB charger / power path TS LiIon NTC SYS 1 mF VINDCDC1/2 ISET 2 x 10 mF VINDCDC3 set charge current BYPASS (2.25 V reference output) DEFDCDC2 ALTAS IV L1 DEFDCDC3 DCDC1 600 mA VINLDO1/2 SYS 1 mF 2.2 mH VCC_3V3 (VDDIO) VDCDC1 10 mF L2 2.2 mH DCDC2 600 mA INT_LDO VCC_1V8 (VDDIO_MEM) VDCDC2 2.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 SLVS950G – JULY 2009 – REVISED MAY 2013 www.ti.com PB_IN can be released HIGH any time after POWR_ON=HIGH 15s PB_OUT level not defined as voltage at pull-up has not ramped at that time 50ms debounce 50ms debounce SYS POWER_ON asserted HIGH by the application processor any time while /PB_IN=LOW to keep the system alive EN_EXTLDO (VDD_RTCIO) VLDO2 (VDD_PRE) VDCDC1 (VCC_3V3) 1ms 0.95 x Vout,nominal 1ms 0.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 www.ti.com SLVS950G – JULY 2009 – REVISED MAY 2013 Prima SLEEP Mode and DEEP SLEEP Mode Support TPS6507x contains a sequencing option for the Sirf Prima processor. The sequencing option defines how the voltages are ramped at initial power-up and shutdown as well as the timing for entering power save mode for the processor (SLEEP mode). The Prima processor supports SLEEP mode and also DEEP SLEEP mode.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 SLVS950G – JULY 2009 – REVISED MAY 2013 www.ti.com PB_IN can be released HIGH any time after POWR_ON=HIGH 15s PB_OUT level not defined as voltage at pull-up has not ramped at that time 50ms debounce 50ms debounce SYS POWER_ON asserted HIGH by the application processor any time while /PB_IN=LOW to keep the system alive EN_EXTLDO (VDD_RTCIO) VLDO2 (VDD_PRE) 1ms 0.95 x Vout,nominal 1ms VDCDC1 (VCC_3V3) 0.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 www.ti.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 SLVS950G – JULY 2009 – REVISED MAY 2013 www.ti.com TPS65073 AC 1uF BAT USB charger / power path 1uF LiIon VDDS_MMC1(1.8V / 3.0V) TS SYS NTC ISET VINDCDC1/2 set charge current VINDCDC3 2 x 10uF 1.5uH L1 DEFDCDC2 DCDC1 600mA DEFDCDC3 SYS OMAP35xx TPS79901 Vin SYS LDO 10uF EN BAT VINLDO1/2 VDCDC1 L2 1uF DCDC2 600mA 1.5uH VDDCORE (1.2V) VDCDC2 /PB_IN VDDS_WKUP_BG (1.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 www.ti.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 SLVS950G – JULY 2009 – REVISED MAY 2013 www.ti.com TPS650731 BAT AC BAT 10 mF 1 mF USB charger / power path TS NTC SYS 1 mF VINDCDC1/2 ISET VINDCDC3 set charge current L1 DCDC1 600mA DEFDCDC2 OMAP35xx 2 x 10 mF 2.2 mH VDCDC1 VDDS_WKUP_BG (1.8 V) VDDS_MEM; VDDS 10 mF VDDS_SRAM DEFDCDC3 L2 SYS LiIon DCDC2 600mA VINLDO1/2 2.2 mH VDDCORE (1.2 V) VDCDC2 10 mF 2.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 www.ti.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 SLVS950G – JULY 2009 – REVISED MAY 2013 www.ti.com TPS650732 BAT AC BAT 1uF USB charger / power path 1uF SYS VINDCDC3 VDDS1-5 (1.8V) VDCDC1 DEFDCDC3 VINLDO1/2 10uF 2.2uH L2 DCDC2 600mA AM3505 2 x 10uF 2.2uH L1 DCDC1 600mA DEFDCDC2 SYS NTC VINDCDC1/2 ISET set charge current SYS 10uF LiIon TS VDDSHV (3.3V) VDCDC2 10uF 2.2uH 1uF L3 DCDC3 1500mA /PB_IN VDD_CORE (1.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 www.ti.com SLVS950G – JULY 2009 – REVISED MAY 2013 /PB_IN can be released HIGH any time after POWR_ON=HIGH PB_OUT level not defined as voltage at pull-up has not ramped at that time 50ms debounce 50ms debounce SYS POWER_ON asserted HIGH by the application processor any time while /PB_IN=LOW to keep the system alive VDCDC1 (VDDS1-5 1.8V ) 170us 250us VDCDC2 (VDDSHV) 3.3V 170us 250us VLDO_ext1 (VDDS_SRAM) 1.
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 SLVS950G – JULY 2009 – REVISED MAY 2013 www.ti.com REVISION HISTORY Changes from Revision A (August 2009) to Revision B Page • Changed title from ".....Navigation Systems" to ".......Battery Powered Systems" ................................................................ 1 • Changed status of TPS65072RSL device to Production Data .........................................................................................
TPS65070, TPS65072, TPS65073 TPS650731, TPS650732, TPS650701, TPS650702, TPS650721 www.ti.com SLVS950G – JULY 2009 – REVISED MAY 2013 Changes from Revision F (July 2012) to Revision G • Page Changed the PPATH1. Register Address: 01h section table. Default row From: xx00011 To: xx00110 .........................
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.com (3) 11-Apr-2013 MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS65070RSLR VQFN RSL 48 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2 TPS65070RSLR VQFN RSL 48 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2 TPS65070RSLT VQFN RSL 48 250 180.0 16.4 6.3 6.3 1.5 12.0 16.
PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS65070RSLR VQFN RSL 48 2500 367.0 367.0 38.0 TPS65070RSLR VQFN RSL 48 2500 367.0 367.0 38.0 TPS65070RSLT VQFN RSL 48 250 210.0 185.0 35.0 TPS65070RSLT VQFN RSL 48 250 210.0 185.0 35.0 TPS65072RSLR VQFN RSL 48 2500 367.0 367.0 38.0 TPS65072RSLT VQFN RSL 48 250 210.0 185.0 35.
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