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FEATURES APPLICATIONS

DESCRIPTION

TYPICAL APPLICATION

VIN

DRVN

FBN

REF

COMP

DLY1

DLY2

FDLY

SW SW

SUP

DRVP

CPI

FBP

GND

PGND

VCOM

TPS65150

ADJ

CTRL

VGH

Vin

5 V

500 k

1 nF

500 k

3.9 H

22 F

0.33 FD2

620 k

0.33 F

150 k

220 nF

VGH

Control Signal

2.2 nF

C10

22 pF

C11

10 nF

C12

10 nF

C13

100 nF

CPI

C16

0.33 F

1 F

0.33 F

VGH

23 V/20 mA

COM

Output

C14

1 F

C15

22 pF

820 k

75 k

22 F

56 k

1 M

CPI

13.5 V/450 mA

VGL

−5 V/20 mA

TPS65150

SLVS576 – SEPTEMBER 2005

Low Input Voltage, Compact LCD Bias IC With VCOM Buffer

• TFT LCD Displays for Notebooks

• 1.8-V to 6-V Input Voltage Range

• TFT LCD Display for Monitor

• Integrated VCOM Buffer

• Car Navigation Display

• High Voltage Switch to Isolate VGH

• Gate Voltage Shaping of VGH

• 2-A Internal MOSFET Switch

The TPS65150 offers a very compact and small

• Main Output Vs up to 15 V With <1% Output

power supply solution that provides all three voltages

Voltage Accuracy

required by thin film transistor (TFT) LCD displays.

• Virtual Synchronous Converter Technology

With an input voltage range of 1.8 V to 6.0 V the

device is ideal for notebooks powered by a 2.5-V or

• Negative Regulated Charge Pump Driver VGL

3.3-V input rail or monitor applications with a 5-V

• Positive Regulated Charge Pump Driver VGH

input voltage rail. Additionally the TPS65150 provides

• Adjustable Power On Sequencing

an integrated high current buffer to provide the

VCOM voltage for the TFT backplane.

• Adjustable Fault Detection Timing

• Gate Drive Signal for external isolation

Two regulated adjustable charge pump driver provide

MOSFET

the positive VGH and negative VGL bias voltages for

the TFT. The device incorporates adjustable power

• Thermal Shutdown

on sequencing for VGL as well as for VGH. This

• Available in TSSOP-24 Package

avoids any additional external components to

• Available in QFN-24 Package

implement application specific sequencing. The

device has an integrated high voltage switch to

isolate VGH.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPad is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (33 pages)

PAGE 1
TPS65150 www.ti.com SLVS576 – SEPTEMBER 2005 Low Input Voltage, Compact LCD Bias IC With VCOM Buffer FEATURES APPLICATIONS • • • • • • • • • • • • • • • • • • 1.
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TPS65150 www.ti.com SLVS576 – SEPTEMBER 2005 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) The same internal circuit can also be used to provide a gate shaping signal of VGH for the LCD panel controlled by the signal applied to the CTRL input.
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TPS65150 www.ti.com SLVS576 – SEPTEMBER 2005 RECOMMENDED OPERATING CONDITIONS (continued) MIN TJ Operating junction temperature TYP –40 MAX UNIT 125 °C MAX UNIT ELECTRICAL CHARACTERISTICS VIN = 3.3 V, Vs = 10 V, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP SUPPLY CURRENT VIN Input voltage range 1.
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TPS65150 www.ti.com SLVS576 – SEPTEMBER 2005 ELECTRICAL CHARACTERISTICS (continued) VIN = 3.3 V, Vs = 10 V, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 1.187 1.214 1.238 V 10 100 nA VFB Feedback regulation voltage CTRL = GND, VGH = open IFB Feedback input bias current CTRL = GND, VGH = open RDS(on) Q3 P-Channel switch RDSon IOUT = 20 mA 1.
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TPS65150 www.ti.
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TPS65150 www.ti.com SLVS576 – SEPTEMBER 2005 TERMINAL FUNCTIONS (continued) TERMINAL NAME IN PGND NO. I/O QFN TSSOP 14 11 I DESCRIPTION Input of the Vcom buffer. If this pin is connected to GND, the Vcom buffer is disabled. 10, 11 7, 8 REF 23 20 O Power ground Internal reference output typically 1.213 V SUP 12 9 I/O Supply pin of the positive, negative charge pump and Boost Converter Gate Drive Circuit.
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TPS65150 www.ti.com SLVS576 – SEPTEMBER 2005 TYPICAL CHARACTERISTICS TABLE OF GRAPHS FIGURES Main Boost Converter η Efficiency vs Load current Vs=10 V 1 η Efficiency vs Load current Vs=13.
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TPS65150 www.ti.com SLVS576 – SEPTEMBER 2005 EFFICIENCY vs LOAD CURRENT SWITCHING FREQUENCY vs TEMPERATURE 1.155 100 VS = 13.5 V VS = 15 V, VGH = VGL = No Load, Switching Efficiency − % f − Frequency − MHz VIN = 5 V VIN = 3.3 V 70 VIN = 3.6 V 1.150 90 80 VIN = 7 V VIN = 2.5 V 60 VIN = 1.8 V 1.145 1.140 1.135 1.130 50 40 0 1.125 0.05 0.1 0.15 0.2 0.25 0.3 IO − Load Current − A 0.35 0.4 1.120 −40 −20 0 20 40 60 Figure 3. Figure 4.
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TPS65150 www.ti.com SLVS576 – SEPTEMBER 2005 LOAD TRANSIENT RESPONSE SOFT START BOOST CONVERTER VIN 5 V/div VO1 100 mV/div VIN = 3.3 V VS = 10 V, CO = 22 F VS 5 V/div IO 30 mA to 330 mA VIN = 5 V VO = 13.5 V Iout = 200 mA IIN 500 mA/div 100 s/div 2.5 ms/div Figure 7. Figure 8. POWER-ON SEQUENCING POWER-ON SEQUENCING WITH EXTERNAL ISOLATION MOSFET AT VS VS 5 V/div VS 5 V/div VGH 10 V/div VGH 10 V/div VGL 5 V/div VGL 5 V/div VCOM 2 V/div VIN = 5 V VO = 13.
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TPS65150 www.ti.com SLVS576 – SEPTEMBER 2005 GATE VOLTAGE SHAPING VGH ADJUSTABLE FAULT DETECTION CTRL 2 V/div Fault Delay Time VS 5 V/div VGH 10 V/div VGH 10 V/div Fault (Heavy Load at VS) VGL 5 V/div CADJ = 68 pF VGH = No Load CFDLY = 100 nF 10 ms/div 2.5 s/div Figure 11. Figure 12. VGL– GATE VOLTAGE LOW vs LOAD CURRENT VGH– GATE VOLTAGE HIGH vs LOAD CURRENT –X2 STAGE −4.86 VS = 10 V VGL = –5 V 24.50 VGH − Gate Voltage High − V VGL − Gate Voltage Low − V −4.88 25 TA = 85 C −4.90 −4.
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TPS65150 www.ti.com SLVS576 – SEPTEMBER 2005 VGH– GATE VOLTAGE HIGH vs LOAD CURRENT – X3 STAGE VCOM BUFFER dVOUT vs LOAD CURRENT 25 0.08 0.06 VS = 10 V VVCOM = 5 V 24 0.04 23.50 VS = 10 V VGH = 24 V x3 Stage 23 VCOM Buffer − V VGH − Gate Voltage High − V 24.50 TA = −40 C 22.50 TA = 25 C 22 21.50 TA = 85 C 0.02 0 −0.02 −0.04 21 −0.06 22.50 20 0 0.02 0.04 0.06 IO − Load Current − A Figure 15. 0.08 0.1 −0.08 −150 −100 −50 0 50 IO − Load Current − A 100 150 Figure 16.
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TPS65150 www.ti.com SLVS576 – SEPTEMBER 2005 FUNCTIONAL BLOCK DIAGRAM VIN SW SW Q2 Main boost converter Current Limit Bias Vref=1.213V Logic Control Block Shutdown Latch Timer Thermal Shutdown FDLY GND DL1 SUP and Soft Start 1.2 MHz Oscillator SUP Control Logic Gate Drive circuit DL2 Q1 COMP PGND GM Amplifier Sawtooth Generator FB Comparator PGND SUP VFB SUP (Vout) 1.154V Positive Charge Pump SUP I DRVP GM Amplifier Low Gain VFB 1.154 Current Control Softstart Vref 1.
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TPS65150 www.ti.com SLVS576 – SEPTEMBER 2005 DETAILED DESCRIPTION Main Boost Converter The main boost converter operates with pulse width modulation (PWM) and a fixed switching frequency of 1.2 MHz. The converter uses an unique fast response, voltage mode controller scheme with input voltage feedforward. This achieves excellent line and load regulation (0.16%/A load regulation typical) and allows the use of small external components.
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TPS65150 www.ti.com SLVS576 – SEPTEMBER 2005 DETAILED DESCRIPTION (continued) SUP = VIN for VS > = 15 V SUP = VS for VS < = 15 V Vs I DRVP DRVP Current Control Soft Start Cfly VGH 23 V/50 mA Q3 R5 C13 0.47 F FBP R6 Figure 17. Extract of the Positive Charge Pump Driver If higher output voltages are required another charge pump stage can be added to the output, as shown in Figure 21 at the end of the data sheet. To minimize quiescent current a high impedance feedback divider should be used.
PAGE 15
TPS65150 www.ti.com SLVS576 – SEPTEMBER 2005 DETAILED DESCRIPTION (continued) Power-on Sequencing, DLY1, DLY2 As soon as the input voltage is applied, and rises above the undervoltage lockout (UVLO), the device starts with the main boost converter, Vs, coming up first. Then the negative voltage, VGL, comes up, set by the delay time DLY1; and then the positive charge pump, VGH, set by the delay time DLY2. Finally, the VCOM buffer starts up.
PAGE 16
TPS65150 www.ti.com SLVS576 – SEPTEMBER 2005 DETAILED DESCRIPTION (continued) Q5 CPI VGH Q7 Control CTRL, UVOL, FPB = High Q5 = Q7 = ON, Q6 = OFF CTRL = Low Q5 = Q7 = OFF, Q6 = Turns ON Q6 FBP ADJ UVLO I ADJ Vref 1.213 V Cadj 47 pF CTRL Figure 19. Implementation of the Gate voltage shaping Control Signal (Pin CTRL) VCPI VGH V VL toff ton Iadj x toff Cadj V Figure 20. Timing Diagram of the Gate voltage shaping The control signal applied to CTRL sets the timing of VGH.
PAGE 17
TPS65150 www.ti.com SLVS576 – SEPTEMBER 2005 DETAILED DESCRIPTION (continued) Thermal Shutdown A thermal shutdown is implemented to prevent damage because of excessive heat and power dissipation. Typically, the thermal shutdown threshold is 155°C . When this threshold is reached, the device enters shutdown. The device can be enabled again by cycling the input voltage to GND. Vcom Buffer The VCOM Buffer is a transconductance amplifier designed to drive capacitive loads.
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TPS65150 www.ti.com SLVS576 – SEPTEMBER 2005 DETAILED DESCRIPTION (continued) Table 1. Inductor Selection INDUCTOR VALUE COMPONENT SUPPLIER DIMENSIONS IN mm Isat – DC Resistance 4.7 µH Coilcraft DO1813P-472HC 8,89 × 6,1 × 5,0 2.6 A – 54 mΩ 4.2 µH Sumida CDRH5D28 4R2 5,7 × 5,7 × 3 2.2 A – 23 mΩ 4.7 µH Sumida CDC5D23 4R7 6 × 6 × 2,5 1.6 A – 48 mΩ 4.2 µH Sumida CDRH6D12 4R2 6,5 × 6,5 × 1,5 1.8 A – 60 mΩ 3.9 µH Sumida CDRH6D28 3R9 7,0 × 7,0 × 3,0 2.6A – 20 mΩ 3.
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TPS65150 www.ti.com SLVS576 – SEPTEMBER 2005 Setting the Output Voltage The output voltage is set by the external resistor divider and is calculated as: V out 1.146 V 1 R1 R2 (10) To minimize quiescent current high impedance feedback resistors should be used. The upper feedback resistor R1 should not be larger than 1MΩ. Across the upper resistor, a bypass capacitor is required to speed up the circuit during load transients.
PAGE 20
TPS65150 www.ti.com SLVS576 – SEPTEMBER 2005 10. The power pad of the TSSOP package needs to be soldered to the PCB for imroved thermal performance. 11. The thermal pad of the QFN package needs to be soldered to the PCB for reliability and thermal performance reasons.
PAGE 21
TPS65150 www.ti.com SLVS576 – SEPTEMBER 2005 APPLICATION INFORMATION R8 500 k C6 R7 500 k 1 nF IN VIN DRVN D3 R3 620 k REF DRVP GND R4 150 k PGND FBP CPI PGND VGH CTRL VCOM TPS65150 COMP VGH Contol Signal C9 470 pF R9 33 k DLY1 C8 220 nF FB ADJ C3 0.33 F SW SW SUP FBN C10 C11 22 pF 10 nF 10 nF R2 430 k C2 22 F R2 56 k C16 D5 D6 D7 CPI CPI 0.33 F C17 C18 0.33 F 0.33 F SW C4 0.
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TPS65150 www.ti.com SLVS576 – SEPTEMBER 2005 APPLICATION INFORMATION (continued) R8 500 k C6 R7 500 k 1 nF D3 R3 620 k FB REF DRVP VGH CPI PGND VGH CTRL VCOM COMP GD C16 D5 CPI 0.33 F C4 0.33 F CPI C11 C12 22 pF 10 nF 10 nF R5 1 M R6 56 k VGH 23 V/20 mA VCOM Output C13 C10 C2 22 F R2 75 k FBP PGND C9 2.2 nF Contol Signal TPS65150 ADJ C8 220 nF SUP FBN GND R4 150 k SW R1 820 k C15 22 pF C14 1 F FDLY 0.33 F SW DLY1 C3 0.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Dec-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) TPS65150PWPR HTSSOP PWP 24 2000 330.0 16.4 TPS65150RGER VQFN RGE 24 3000 330.0 TPS65150RGER VQFN RGE 24 3000 330.0 6.95 8.3 1.6 8.0 16.0 Q1 12.4 4.35 4.35 1.1 8.0 12.0 Q2 12.4 4.25 4.25 1.15 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Dec-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS65150PWPR HTSSOP PWP 24 2000 367.0 367.0 38.0 TPS65150RGER VQFN RGE 24 3000 338.0 355.0 50.0 TPS65150RGER VQFN RGE 24 3000 367.0 367.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.