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PRODUCTPREVIEW

TPS65186

www.ti.com

SLVSB04 –JULY 2011

PMIC FOR E Ink

Vizplex™ ENABLED ELECTRONIC PAPER DISPLAY

Check for Samples: TPS65186

• Flexible Power-Up and Power Down

FEATURES

Sequencing

2345

• Single Chip Power Management Solution for

• Integrated 10-Ω, 3.3-V Power Switch for

E Ink

Vizplex™ Electronic Paper Displays

Disabling System Power Rail to E-Ink Panel

• Generates Positive and Negative Gate and

• Thermistor Monitoring

Source Driver Voltages and Back-Plane Bias

– –10°C to 85°C Temperature Range

from a Single, Low-Voltage Input Supply

– ±1°C Accuracy from 0°C to 50°C

• Supports 9.7 Inch and Larger Panel Size

• I

C Serial Interface

• 3-V to 6-V Input Voltage Range

– Slave Address 0x48h

• Boost Converter for Positive Rail Base

• Package Options:

• Inverting Buck-Boost Converter for Negative

Rail Base

– 48-Pin, 0.5 mm Pitch,

7 mm x 7 mm x 0.9 mm (QFN) RGZ

• Two Adjustable LDOs for Source Driver

Supply

APPLICATIONS

– LDO1: 15 V, 120 mA (VPOS)

– LDO2: –15 V, 120 mA (VNEG)

• Power Supply for Active Matrix E Ink

Vizplex™ Panels

• Accurate Output Voltage Tracking

• EPD Power Supply

– VPOS - VNEG = ±50 mV

• E-Book Readers

• Two Charge Pumps for Gate Driver Supply

• EPSON

S1D13522 (ISIS) Timing Controller

– CP1: 22 V, 10 mA (VDDH)

• EPSON

S1D13521 (Broadsheet) Timing

– CP2: –20 V, 12 mA, (VEE)

Controller

• Adjustable VCOM Driver for Accurate

• Application Processors With Integrated or

Panel-Backplane Biasing

Software Timing Controller ( OMAP™)

– User Programmable Default

– 0 V to -5.11 V

– ± 1.5% accuracy (±10 mV)

– 9-Bit Control (10-mV Nominal Step Size)

DESCRIPTION

The TPS65186 is a single-chip power supply designed to for E Ink

Vizplex™ displays used in portable e-reader

applications and supports panel sizes up to 9.7 inches and greater. Two high efficiency DC/DC boost converters

generate ±16-V rails which are boosted to 22 V and –20 V by two change pumps to provide the gate driver

supply for the Vizplex™ panel. Two tracking LDOs create the ±15-V source driver supplies which support up to

120-mA of output current. All rails are adjustable through the I

C interface to accommodate specific panel

requirements.

Accurate back-plane biasing is provided by a linear amplifier that can be adjusted from 0 V to -5.11 V with 9-bit

control through the serial interface and can source or sink current depending on panel condition. The TPS65186

supports automatic panel kickback voltage measurement which eliminates the need of manual VCOM calibration

in the production line. The measurement result can be stored in non-volatile memory to become the new VCOM

power-up default value.

TPS65186 is available in a 48-pin 7x7 mm

QFN with 0.5-mm pitch.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2OMAP is a trademark of Texas Instruments.

3Vizplex is a trademark of E Ink Corporation.

4E Ink is a registered trademark of E Ink Corporation.

5EPSON is a registered trademark of Seiko Epson Corporation.

PRODUCT PREVIEW information concerns products in the

formative or design phase of development. Characteristic data and

other specifications are design goals. Texas Instruments reserves

the right to change or discontinue these products without notice.

Summary of content (47 pages)

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TPS65186 SLVSB04 – JULY 2011 www.ti.com ® PMIC FOR E Ink Vizplex™ ENABLED ELECTRONIC PAPER DISPLAY Check for Samples: TPS65186 • Single Chip Power Management Solution for E Ink® Vizplex™ Electronic Paper Displays • Generates Positive and Negative Gate and Source Driver Voltages and Back-Plane Bias from a Single, Low-Voltage Input Supply • Supports 9.
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TPS65186 SLVSB04 – JULY 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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TPS65186 SLVSB04 – JULY 2011 www.ti.com ORDERING INFORMATION (1) (1) (2) TA PACKAGE (2) ORDERABLE PART NUMBER TOP-SIDE MARKING -10°C to 85°C RGZ TPS65186RGZR TPS65186 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
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TPS65186 SLVSB04 – JULY 2011 www.ti.com TERMINAL NAME PRODUCT PREVIEW 4 NO. N/C 9 VIN 10 N/C 11 VCOM_CTRL 12 N/C 13 VCOM 14 I/O DESCRIPTION Not internally connected I Input power supply to general circuitry Not internally connected I VCOM enable. Pull this pin high to enable the VCOM amplifier. When pin is pulled low and VN is enabled, VCOM discharge is enabled.
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TPS65186 SLVSB04 – JULY 2011 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) (2) (2) VALUE UNIT –0.3 to 7 V Ground pins to system ground –0.3 to 0.3 V Voltage range at SDA, SCL, WAKEUP, PWRUP, VCOM_CTRL, VDDH_FB, VEE_FB, PWR_GOOD, nINT –0.3 to 3.6 V Voltage on VB, VB_SW, VPOS_IN, VDDH_IN –0.3 to 20 V Voltage on VN, VEE_IN, VCOM_PWR, VNEG_IN –20 to 0.3 V Voltage from VIN_P to VN_SW –0.
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TPS65186 SLVSB04 – JULY 2011 www.ti.com RECOMMENDED EXTERNAL COMPONENTS PART NUMBER VALUE SIZE MANUFACTURER LQH44PN4R7MP0 4.7 µH 4 mm x 4 mm x 1.65 mm Murata NR4018T4R7M 4.7 µH 4 mm x 4 mm x 1.8 mm Taiyo Yuden VLS252015ET-2R2M 2.2 µH 2 mm x 2.5 mm x 1.5 mm TDK NR4012T2R2M 2.2 µH 4 mm x 4 mm x 1.2 mm Taiyo Yuden GRM21BC81E475KA12L 4.7 µF, 25 V, X6S 0805 Murata GRM32ER71H475KA88L 4.
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TPS65186 SLVSB04 – JULY 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VIN = 3.7 V, TA = –10°C to 85ºC, Typical values are at TA = 25ºC (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 3 3.
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TPS65186 SLVSB04 – JULY 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VIN = 3.7 V, TA = –10°C to 85ºC, Typical values are at TA = 25ºC (unless otherwise noted) PARAMETER TEST CONDITIONS MIN VSET = ±15 V, ILOAD = ±20 mA, 0°C to 60°C -50 TYP MAX UNIT LD01 (POS) AND LDO2 (VNEG) TRACKING VDIFF Difference between VPOS and VNEG 50 mV VCOM DRIVER IVCOM Drive current Allowed operating range Accuracy VCOM 15 -5.5 1 VCOM[8:0] = 0x07Dh (-1.25 V), VIN = 3.4 V to 4.2 V, no load -0.8 0.
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TPS65186 SLVSB04 – JULY 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VIN = 3.7 V, TA = –10°C to 85ºC, Typical values are at TA = 25ºC (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX VIN3P3 = 3.3 V, ID = 10 mA Over full temperature range 10.5 TBD VIN3P3 = 2.7 V, ID = 10 mA Over full temperature range 12.
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TPS65186 SLVSB04 – JULY 2011 www.ti.com TYPICAL CHARACTERISTICS PRODUCT PREVIEW 10 DEFAULT POWER-UP SEQUENCE DEFAULT POWER-DOWN SEQUENCE (1-kΩ External Discharge Resistor on Each Rail) Figure 1. Figure 2. INRUSH CURRENT @ VIN = 3.7 V, CIN = 100 µF INRUSH CURRENT @ VIN = 5 V, CIN = 100 µF Figure 3. Figure 4.
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TPS65186 SLVSB04 – JULY 2011 www.ti.com SWITCHING WAVE FORMS, VB VIN = 3.7 V, RLOAD, VPOS = 330 Ω, RLOAD, VNEG = 330 Ω, No Load on VDDH, VEE Figure 7. Figure 8. SWITCHING WAVE FORMS, VN VIN = 5 V, RLOAD, VPOS = 330 Ω, RLOAD, VNEG = 330 Ω, No Load on VDDH, VEE SWITCHING WAVE FORMS, VB VIN = 5 V, RLOAD, VPOS = 330 Ω, RLOAD, VNEG = 330 Ω, No Load on VDDH, VEE Figure 9. Figure 10. VB DCDC EFFICIENCY, T = 25°C 100 100 90 90 80 80 70 70 60 V IN= 3.
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TPS65186 SLVSB04 – JULY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) VEE CHARGE PUMP EFFICIENCY, T = 25°C VDDH CHARGE PUMP EFFICIENCY, T = 25°C 100 100 90 90 VIN=5V VIN=5V 80 80 VIN=3.5V VIN=3. 5 70 Efficiency [%] Efficiency [%] 70 60 50 40 60 50 40 30 30 20 20 10 10 0 0 0 2 4 6 8 10 12 0 2 6 8 10 12 Output Current [mA] Figure 13. Figure 14. 3p3V SWITCH IMPEDANCE VIN = 3.7 V, ILOAD, V3p3 = 10 mA SOURCE DRIVER SUPPLY TRACKING VIN = 3.
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TPS65186 SLVSB04 – JULY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) KICKBACK VOLTAGE MEASUREMENT TIMING VIN = 3.7 V; AVG[1:0] = 00 (Single Measurement) Time from ACQ Bit Set to ACQC Interrupt Received KICKBACK VOLTAGE MEASUREMENT ERROR VIN = 3.7 V 2 Measurementerror [LSB] 1.5 1 0.5 0 -0.5 -1 -1.5 -2 0 640 12 80 192 0 2560 3200 3840 44 80 512 0 F o rce d Kick ba c k Vo lta g e [m V] Figure 19. Figure 20. PRODUCT PREVIEW KICKBACK VOLTAGE MEASUREMENT TIMING VIN = 3.
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TPS65186 SLVSB04 – JULY 2011 www.ti.com MODES OF OPERATION The TPS65186 has three modes of operation, SLEEP, STANDBY, and ACTIVE. SLEEP mode is the lowest-power mode in which all internal circuitry is turned off. In STANDBY, all power rails are shut down but the device is ready to accept commands through the I2C interface. In ACTIVE mode one or more power rails are enabled. SLEEP This is the lowest power mode of operation.
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TPS65186 SLVSB04 – JULY 2011 www.ti.com POWER DOWN All rails = OFF V3P3 switch = OFF I2C = NO Registers à default SLEEP WAKEUP = high & PWRUP= low WAKEUP = low WAKEUP = low All rails I2C STANDBY WAKEUP = high & (STANDBY bit = 1|| PWRUP(?) || FAULT ) = OFF = YES PRODUCT PREVIEW WAKEUP = high & PWRUP = high Battery removed WAKEUP = high & (ACTIVE bit = 1 || PWRUP( ) ) ? ACTIVE NOTES: ||, & ( ), (?) UVLO TSD UV = logic OR, logic AND. = rising edge, falling edge.
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TPS65186 SLVSB04 – JULY 2011 www.ti.com WAKE-UP AND POWER UP SEQUENCING The power-up/down order and timing is defined by user register settings. The default settings support the E Ink® Vizplex™ panel and typically do not need to be changed. In SLEEP mode the TPS65186 is completely turned off, the I2C registers are reset, and the device does not accept any I2C transaction. Pull the WAKEUP pin high with the PWRUP pin low and the device enters STANDBY mode which enables the I2C interface.
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TPS65186 SLVSB04 – JULY 2011 www.ti.com VIN I2C 1.8ms (1) PWRUP SLEEP WAKEUP STANDBY ACTIVE ACTIVE 50ms VN VB UDLY 1 DDLY 4 UDLY 1 VNEG UDLY 2 UDLY 2 VEE UDLY 3 DDLY 3 UDLY3 PRODUCT PREVIEW VPOS UDLY 4 DDLY 2 UDLY 4 VDDH DDLY 1 PWR_GOOD 300 us (max) 300 us (max) (1) Minimum delay time between WAKEUP rising edge and IC rady to accept I 2C transaction . In this example the first power-up sequence is started by pulling the PWRUP pin high (rising edge).
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TPS65186 SLVSB04 – JULY 2011 www.ti.com V3P3 POWER SWITCH The integrated power switch is used to cut the 3.3-V supply to the EPD panel and is controlled through the V3P3_EN pin of the ENABLE register. In SLEEP mode the switch is automatically turned off and its output is discharged to ground. The default power-up state is OFF. To turn the switch ON, set the V3P3_ENbit to 1. VCOM ADJUSTMENT VCOM is the output of a power-amplifier with an output voltage range of 0 V to -5.11 V, adjustable in 10-mV steps.
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TPS65186 SLVSB04 – JULY 2011 SETUP www.ti.
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TPS65186 SLVSB04 – JULY 2011 www.ti.com FAULT HANDLING AND RECOVERY The TPS65186 monitors input and output voltages and die temperature and will take action if operating conditions are outside normal limits. Whenever the TPS65186 encounters: • Thermal Shutdown (TSD) • Positive Boost Under Voltage (VB_UV) • Inverting Buck-Boost Under Voltage (VN_UV) • Input Under Voltage Lock Out (UVLO) it shuts down all power rails and enters STANDBY mode. Shut-down follows the order defined by DWNSEQx registers.
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TPS65186 SLVSB04 – JULY 2011 www.ti.com NTC BIAS CIRCUIT Figure 27 below shows the block diagram of the NTC bias and measurement circuit. The NTC is biased from an internally generated 2.25-V reference voltage through an integrated 7.307-KΩ bias resistor. A 43-kΩ resistor is connected parallel to the NTC to linearize the temperature response curve. The circuit is designed to work with a nominal 10-kΩ NTC and achieves accuracy of ±1°C from 0°C to 50°C.
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TPS65186 SLVSB04 – JULY 2011 www.ti.com • • • When the temperature is equal or greater than the TMST_HOT[3:0] threshold, the TMST_HOT interrupt bit of the INT1 register is set, and the nINT pin is pulled low. If the last temperature is different from the baseline temperature by ±2°C (default) or more, the DTX interrupt bit of the INT1 register is set. The latest temperature becomes the new baseline temperature. Please note that by default the DTX interrupt is disabled, i.e.
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TPS65186 SLVSB04 – JULY 2011 www.ti.com reception of the data word sent to the device. A stop condition is recognized as a low to high transition of the SDA input during the high portion of the SCL signal. All other transitions of the SDA line must occur during the low portion of the SCL signal. An acknowledge is issued after the reception of valid address, sub-address and data words.
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TPS65186 SLVSB04 – JULY 2011 www.ti.com DATA TRANSMISSION TIMING VBAT = 3.6 V ±5%, TA = 25ºC, CL = 100 pF (unless otherwise noted) f(SCL) Serial clock frequency tHD;STA Hold time (repeated) START condition. After this period, the first clock pulse is generated.
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TPS65186 SLVSB04 – JULY 2011 www.ti.com ENABLE (ENABLE) Address – 0x01h DATA BIT D7 D6 D5 D4 D3 D2 D1 D0 FIELD NAME ACTIVE STANDBY V3P3_EN VCOM_EN VDDH_EN VPOS_EN VEE_EN VNEG_EN READ/WRITE R/W R/W R/W R/W R/W R/W R/W R/W RESET VALUE 0 0 0 0 0 0 0 0 BIT DEFINITION (1) FIELD NAME STANDBY to ACTIVE transition bit ACTIVE 1 – Transition from STANDBY to ACTIVE mode.
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TPS65186 SLVSB04 – JULY 2011 www.ti.com POWER UP SEQUENCE REGISTER 1 (UPSEQ1) Address – 0x0Ah DATA BIT FIELD NAME D7 D6 UDLY4[1:0] D5 D4 UDLY3[1:0] D3 D2 UDLY2[1:0] D1 D0 UDLY1[1:0] READ/WRITE R/W R/W R/W R/W R/W R/W R/W R/W RESET VALUE 0E2 1E2 0E2 1E2 0E2 1E2 0E2 1E2 FIELD NAME BIT DEFINITION DLY4 delay time set; defines the delay time from STROBE3 to STROBE4 during power-up.
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TPS65186 SLVSB04 – JULY 2011 www.ti.com POWER DOWN SEQUENCE REGISTER 1 (DWNSEQ1) Address – 0x0Ch DATA BIT FIELD NAME D7 D6 DDLY4[1:0] D5 D4 D2 DDLY2[1:0] D1 D0 DDLY1 DFCTR READ/WRITE R/W R/W R/W R/W R/W R/W R/W R/W RESET VALUE 1E2 1E2 1E2 0E2 0E2 0E2 0E2 0E2 FIELD NAME DDLY3[1:0] D3 BIT DEFINITION DLY4 delay time set; defines the delay time from STROBE3 to STROBE4 during power-down.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS65186RGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 TPS65186RGZT VQFN RGZ 48 250 180.0 16.4 7.3 7.3 1.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS65186RGZR VQFN RGZ 48 2500 367.0 367.0 38.0 TPS65186RGZT VQFN RGZ 48 250 210.0 185.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.