Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - power management - special purpose 2.5 A VQFN 48 (6x6)

TPS65217A, TPS65217B, TPS65217C, TPS65217D

www.ti.com

SLVSB64F –NOVEMBER 2011–REVISED APRIL 2013

SINGLE-CHIP PMIC FOR BATTERY-POWERED SYSTEMS

Check for Samples: TPS65217A, TPS65217B, TPS65217C, TPS65217D

FEATURES

234

CHARGER/POWER PATH

– Switch Impedance 300 mΩ (Typical)

– 200-mA Current Limit

• 2-A Output Current on Power Path

– Passive Discharge to Ground When

• Linear Charger; 700-mA Maximum Charge

Disabled

Current

• Configured as LDOs:

• 20-V Tolerant USB and AC Inputs

– LDO Output Voltage Range: 1.5 V – 3.3 V

• 100-mA, 500-mA, 1300-mA or 1800-mA Current

Limit on USB Input

– VIN Range: 2.7 V – 5.8 V

• Thermal Regulation, Safety Timers

– 200-mA Current Limit (TPS65217A, B)

• Temperature Sense Input

– 400-mA Current Limit (TPS65217C, D)

– Passive Discharge to Ground When

STEP-DOWN CONVERTER (DCDC1, 2, 3)

Disabled

• Three Step-Down Converter With Integrated

Switching FETs

WLED DRIVER

– DCDC1: 0.9 V – 1.8 V at 1.2 A

• Internally Generated PWM for Dimming

Control

– DCDC2: 0.9 V – 3.3 V at 1.2 A

• 38-V Open LED Protection

– DCDC3: 0.9 V – 1.5 V at 1.2 A

• Supports Two Strings of Up To 10 LEDs at

• VIN Range: 2.7 V – 5.8 V

25 mA Each

• 2.25-MHz Fixed Frequency Operation

• Internal Low-Side Current Sinks

• Power Save Mode at Light Load Current

• Output Voltage Accuracy in PWM Mode ±2.0%

PROTECTION

• 100% Duty Cycle for Lowest Dropout

• Undervoltage Lockout and Battery Fault

• Typical 15-µA Quiescent per Converter

Comparator

• Passive Discharge to Ground When Disabled

• Always-On Push-Button Monitor

• Hardware Reset Pin

LDOs (LDO1, 2)

• Password Protected I

Registers

• Two Adjustable LDOs

– LDO1: 1.0 V – 3.3 V (1.8-V Default)

INTERFACE

at 100 mA

• I

C Interface (Address 0x24)

– LDO2: 0.9V – 3.3 V (3.3-V Default) at 100 mA

• Password Protected I

C Registers

• VIN Range: 1.8 V – 5.8 V

PACKAGE

• LDO2 Can Be Configured to Track DCDC3

• Available in 6-mm × 6-mm, 48-Pin QFN

• Typical 15-µA Quiescent Current

APPLICATIONS

LOAD SWITCHES (LDO3, 4)

• AM335x ARM

Cortex™-A8 Microprocessors

• Two Independent Load Switches That Can Be

• Portable Navigation Systems

Configured as LDOs

• Tablet Computing

• Configured as Switches:

• 5-V Industrial Equipment

– VIN Range: 1.8 V – 5.8 V

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2Cortex is a trademark of ARM Ltd or its subsidiaries.

3ARM is a registered trademark of ARM Ltd or its subsidiaries.

C is a registered trademark of Philips Semiconductors Corporation.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (86 pages)

PAGE 1
TPS65217A, TPS65217B, TPS65217C, TPS65217D www.ti.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 www.ti.com DESCRIPTION The TPS65217 is a single chip power management IC specifically designed to support the AM335x series of application processors in portable and 5-V, non-portable applications.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D www.ti.com SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 www.ti.com ORDERING INFORMATION (1) TA PACKAGE -40°C to 105°C (1) (2) ORDERABLE PART NUMBER (2) TOP-SIDE MARKING TPS65217ARSL TPS65217A RSL TPS65217BRSL TPS65217B TPS65217CRSL TPS65217C TPS65217DRSL TPS65217D For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D www.ti.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 TERMINAL NAME www.ti.com I/O NO. DESCRIPTION L1 20 O Switch pin for DCDC1. Connect to inductor. VIN_DCDC1 21 I Input voltage for DCDC1. Must be connected to SYS pin. VIN_DCDC2 22 I Input voltage for DCDC2. Must be connected to SYS pin. L2 23 O Switch pin for DCDC2. Connect to inductor. VDCDC2 24 O DCDC2 output/feedback voltage sense input PB_IN 25 I Push-button monitor input.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D www.ti.com SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) (2) VALUE Supply voltage range (with respect to PGND) Input/Output voltage range (with respect to PGND) BAT -0.3 to 7 USB, AC -0.3 to 20 All pins unless specified separately -0.3 to 7 ISINK -0.3 to 20 L4, FB_WLED -0.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 www.ti.com ELECTRICAL CHARACTERISTICS VBAT = 3.6 V ±5%, TJ = 27ºC (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT VOLTAGE AND CURRENTS VBAT Battery input voltage range VAC AC adapter input voltage range VUSB USB input voltage range Under voltage lock-out VUVLO USB or AC supply connected 0 5.5 2.75 5.5 Valid range for charging 4.3 5.8 V Valid range for charging 4.3 5.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D www.ti.com SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 ELECTRICAL CHARACTERISTICS (continued) VBAT = 3.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VBAT = 3.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D www.ti.com SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 ELECTRICAL CHARACTERISTICS (continued) VBAT = 3.6 V ±5%, TJ = 27ºC (unless otherwise noted) PARAMETER TEST CONDITIONS Output voltage range VOUT IOUT MIN TYP MAX External resistor divider (XADJ2 = 1) 0.6 VIN I2C selectable in 25-mV steps (XADJ2 = 0) 0.9 3.3 -2 3 DC output voltage accuracy VIN = VOUT + 0.3 V to 5.8 V; 0 mA ≤ IOUT ≤ 1.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VBAT = 3.6 V ±5%, TJ = 27ºC (unless otherwise noted) PARAMETER TEST CONDITIONS Output voltage range VOUT TYP MAX 1.0 3.3 LDO2, I2C selectable 0.9 3.3 IOUT = 10 mA, VIN > VOUT + 200 mV, VOUT > 0.9 V -2 2 Line regulation VIN = 2.7 V - 5.5 V, VOUT = 1.2 V, IOUT = 100 mA -1 1 IOUT = 1 mA - 100 mA, VOUT = 1.2 V, VIN = 3.3 V -1 1 -2.5 2.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D www.ti.com SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 ELECTRICAL CHARACTERISTICS (continued) VBAT = 3.6 V ±5%, TJ = 27ºC (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 5.8 V 300 650 mΩ LS1/LDO3 & LS2/LDO4, CONFIGURED AS LOAD SWITCHES VIN Input voltage range LS1_VIN, LS2_VIN pins RDS(ON) P-channel MOSFET on-resistance VIN = 1.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VBAT = 3.6 V ±5%, TJ = 27ºC (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG MULTIPLEXER Gain, VBAT, VSYS VBAT/VOUT,MUX; VSYS/VOUT,MUX 3 Gain, VTS, MUX_IN VTS/VOUT,MUX; VMUX_IN/VMUX_OUT 1 g ICHRG[1:0] = 00b 7.575 ICHRG[1:0] = 01b 5.625 ICHRG[1:0] = 10b 4.500 ICHRG[1:0] = 11b 3.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D www.ti.com SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 MODES OF OPERATION OFF In OFF mode the PMIC is completely shut down with the exception of a few circuits to monitor the AC, USB, and push-button input. All power rails are turned off and the registers are reset to their default values. The I2C communication interface is turned off. This is the lowest-power mode of operation.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 www.ti.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D www.ti.com SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 WAKE-UP AND POWER UP SEQUENCING The TPS65217 has a pre-defined power-up / power-down sequence which in a typical application does not need to be changed. However, it is possible to define custom sequences under I2C control. The power-up sequence is defined by strobes and delay times.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 www.ti.com The power up sequence is executed if one of the following events occurs: From OFF State: • Push-button is pressed (falling edge on PB_IN) OR • USB voltage is asserted (rising edge on USB) OR • AC adaptor is inserted (rising edge on AC) AND • PWR_EN pin is asserted (pulled high) AND • Device is not in Under Voltage Lockout (UVLO) or Over Temperature Shutdown (OTS).
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TPS65217A, TPS65217B, TPS65217C, TPS65217D www.ti.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 www.ti.com LDO1, LDO2 PGOOD (LDO_PGOOD) LDO_PGOOD is a push-pull output which is driven to high-level whenever LDO1 and/or LDO2 are enabled and in regulation. It is pulled low when both LDOs are disabled or at least one is enabled but has encountered a fault. A typical fault is an output short or over-current condition. In normal operation LDO_PGOOD is high in ACTIVE and SLEEP state and low in RESET or OFF state.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D www.ti.com SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 PUSH BUTTON MONITOR (PB_IN) The TPS65217 has an active-low push-button input which is typically connected to a momentary switch to ground. The PB_IN input has a 50ms deglitch time and an internal pull-up resistor to an always-on supply. The push button monitor is used to: • Power-up the device from OFF or SLEEP mode upon detecting a falling edge on PB_IN.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 www.ti.com POWER ENABLE PIN (PWR_EN) The PWR_EN pin is used to keep the unit in ACTIVE mode once it has detected a wakeup event as described in the Modes of Operation section. If the PWR_EN pin is not asserted within 5 seconds of the nWAKEUP pin being pulled low, the device will shut down the power and enter either OFF or SLEEP mode, depending on the OFF bit in the STATUS register.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D www.ti.com SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 ANALOG MULTIPLEXER The TPS65217 provides an analog multiplexer that allow access to critical system voltages such as: • battery voltage (VBAT) • system voltage (VSYS) • temperature sense voltage (VTS), and • VICHARGE, a voltage proportional to the charging current. In addition one external input is available to monitor an additional system voltage.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 www.ti.com BATDET VBAT 1 4.1V 0 AC detect AC VSYS ACSINK AC_EN AC_SINK SWITCH CONTROL VBAT IAC[1:0] USB detect USB USBSINK USB_EN USB_SINK SWITCH CONTROL BACKGATE CONTROL ISC BAT IUSB[1:0] enable BAT _SENSE CHRGER CONTROL TS CHG_EN SUSP RESET ICHRG[1:0] DPPMTH[1:0] BATDET TERMIF[1:0] TERM 1.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D www.ti.com SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 1000mA System load ISYS 700mA Time 500mA Charge current setting IBAT 300mA Time IAC 1300mA 1300mA current limit 1200mA Time Figure 9. Power Path Management. In this example the AC input current limit is set to 1300 mA, battery charge current is 500 mA and system load is 700 mA.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 www.ti.com AC and USB Input Discharge AC and USB inputs have 90-µA internal current sinks which are used to discharge the input pins to avoid false detection of an input source. The AC sink is enabled when USB is a valid supply and VAC is below the detection threshold. Likewise, the USB sink is enabled when AC is a valid supply and VUSB is below the detection limit.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D www.ti.com SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 Charge Termination When the charging current drops below the termination current threshold, the charger is turned off. The value of the termination current threshold can be set in register CHGCONFIG3 using bits TERMIF[1:0]. The termination current has a default setting of 7.5% of the ICHRG[1:0] setting.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 www.ti.com The fault status is indicated by CHTOUT and PCHTOUT bits in CHGCONFIG0 register. Timeout faults are cleared and a new charge cycle is started when either USB or AC supplies are connected (rising edge of VUSB or VAC), the charger RESET bit is set to 1 in the CHGCONFIG1 register, or the battery voltage drops below the recharge threshold VRCH.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D www.ti.com SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 Charge Current Charge Current NOTE The device can be configured to support a 100-kΩ NTC (B = 3960) by setting the the NTC_TYPE bit in register CHGCONFIG1 to 1. However it is not recommended to do so. In sleep mode the charger continues charging the battery but all register values are reset to default values, therefore the charger would get wrong temperature information.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 www.ti.com DCDC CONVERTERS Operation The TPS65217 step down converters typically operate with 2.25-MHz fixed frequency pulse width modulation (PWM) at moderate to heavy load currents. At light load currents the converter automatically enters Power Save Mode and operates in PFM (Pulse Frequency Modulation).
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TPS65217A, TPS65217B, TPS65217C, TPS65217D www.ti.com SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 During the Power Save Mode the output voltage is monitored with a PFM comparator. As the output voltage falls below the PFM comparator threshold of VOUT - 1%, the device starts a PFM current pulse. For this the high-side MOSFET will turn on and the inductor current ramps up. Then it is turned off and the low-side MOSFET switch turns on until the inductor current becomes 0 again.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 www.ti.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D www.ti.com SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 where: f = Switching frequency (2.25 MHz typical) L = Inductor value ΔIL = Peak to peak inductor ripple current ILmax = Maximum inductor current The highest inductor current will occur at maximum VIN. Open core inductors have a soft saturation characteristic and they can usually handle higher inductor currents versus a comparable shielded inductor.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 www.ti.com Input Capacitor Selection Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is required for best input voltage filtering and minimizing the interference with other circuits caused by high input voltage spikes. The converters need a ceramic input capacitor of 10 µF. The input capacitor can be increased without any limit for better input voltage filtering.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D www.ti.com SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 WHITE LED DRIVER TPS65217 contains a boost converter and two current sinks capable of driving up to 2 x 10 LEDs at 25 mA or a single string at 50 mA of current. The current per current sink is approximated by the following equation: I LED = 1048´ 1.24V RSET (7) Two different current levels can be programmed using two external RSET resistors.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 www.ti.com BATTERY-LESS/5-V OPERATION TPS65217 provides a linear charger for Li+ batteries but the IC can operate without a battery attached. There are three basic use-cases for battery-less operation: 1. The system is designed for battery operation, but the battery is not inserted. The system can be powered by connecting an AC adaptor or USB supply. 2.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D www.ti.com SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 Table 5. Functional Differences Between Battery-Less/5-V Only Operation With and Without 20-V Input Over-Voltage Protection (continued) POWER SUPPLIED THROUGH AC PIN (CASE (1) AND (2)) Response to input-over-voltage Device enters OFF mode. NOTE: If a battery is present in the system, TPS65217 automatically switches from AC to BAT supply when AC input exceeds 6.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 S SLAVE ADDRESS W A www.ti.com REG ADDRESS A DATA REGADDR A DATA SUBADDR +n A DATA SUBADDR +n+1 Ā P A S SLAVE ADDRESS R A DATA REGADDR +n A n bytes + ACK S SLAVE ADDRESS W A REG ADDRESS DATA REGADDR A DATA REGADDR + n+1 Ā P n bytes + ACK From master to slave R Read (high) S Start Ā Not Acknowlege From slave to master W Write (low) P Stop A Acknowlege Figure 20. I2C Data Protocol.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D www.ti.com SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 DATA TRANSMISSION TIMING VBAT = 3.6 V ±5%, TA = 25ºC, CL = 100 pF (unless otherwise noted) PARAMETER TEST CONDITIONS fSCL Serial clock frequency tHD;STA Hold time (repeated) START condition.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 www.ti.com PASSWORD PROTECTION Registers 0x0B through 0x1F with exception of the password register are protected against accidental write by a 8-bit password. The password needs to be written prior to writing to a protected register and is automatically reset to 0x00h after the following I2C transaction, regardless of the register that was accessed and regardless of the transaction type (read or write).
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TPS65217A, TPS65217B, TPS65217C, TPS65217D www.ti.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 www.ti.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D www.ti.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 www.ti.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D www.ti.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 www.ti.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D www.ti.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 www.ti.com CHARGER CONFIGURATION REGISTER 3 (CHGCONFIG3) Address – 0x06h DATA BIT D7 FIELD NAME D6 D5 ICHRG[1:0] D4 DPPMTH[1:0] D3 D2 PCHRGT D1 TERMIF[1:0] D0 TRANGE READ/WRITE R/W R/W R/W R/W R/W R/W R/W R/W RESET VALUE 1 0 1 1 0 0 1 0 FIELD NAME BIT DEFINITION Charge current setting 00 – 300 mA ICHRG[1:0] 01 – 400 mA 10 – 500 mA 11 – 700 mA Power path DPPM threshold 00 – 3.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D www.ti.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 www.ti.com WLED CONTROL REGISTER 2 (WLEDCTRL2) Address – 0x08h DATA BIT D7 D6 D5 D4 D3 D2 D1 D0 FIELD NAME not used READ/WRITE R/W R/W R/W R/W DUTY[6:0] R/W R/W R/W R/W RESET VALUE 0 0 0 0 0 0 0 0 FIELD NAME not used BIT DEFINITION N/A 000 0000 – 1% 000 0001 – 2% ... 110 0010 – 99% DUTY[6:0] 110 0011 – 100% 110 0100 – 0% ...
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TPS65217A, TPS65217B, TPS65217C, TPS65217D www.ti.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 www.ti.com STATUS REGISTER (STATUS) Address – 0x0Ah DATA BIT D7 D6 D5 D4 D3 D2 D1 D0 FIELD NAME OFF not used not used not used ACPWR USBPWR not used PB READ/WRITE R/W R/W R/W R/W R R R R RESET VALUE 0 0 0 0 0 0 0 0 FIELD NAME BIT DEFINITION OFF OFF bit. Set this bit to 1 to enter OFF state when PWR_EN pin is pulled low. Bit is automatically reset to 0.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D www.ti.com SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 PASSWORD REGISTER (PASSWORD) Address – 0x0Bh DATA BIT D7 D6 D5 D4 READ/WRITE R/W R/W R/W R/W RESET VALUE 0 0 0 0 FIELD NAME D3 D2 D1 D0 R/W R/W R/W R/W 0 0 0 0 PWRD[7:0] FIELD NAME BIT DEFINITION 0000 0000 – Password protected registers are locked for write access ...
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TPS65217A, TPS65217B, TPS65217C, TPS65217D SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 www.ti.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D www.ti.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 www.ti.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D www.ti.com SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 FIELD NAME BIT DEFINITION (TPS65217C) DCDC1 voltage adjustment option XADJ1 0 – Output voltage is adjusted through register setting 1 – Output voltage is externally adjusted not used N/A DCDC1 output voltage setting DCDC1[5:0] 00 0000 – 0.900 V 01 0000 – 1.300 V 10 0000 – 1.900 V 11 0000 – 2.700 V 00 0001 – 0.925 V 01 0001 – 1.325 V 10 0001 – 1.950 V 11 0001 – 2.750 V 00 0010 – 0.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 www.ti.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D www.ti.com SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 FIELD NAME BIT DEFINITION (TPS65217B, TPS65217C, TPS65217D) DCDC2 voltage adjustment option XADJ2 0 – Output voltage is adjusted through register setting 1 – Output voltage is externally adjusted not used N/A DCDC2 output voltage setting DCDC2[5:0] 00 0000 – 0.900 V 01 0000 – 1.300 V 10 0000 – 1.900 V 11 0000 – 2.700 V 00 0001 – 0.925 V 01 0001 – 1.325 V 10 0001 – 1.950 V 11 0001 – 2.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 www.ti.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D www.ti.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 www.ti.com LDO1 CONTROL REGISTER (DEFLDO1) Address – 0x12h (Password Protected) DATA BIT D7 D6 D5 D4 D3 D2 D1 D0 FIELD NAME not used not used not used not used READ/WRITE R/W R/W R/W R/W R/W R/W R/W R/W RESET VALUE 0 0 0 0 1 0 0 1 FIELD NAME LDO1[3:0] BIT DEFINITION not used N/A not used N/A not used N/A not used N/A LDO1 output voltage setting LDO1[3:0] 62 0000 – 1.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D www.ti.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 www.ti.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D www.ti.com SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 FIELD NAME BIT DEFINITION (TPS65217C, TPS65217D) not used N/A not used N/A LS / LDO configuration bit LS1LDO3 0 – FET functions as load switch (LS1) 1 – FET is configured as LDO3 LDO3 output voltage setting (LS1LDO3 = 1) LDO3[4:0] 0 0000 – 1.50 V 0 1000 – 1.90 V 1 0000 – 2.55 V 1 1000 – 2.95 V 0 0001 – 1.55 V 0 1001 – 2.00 V 1 0001 – 2.60 V 1 1001 – 3.00 V 0 0010 – 1.60 V 0 1010 – 2.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 www.ti.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D www.ti.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 www.ti.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D www.ti.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 www.ti.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D www.ti.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 www.ti.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D www.ti.com SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 FIELD NAME BIT DEFINITION (TPS65217B) LDO2 enable STROBE 0000 – rail is not controlled by sequencer 0001 – enable at STROBE1 0010 – enable at STROBE2 0011 – enable at STROBE3 0100 – enable at STROBE4 LDO2_SEQ[3:0] 0101 – enable at STROBE5 0110 – enable at STROBE6 0111 – enable at STROBE7 1000 – rail is not controlled by sequencer 1001 – rail is not controlled by sequencer ...
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TPS65217A, TPS65217B, TPS65217C, TPS65217D SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 FIELD NAME www.ti.com BIT DEFINITION (TPS65217C, TPS65217D) LDO2 enable STROBE 0000 – rail is not controlled by sequencer 0001 – enable at STROBE1 0010 – enable at STROBE2 0011 – enable at STROBE3 0100 – enable at STROBE4 LDO2_SEQ[3:0] 0101 – enable at STROBE5 0110 – enable at STROBE6 0111 – enable at STROBE7 1000 – rail is not controlled by sequencer 1001 – rail is not controlled by sequencer ...
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TPS65217A, TPS65217B, TPS65217C, TPS65217D www.ti.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 www.ti.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D www.ti.
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TPS65217A, TPS65217B, TPS65217C, TPS65217D SLVSB64F – NOVEMBER 2011 – REVISED APRIL 2013 www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com (4) 17-May-2013 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
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PACKAGE MATERIALS INFORMATION www.ti.com 30-May-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing TPS65217ARSLR VQFN RSL 48 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2 TPS65217ARSLT VQFN RSL 48 250 180.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2 TPS65217BRSLR VQFN RSL 48 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 30-May-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS65217ARSLR VQFN RSL 48 2500 367.0 367.0 38.0 TPS65217ARSLT VQFN RSL 48 250 210.0 185.0 35.0 TPS65217BRSLR VQFN RSL 48 2500 367.0 367.0 38.0 TPS65217BRSLT VQFN RSL 48 250 210.0 185.0 35.0 TPS65217CRSLR VQFN RSL 48 2500 367.0 367.0 38.0 TPS65217CRSLT VQFN RSL 48 250 210.0 185.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.