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TPS65250

www.ti.com

SLVSAA3C –JUNE 2010–REVISED OCTOBER 2012

4.5-V TO 18-V INPUT, HIGH CURRENT, SYNCHRONOUS STEP DOWN THREE BUCK

CONVERTER WITH INTEGRATED FET AND DYING GASP STORAGE AND RELEASE

CIRCUIT

Check for Samples: TPS65250

FEATURES

• Wide Input Supply Voltage Range • Soft Start Pins

(4.5 V - 18 V)

• Current-Mode Control With Simple

• 0.8 V, 1% Accuracy Reference Compensation Circuit

• Continuous Loading: 3 A (Buck 1), • Power Good and Reset Generator

2 A (Buck 2 and 3)

• Storage and Release Circuit Optimized for

• Maximum Current: 3.5 A (Buck 1), Reduction of Storage Capacitance in Dying

2.5 A (Buck 2 and 3) Gasp Mode (Option)

• Adjustable Switching Frequency • Low Power Mode Set By External Signal

300 kHz - 2.2 MHz Set By External Resistor

• QFN Package, 40-Pin 6 mm x 6 mm RHA

• External Synchronization Pin for Oscillator

APPLICATIONS

• External Enable/Sequencing and Soft Start

Pins

• xDSL/xPON Modems

• Adjustable Current Limit Set By External

• Cable Modems

Resistor

• Power Line Modem

• Home Gateway and Access Point Networks

• Wireless Routers

• Set Top Box

DESCRIPTION/ORDERING INFORMATION

The TPS65250 features three synchronous wide input range high efficiency buck converters. The converters are

designed to simplify its application while giving the designer the option to optimize their usage according to the

target application.

The converters can operate in 5-, 9-, 12- and 15-V systems and have integrated power transistors. The output

voltage can be set externally using a resistor divider to any value between 0.8 V and the input supply minus 1 V.

Each converter features enable pin that allows a delayed start-up for sequencing purposes, soft start pin that

allows adjustable soft-start time by choosing the soft-start capacitor, and a current limit (RLIMx) pin that enables

designer to adjust current limit by selecting an external resistor and optimize the choice of inductor. The COMP

pin allows optimizing transient versus dc accuracy response with a simple RC compensation.

The switching frequency of the converters can either be set with an external resistor connected to ROSC pin or

can be synchronized to an external clock connected to SYNC pin if needed. The switching regulators are

designed to operate from 300 kHz to 2.2 MHz. Both Bucks 2 and Buck 3 run in-phase and 180° out of phase with

Buck 1 to minimize input filter requirements.

TPS65250 features a unique storage and release circuitry for dying gasp mode. The storage capacitor is

separated from input capacitor during normal operation. The storage and release circuit will charge the storage

capacitor with a controlled circuit to reduce the inrush current from the adaptor supply to a storage voltage of

20 V to accumulate as much energy as possible taking advantage of the ½ CV² feature.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (38 pages)

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TPS65250 www.ti.com SLVSAA3C – JUNE 2010 – REVISED OCTOBER 2012 4.5-V TO 18-V INPUT, HIGH CURRENT, SYNCHRONOUS STEP DOWN THREE BUCK CONVERTER WITH INTEGRATED FET AND DYING GASP STORAGE AND RELEASE CIRCUIT Check for Samples: TPS65250 FEATURES 1 • • • • • • • • Wide Input Supply Voltage Range (4.5 V - 18 V) 0.8 V, 1% Accuracy Reference Continuous Loading: 3 A (Buck 1), 2 A (Buck 2 and 3) Maximum Current: 3.5 A (Buck 1), 2.5 A (Buck 2 and 3) Adjustable Switching Frequency 300 kHz - 2.
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TPS65250 SLVSAA3C – JUNE 2010 – REVISED OCTOBER 2012 www.ti.com TPS65250 continuously monitors the input voltage. Once the input voltage drops below a release voltage of 10.5 V, the circuit tries to transfer charge from storage capacitor to the input capacitor keeping the input voltage closer to release value for as long as possible. The release voltage should be set lower than the processor dying gasp detect voltage.
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TPS65250 www.ti.com SLVSAA3C – JUNE 2010 – REVISED OCTOBER 2012 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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TPS65250 SLVSAA3C – JUNE 2010 – REVISED OCTOBER 2012 www.ti.
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TPS65250 www.ti.com SLVSAA3C – JUNE 2010 – REVISED OCTOBER 2012 TERMINAL FUNCTIONS (DCA) NAME NO. I/O DESCRIPTION RLIM3 1 I Current limit setting for Buck 3. Fit a resistor from this pin to ground to set the peak current limit on the output inductor. SS3 2 I Soft start pin for Buck 3. Fit a small ceramic capacitor to this pin to set the converter soft start time. COMP3 3 O Compensation for Buck 3. Fit a series RC circuit to this pin to complete the compensation circuit of this converter.
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TPS65250 SLVSAA3C – JUNE 2010 – REVISED OCTOBER 2012 www.ti.com TERMINAL FUNCTIONS (DCA) (continued) NO. I/O GASP NAME 31 O Open drain output to signal dying gasp operation to host (active low). DESCRIPTION LDODG 32 O Dying gaps 18-V supply output. Decouple with a 10-µF, 25-V ceramic capacitor. VINDG 33 I Dying gasp circuit connection to input supply. Fit a 10-µF ceramic capacitor close to this pin. STRG 34 O Reservoir capacitor for dying gasps "storage and release" operation.
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TPS65250 www.ti.com SLVSAA3C – JUNE 2010 – REVISED OCTOBER 2012 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VIN Input operating voltage 4.
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TPS65250 SLVSAA3C – JUNE 2010 – REVISED OCTOBER 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VIN = 12 V ±5%, VINB2, VINB3 = 5 V ±5%, TJ = –40°C to 125°C, fSW = 1 MHz (unless otherwise noted) MAX UNIT FSW_BK Converter switching frequency range PARAMETER Set externally with resistor TEST CONDITIONS MIN 0.3 TYP 2.
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TPS65250 www.ti.com SLVSAA3C – JUNE 2010 – REVISED OCTOBER 2012 ELECTRICAL CHARACTERISTICS (continued) VIN = 12 V ±5%, VINB2, VINB3 = 5 V ±5%, TJ = –40°C to 125°C, fSW = 1 MHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN 0.2 TYP MAX UNIT ILDO_LIMIT Pump and dump LDO current limit VIN = 12 V, maximum charge current supplied by VIN tPRECHARGE Time to charge storage capacitor to VIN with IPRECHARGE_LIMIT VIN = 12 V, VSTORAGE = 18 V.
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TPS65250 SLVSAA3C – JUNE 2010 – REVISED OCTOBER 2012 www.ti.com STATE MACHINE Reset state Reset state (VIN is low) Read EEPROM VIN>1.5 Check Internal Rails (VIN, V3, and V7) PreCharge nPUC=LO or BU_EN=LO Vstorage charges toward VIN VIN>Vrelease && BU_EN Faultint=1 OR Faultext=1 Discharge Enable capacitors for 10msec VIN<1.
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TPS65250 www.ti.com SLVSAA3C – JUNE 2010 – REVISED OCTOBER 2012 TYPICAL CHARACTERISTICS Buck 1 TA = 25°C, VIN = 12 V, fSW = 1.1 MHz (unless otherwise noted) Figure 5. Start-Up VOUT = 3.3 V, 2 A Figure 6. Start-Up VOUT = 1.2 V, 3.5 A Figure 7. Ripple VOUT = 3.3 V, 1.5 A, fSW = 1.1 MHz, 20 mV/div Figure 8. Ripple VOUT = 1.2 V, 4 A, fSW = 1.1 MHz, 50 mV/div Figure 9. Transient Load Response VOUT = 3.3 V, ∆I = 1 A to 1.5 A, 100 mV/div Figure 10. Transient Load Response VOUT = 1.2 V, ∆I = 1.
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TPS65250 SLVSAA3C – JUNE 2010 – REVISED OCTOBER 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) Buck 1 TA = 25°C, VIN = 12 V, fSW = 1.1 MHz (unless otherwise noted) 12 Figure 11. Transient Supply Response VOUT = 3.3 V, ∆V = 8 V to 16.5 V, 20 mV/div Figure 12. Efficiency VOUT = 3.3 V, L= 4.7 µH, DCR = 28 mΩ Figure 13. Efficiency VOUT = 1.2 V, L = 4.7 µH, DCR = 28 mΩ Figure 14. Efficiency Low Power Enabled VOUT = 3.3 V, L = 4.
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TPS65250 www.ti.com SLVSAA3C – JUNE 2010 – REVISED OCTOBER 2012 TYPICAL CHARACTERISTICS Buck 2 TA = 25°C, VIN = 12 V, fSW = 1.14 MHz (unless otherwise noted) Figure 15. Start-Up VOUT = 2.5 V, 1.5 A Figure 16. Ripple VOUT = 2.5 V, 2.5 A, fSW = 0.8 MHz 20 mV/div Figure 17. Transient Load Response VOUT = 2.5 V, ∆I = 1 A to 1.5 A Figure 18. Transient Load Response VOUT = 1.8 V, ∆I = 1 A to 2 A Figure 19. Transient Supply Response VOUT = 2.5 V, ∆V = 9 V to 8 V Figure 20. Efficiency VOUT = 3.3 V, L = 4.
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TPS65250 SLVSAA3C – JUNE 2010 – REVISED OCTOBER 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) Buck 2 TA = 25°C, VIN = 12 V, fSW = 1.14 MHz (unless otherwise noted) Figure 21. Efficiency VOUT = 1.8 V, L = 4.7 µH, DCR = 28 mΩ (Also Applies to Buck3) 14 Submit Documentation Feedback Figure 22. Efficiency Low Power Enabled VOUT = 2.5 V, L = 4.
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TPS65250 www.ti.com SLVSAA3C – JUNE 2010 – REVISED OCTOBER 2012 TYPICAL CHARACTERISTICS Buck 3 TA = 25°C, VIN = 12 V, fSW = 1.14 MHz (unless otherwise noted) Figure 23. Start-Up VOUT = 7.5 V, 0.7 A Figure 24. Ripple VOUT = 7.5 V, 2.5 A, fSW = 800 kHz 20 mV/div Figure 25. Transient Load Response VOUT = 7.5 V, ∆I = 1 A to 1.5 A Figure 26. Transient Supply Response VOUT = 2.5 V, ∆V = 9 V to 8 V Figure 27. Efficiency VOUT = 2.5 V, L = 4.7 µH, DCR = 28 mΩ (Also Applies to Buck2) Figure 28.
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TPS65250 SLVSAA3C – JUNE 2010 – REVISED OCTOBER 2012 www.ti.com TYPICAL APPLICATION CIRCUIT FOR ADSL SYSTEM AND COMPONENT SELECTION The TPS65250 has been devised to optimize the power train of xDSL applications. Figure 29 shows a simplified block diagram. PGOOD PGOOD monitor 6.5V LDOs Always ON 3.3V GASP GASP monitor BUCK1 SYS BUCK1 Vin=12V BUCK2 I/O BUCK2 BUCK3 Line driver BUCK3 DUMP PUMP adjustable 7.5-15.1V (Regulates up to 2Vin-1.5 + Figure 29.
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TPS65250 www.ti.com SLVSAA3C – JUNE 2010 – REVISED OCTOBER 2012 Table 1. Storage and Release Circuit Advantages (continued) FEATURE ADVANTAGE Adjustable current limit Using a resistor to set the peak current limit allows to choose the smallest possible inductor for a given load condition by setting the current limit to match the saturation current of the inductor. Adjustable frequency and sync pin TPS65250 can be synchronized to a 1.1-MHz or 2.2-MHz external clock.
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TPS65250 SLVSAA3C – JUNE 2010 – REVISED OCTOBER 2012 www.ti.com Out-of-Phase Operation Buck 1 has a low conduction resistance compared to Buck 2 and 3. Normally buck 1 is used to drive higher system loads. Buck 2 and 3 are used to drive some peripheral loads like I/O and line drivers . The combination of buck 2 and 3’s loads may be on par with Buck 1’s. In order to reduce input ripple current, buck 2 operates in phase with buck 3; buck 1 and buck 2 operate 180 degrees out-of-phase.
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TPS65250 www.ti.com SLVSAA3C – JUNE 2010 – REVISED OCTOBER 2012 Vo iL Co RL Gm=10A/V RESR Cff R1 Current Sense I/V Gain FBx g M = 130 u Vref = 0.8V COMPx R2 Rc CRoll Cc Figure 32. Loop Compensation The design guidelines for TPS65250 loop compensation are as follows: 1. Set up cross over frequency fc. 2. RC can be determined by: RC = 2p × fc × Vo × Co g M × Vref × gm ps (4) Where is the GM amplifier gain (130 µA/V), is the power stage gain (10 A/V). 3.
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TPS65250 SLVSAA3C – JUNE 2010 – REVISED OCTOBER 2012 www.ti.com To calculate the external compensation components follow the following steps: TYPE II CIRCUIT TYPE III CIRCUIT Select switching frequency that is appropriate for application depending on L, C sizes, output ripple, EMI concerns and etc. Switching frequencies between 500 kHz and 1 MHz give best trade off between performance and cost. When using smaller L and Cs, switching frequency can be increased.
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TPS65250 www.ti.com SLVSAA3C – JUNE 2010 – REVISED OCTOBER 2012 Current Limit Protection Figure 33 shows the (peak) inductor current limit for Buck 1. The typical limit can be approximated with the following graph. Figure 33. Buck 1 Figure 34 shows the (peak) inductor current limit for Buck 2. The typical limit can be approximated with the following graph. Figure 34. Buck 2 Figure 35 shows the (peak) inductor current limit for Buck 3. The typical limit can be approximated with the following graph.
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TPS65250 SLVSAA3C – JUNE 2010 – REVISED OCTOBER 2012 www.ti.com Figure 35. Buck 3 All converters operate in hiccup mode: Once an over-current lasting more than 10 ms is sensed in any of the converters, they will shuts down for 10 ms and then the start-up sequencing will be tried again. If the overload has been removed, the converter will ramp up and operate normally.
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TPS65250 www.ti.com SLVSAA3C – JUNE 2010 – REVISED OCTOBER 2012 THOT_SPOT = TA + PDIS · qJA (8) Where: TA is the ambient temperature PDIS is the sum of losses in all converters θJA is the junction to ambient thermal impedance of the device and it is heavily dependant on board layout Figure 36. Buck 1 VIN = 12 V, fSW = 500 kHz Figure 37. Buck 1 VIN = 12 V, fSW = 1.1 MHz Figure 38. Buck 2 and 3 VIN = 12 V, fSW = 500 kHz Figure 39. Buck 2 and 3 VIN = 12 V, fSW = 1.
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TPS65250 SLVSAA3C – JUNE 2010 – REVISED OCTOBER 2012 1 · DVOUT = ¾ C ( www.ti.com VIN L · ILIMIT2 ILOAD - ¾ ¾· ¾ 2 VOUT · (VIN - VOUT) fSLEEP_CLK ) (10) And the peak output voltage during low power operation is: DVOUT VOUT_PK = VOUT + ¾ 2 (11) VOUT_PK VOUT Figure 40.
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TPS65250 www.ti.com SLVSAA3C – JUNE 2010 – REVISED OCTOBER 2012 1 2 3 4 5 6 GND J3 VIN GND GND R2 0 R6 0 C33 19 C24 47nF GND TP16 20 GND C29 FB2A 47nF C18 41 GND EN2 PwrPad V3V 1 2 3 LDODG GASP R16 487k R15 16.9K C25 C8 3 47nF VIN 38 C9 4.7nF DNI GND C34 GND JP6 TDK-SLF7055 10uF GND 2 L3 GND GND 37 C11 4.7uH 36 35 7.5V@0.
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TPS65250 SLVSAA3C – JUNE 2010 – REVISED OCTOBER 2012 www.ti.com The control and power signals used in the design are shown in Table 2. Table 2. Control and Power Signals SIGNAL TYPE STATUS FUNCTION POWER VIN I 12-V DC main supply to TPS65250 GND System ground. All ground pins and power pad should be connected together. 3.3V O Output of Buck 1 2.5V O Output of Buck 2 7.5V O Output of Buck 3 VPULL O Voltage used to connect the pull-up resistors of the Open Drain outputs (PGOOD, GASP).
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TPS65250 www.ti.com SLVSAA3C – JUNE 2010 – REVISED OCTOBER 2012 For this design example, use KIND = 0.2 and the inductor value is calculated to be 5.4 µH. For this design, a nearest standard value was chosen: 4.7 µH. For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded. The RMS and peak inductor current can be found from Equation 13 and Equation 14.
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TPS65250 SLVSAA3C – JUNE 2010 – REVISED OCTOBER 2012 www.ti.com Bootstrap Capacitor Selection A 0.047-µF ceramic capacitor must be connected between the BST to LX pin for proper operation. It is recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have 10-V or higher voltage rating. Adjustable Current Limiting Resistor Selection The converter uses the voltage drop on the high-side MOSFET to measure the inductor current.
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TPS65250 www.ti.com SLVSAA3C – JUNE 2010 – REVISED OCTOBER 2012 3.3-V and 6.5 LDO Regulators The following ceramic capacitor (X7R/X5R) should be connected as close as possible to the described pins: • 10 µF for V7V pin 28 • 3.3 µF for V3V pin 29 Choice of Converter for Pump Operation And Sequencing Requirement Figure 42.
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TPS65250 SLVSAA3C – JUNE 2010 – REVISED OCTOBER 2012 www.ti.com Capacitance Reduction With TPS65250 Pump and Dump Circuit Table 6 shows the capacitance reduction achieved compared to the typical application where the storage capacitor is connected to the adapter supply the following formula applies. 1 C (V 2 - V 2) Dt = ¾ LOW 2 IN DET (20) Where: P = Gasp power ∆t = Gasp time, 60 ms VDET = Detection voltage (at this point is assumed input supply has disappeared), 11 V VLOW = Minimum gasp voltage, 8.
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TPS65250 www.ti.com SLVSAA3C – JUNE 2010 – REVISED OCTOBER 2012 Going through the iterative procedure, using only two 1000-µF, 25-V capacitors will allow for a gasp power in excess of 2.85 W, instead of the 6 required in the application without the pump and dump feature. Table 7. 25-V Capacitors Used in TPS65250 Pump and Dump Circuit to Support 2.85 W ECA1CM222B C (µF) P_GASP (W) COMMENT 1 1000 1.63 Too little 2 2000 3.26 About right 3 3000 4.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 17-Dec-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS65250RHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2 TPS65250RHAT VQFN RHA 40 250 180.0 16.4 6.3 6.3 1.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 17-Dec-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS65250RHAR VQFN RHA 40 2500 367.0 367.0 38.0 TPS65250RHAT VQFN RHA 40 250 210.0 185.0 35.
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