TPS65735 PMU For Active Shutter 3D Glasses Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
TPS65735 SLVSAI6 – JUNE 2011 www.ti.com Contents 1 2 3 2 .................................................................................................................. 5 1.1 Features ...................................................................................................................... 5 1.2 Description ................................................................................................................... 5 1.3 Pin Descriptions ...........................................
TPS65735 SLVSAI6 – JUNE 2011 www.ti.com List of Figures 1-1 TPS65735 Functional Block Diagram ........................................................................................... 5 1-2 TPS65735 Package Pin Assignments .......................................................................................... 7 2-1 System Power Up State Diagram .............................................................................................. 14 2-2 Push Button State Diagram .......................
TPS65735 SLVSAI6 – JUNE 2011 www.ti.com List of Tables ................................................................................................................... 1-1 Pin Descriptions 1-2 Pin Absolute Maximum Ratings .................................................................................................. 7 2-1 nCHG_STAT Functionality ...................................................................................................... 18 2-2 VLDO_SET Functionality ...............
TPS65735 SLVSAI6 – JUNE 2011 www.ti.com PMU For Active Shutter 3D Glasses Check for Samples: TPS65735 1 INTRODUCTION 1.1 Features • Linear Charger – Three Charger Phases: Pre-charge, Fast Charge, and Charge Termination – Externally Set Charge Current, Supports up to 100 mA – LED Current Sinks for Power Good and Charger Status Indication • LDO Supply for External Modules (Microcontroller, RF Module, IR Module) – LDO Continuous Output Current up to 30 mA 1 1.
TPS65735 SLVSAI6 – JUNE 2011 1.3 www.ti.com Pin Descriptions Table 1-1. Pin Descriptions PIN NAME I/O PIN NO.
TPS65735 SLVSAI6 – JUNE 2011 www.ti.com Table 1-2. Pin Absolute Maximum Ratings PIN VALUE / UNIT Input voltage range on all pins (except for VIN, BST_OUT, BST_SW, BST_FB, VLDO, LCLP, LCLN, LCRP, LCRN, AGND, DGND, and PGNDBST) with respect to AGND -0.3 V to 7.0 V VIN with respect to AGND -0.3 V to 28.0 V BST_OUT, BST_SW, LCLP, LCLN, LCRP, and LCRN with respect to PGNDBST -0.3 V to 18.0 V BST_FB with respect to PGNDBST, VLDO with respect to DGND -0.3 V to 3.6 V 1.
TPS65735 SLVSAI6 – JUNE 2011 www.ti.com 2 POWER MANAGEMENT CORE 2.1 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) SUBSYSTEM AND PARAMETER MIN NOM MAX UNIT CHARGER / POWER PATH VVIN Voltage range at charger input pin IVIN Input current at VIN pin 3.7 28 V 200 mA CVIN Capacitor on VIN pin LVIN Inductance at VIN pin VSYS Voltage range at SYS pin ISYS(OUT) Output current at SYS pin CSYS Capacitor on SYS pin 0.
TPS65735 SLVSAI6 – JUNE 2011 www.ti.com 2.3 Thermal Information TPS65735 THERMAL METRIC RSN UNITS 32 PINS θJA Junction-to-ambient thermal resistance (1) 38.9 θJCtop Junction-to-case (top) thermal resistance (2) 26.5 (3) θJB Junction-to-board thermal resistance ψJT Junction-to-top characterization parameter (4) ψJB Junction-to-board characterization parameter (5) 9.8 (6) 3.5 θJCbot (1) (2) (3) (4) (5) (6) 9.8 Junction-to-case (bottom) thermal resistance °C/W 0.
TPS65735 SLVSAI6 – JUNE 2011 www.ti.com Electrical Characteristics (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 6.4 6.6 6.8 UNIT VOVP Input over-voltage protection threshold VVIN: 5 V → 7 V VHYS-OVP Hysteresis on OVP VVIN: 11 V → 5 V VDO(VIN- VIN pin to SYS pin dropout voltage VVIN – VSYS ISYS = 150 mA (including IBAT) VVIN = 4.35 V VBAT = 3.
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TPS65735 SLVSAI6 – JUNE 2011 www.ti.com Electrical Characteristics (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER ILKG(BST_S W) Leakage into BST_SW pin (includes leakage into analog h-bridge switches) ISWLIM(BST) Boost MOSFET switch current limit VDIODE(BST Voltage across integrated boost diode during normal operation ) VREF(BST) TEST CONDITIONS MIN TYP BST_EN signal = LOW (Boost disabled) VBST_SW = 4.
TPS65735 SLVSAI6 – JUNE 2011 www.ti.com 2.6 System Operation The system must complete the power up routine before it enters normal operating mode. The specific system operation depends on the setting defined by the state of the SW_SEL pin. The details of the system operation for each configuration of the SW_SEL pin are contained in this section. 2.6.1 System Power Up Figure 2-1.
TPS65735 SLVSAI6 – JUNE 2011 2.6.2 www.ti.com System Operation Using Push Button Switch Figure 2-2.
TPS65735 SLVSAI6 – JUNE 2011 www.ti.com 2.6.3 System Operation Using Slider Switch Figure 2-3.
TPS65735 SLVSAI6 – JUNE 2011 2.7 www.ti.com Linear Charger Operation This device has an integrated Li-Ion battery charger and system power path management feature targeted at space-limited portable applications. The architecture powers the system while simultaneously and independently charging the battery. This feature reduces the number of charge and discharge cycles on the battery, allows for proper charge termination, and enables the system to run with a defective or absent battery pack.
TPS65735 SLVSAI6 – JUNE 2011 www.ti.com Figure 2-5. Battery Charge Phases In the pre-charge phase, the battery is charged with the pre-charge current that is scaled to be 10% of the fast-charge current set by the resistor connected to the ISET pin. Once the battery voltage crosses the VLOWV threshold, the battery is charged with the fast-charge current (ICHG).
TPS65735 SLVSAI6 – JUNE 2011 www.ti.com During the fast charge phase, the following events may increase the timer durations: 1. The system load current activates the DPM loop which reduces the available charging current 2. The input current is reduced because the input voltage has fallen to VIN(LOW) 3.
TPS65735 SLVSAI6 – JUNE 2011 www.ti.com 2.9 Boost Converter Operation The boost converter in this device is designed for the load of active shutter 3D glasses. This load is typically a light load where the average current is 2 mA or lower and the peak current out of a battery is limited in operation. This asynchronous boost converter operates with a minimum off time / maximum on time for the integrated low side switch, these values are specified in the electrical characteristics table of this datasheet.
TPS65735 SLVSAI6 – JUNE 2011 2.9.2 www.ti.com Boost Load Disconnect When the boost is disabled (BST_EN = LOW), the H-bridge is automatically placed into the OFF state. In the OFF state the high side H-bridge switches are open and the low side switches of the H-bridge are closed. The OFF state grounds and discharges the load, potentially prolonging the life of the LC shutters by eliminating any DC content (see Section 2.10.1 for more information regarding the H-bridge states).
TPS65735 SLVSAI6 – JUNE 2011 www.ti.com If CHARGE+ state is followed by the CHARGE- state, the voltage across the capacitor connected to the H-Bridge output terminals will be reversed. The system is automatically put into the GROUNDED state when the boost is disabled by the BST_EN pin - for more details see Section 2.6. Table 2-3. H-Bridge States from Inputs HBx2 [HBL2 & HBR2] HBx1 [HBL1 & HBR1] 0 0 OPEN 0 1 CHARGE + 1 0 CHARGE - 1 1 GROUNDED H-Bridge State Figure 2-11.
TPS65735 SLVSAI6 – JUNE 2011 www.ti.com 2.11 Power Management Core Control Various functions of the power management core can be controlled by GPIOs of an external MCU or by setting the default state by connecting these function pins to a logic high or low level on the PCB. 2.11.1 SLEEP / Power Control Pin Function The internal SLEEP signal between the power management device and the MSP430 can be used to control the power down behavior of the device.
TPS65735 SLVSAI6 – JUNE 2011 www.ti.com Table 2-4. Scaling Resistors for COMP Pin Function (VVLDO = 2.2 V) Scaling Resistors for COMP Pin Function Value RBSCL1 3.0 MΩ RBSCL2 2.36 MΩ Table 2-5. Scaling Resistors for COMP Pin Function (VVLDO = 3.0 V) Scaling Resistors for COMP Pin Function Value RBSCL1 3.0 MΩ RBSCL2 2.48 MΩ Using the designed values in Table 2-4 or Table 2-5, the voltage on the COMP pin will be: VCOMP = 0.5 × VVLDO + 300 mV.
TPS65735 SLVSAI6 – JUNE 2011 www.ti.com Figure 2-15. SWITCH, Slider Power On-Off Behavior 2.11.6 Push-Button Switch Behavior The system is powered on or off by a push-button press after a press that is greater than 32 ms. The following figures (Figure 2-16 and Figure 2-17) show the system behavior and the expected VLDO output during the normal push-button operation where the on and off press timings are the same value, tON = tOFF. Figure 2-16.
TPS65735 SLVSAI6 – JUNE 2011 www.ti.com Figure 2-17.
TPS65735 SLVSAI6 – JUNE 2011 www.ti.com 3 APPLICATION INFORMATION 3.1 Applications Schematic Figure 3-1. TPS65735 Applications Schematic 3.2 Reducing System Quiescent Current (IQ) This PMU device has been optimized for low power applications. If an even lower quiescent current is desired, the following circuit and configuration can be utilized to reduce system off / sleep quiescent current further.
TPS65735 SLVSAI6 – JUNE 2011 www.ti.com Figure 3-2. Reducing System IQ with Addition of a FET Along with this system configuration, the MCU code must be written such that the MCU sits in the lowest power state that can support an interrupt on a GPIO from a switch (slider or push button). After a valid button press or switch action, the device can begin the power on sequence and open the FET in the previous figure (Figure 3-2).
TPS65735 SLVSAI6 – JUNE 2011 www.ti.com Table 3-1. Recommended RFB1 and RFB2 Values (for IQ(FB) = 5 µA) (1) Targeted VBST_OUT RFB1 (1) RFB2 (1) 8V 1.3 MΩ 240 kΩ 10 V 1.8 MΩ 240 kΩ 12 V 2.2 MΩ 240 kΩ 14 V 2.4 MΩ 240 kΩ 16 V 3.0 MΩ 240 kΩ Resistance values given in closest standard value (5% tolerance, E24 grouping). These resistance values can also be calculated using the following information.
TPS65735 SLVSAI6 – JUNE 2011 www.ti.com Figure 3-4. Bypassing Default TPS65735 Push Button SWITCH Timing In a system where a different push-button SWITCH off timing is required, the SLEEP pin is used to control the power off of the device. After system power up, the MCU must force the SLEEP pin to a high state (VSLEEP > VIH(PMIC)). Once the SWITCH push-button is pressed to shut the system down, a timer in the MCU should be active and counting the desired tOFF time of the device.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE MATERIALS INFORMATION www.ti.com 14-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS65735RSNT Package Package Pins Type Drawing QFN RSN 32 SPQ 250 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 180.0 12.4 Pack Materials-Page 1 4.25 B0 (mm) K0 (mm) P1 (mm) 4.25 1.15 8.0 W Pin1 (mm) Quadrant 12.
PACKAGE MATERIALS INFORMATION www.ti.com 14-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS65735RSNT QFN RSN 32 250 552.0 185.0 36.
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