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TPS65910

TPS65910A

TPS65910A3

TPS659101

TPS659102

TPS659103

TPS659104

TPS659105

TPS659106, TPS659107, TPS659108, TPS659109

www.ti.com

SWCS046U –MARCH 2010–REVISED JUNE 2014

TPS65910x Integrated Power-Management Unit Top Specification

1 Device Overview

1.1 Features

• Embedded Power Controller • Two Enable Signals Multiplexed with SR-I

Configurable to Control any Supply State and

• Two Efficient Step-Down DC-DC Converters for

Processor Cores Supply Voltage

Processor Cores

• Thermal Shutdown Protection and Hot-Die

• One Efficient Step-Down DC-DC Converter for I/O

Detection

Power

• An RTC Resource with:

• One Efficient Step-Up 5-V DC-DC Converter

– Oscillator for 32.768-kHz Crystal or 32-kHz

• SmartReflex™ Compliant Dynamic Voltage

Built-in RC Oscillator

Management for Processor Cores

– Date, Time, and Calendar

• 8 LDO Voltage Regulators and One Real-Time

Clock (RTC) LDO (Internal Purpose) – Alarm Capability

• One High-Speed I

C Interface for General-Purpose • One Configurable GPIO

Control Commands (CTL-I

• DC-DC Switching Synchronization Through

• One High-Speed I

C Interface for SmartReflex Internal or External 3-MHz Clock

Class 3 Control and Command (SR-I

1.2 Applications

• Portable and Handheld Systems • OMAP™ 3 Power Management

1.3 Description

The TPS65910 device is an integrated power-management IC available in 48-QFN package and

dedicated to applications powered by one Li-Ion or Li-Ion polymer battery cell or 3-series Ni-MH cells, or

by a 5-V input; it requires multiple power rails. The device provides three step-down converters, one step-

up converter, and eight LDOs and is designed to support the specific power requirements of OMAP-based

applications.

Two of the step-down converters provide power for dual processor cores and are controllable by a

dedicated class-3 SmartReflex interface for optimum power savings. The third converter provides power

for the I/Os and memory in the system.

The device includes eight general-purpose LDOs providing a wide range of voltage and current

capabilities. The LDOs are fully controllable by the I

C interface. The use of the LDOs is flexible; they are

intended to be used as follows: Two LDOs are designated to power the PLL and video DAC supply rails

on the OMAP-based processors, four general-purpose auxiliary LDOs are available to provide power to

other devices in the system, and two LDOs are provided to power DDR memory supplies in applications

requiring these memories.

In addition to the power resources, the device contains an embedded power controller (EPC) to manage

the power sequencing requirements of the OMAP systems and an RTC.

Table 1-1. Device Information

(1)

PART NUMBER PACKAGE (PIN) BODY SIZE

TPS65910 PVQFN (48) 6.00 mm × 6.00 mm

(1) For more information, see Section 8, Mechanical Packaging and Orderable Information.

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

Summary of content (108 pages)

PAGE 1
Product Folder Sample & Buy Tools & Software Technical Documents Support & Community TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 www.ti.com SWCS046U – MARCH 2010 – REVISED JUNE 2014 TPS65910x Integrated Power-Management Unit Top Specification 1 Device Overview 1.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 SWCS046U – MARCH 2010 – REVISED JUNE 2014 1.4 www.ti.com Functional Block Diagram VBACKUP Figure 1-1 shows the top-level diagram of the device.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 www.ti.com SWCS046U – MARCH 2010 – REVISED JUNE 2014 Table of Contents 1 2 3 4 Device Overview ......................................... 1 5.20 VAUX1 and VAUX2 LDO 1.1 Features .............................................. 1 5.21 VDAC and VPLL LDO............................... 33 1.2 Applications ........................................... 1 5.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 SWCS046U – MARCH 2010 – REVISED JUNE 2014 www.ti.com 2 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 www.ti.com SWCS046U – MARCH 2010 – REVISED JUNE 2014 VERSION DATE T 09/2013 See NOTES (21) U 06/2014 See (22) (21) SWCS046T: Updated • Table 6-23, RTC_Reset_Status_Reg, Changed Reserved bits to 7:1 and changed RESET_STATUS's reset value to 0x0. • Table 6-34, VDD1_OP_REG, Changed SEL Vout to Vout = (SEL[6:0] × 12.5 mV + 0.5625 V) × G.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 SWCS046U – MARCH 2010 – REVISED JUNE 2014 www.ti.com 3 Device Comparison Table 3-1.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 www.ti.com SWCS046U – MARCH 2010 – REVISED JUNE 2014 4 Terminal Configuration and Functions 25 TESTV 26 BOOT0 27 VBACKUP 28 VCC7 29 VRRTC 30 VFB3 31 SW3 32 VFB1 33 PWRON 34 GND1 35 SW1 36 VCC1 Figure 4-1 shows the pin assignments.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 SWCS046U – MARCH 2010 – REVISED JUNE 2014 4.1 www.ti.com Signal Descriptions Table 4-1.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 www.ti.com SWCS046U – MARCH 2010 – REVISED JUNE 2014 Table 4-1.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 SWCS046U – MARCH 2010 – REVISED JUNE 2014 www.ti.com 5 Specifications Absolute Maximum Ratings (1) (2) 5.1 over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT Voltage range on pins/balls VCC1, VCC2, VCCIO, VCC3, VCC4, VCC5, VCC6, VCC7 –0.3 7 V Voltage range on pins/balls VDDIO –0.3 3.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 www.ti.com 5.3 SWCS046U – MARCH 2010 – REVISED JUNE 2014 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) Note 1: VCC7 should be connected to the highest supply that is connected to the device VCCx pin. The exception is that VCC2 and VCC4 can be higher than VCC7.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 SWCS046U – MARCH 2010 – REVISED JUNE 2014 www.ti.com Recommended Operating Conditions (continued) over operating free-air temperature range (unless otherwise noted) Note 1: VCC7 should be connected to the highest supply that is connected to the device VCCx pin. The exception is that VCC2 and VCC4 can be higher than VCC7.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 www.ti.com SWCS046U – MARCH 2010 – REVISED JUNE 2014 Recommended Operating Conditions (continued) over operating free-air temperature range (unless otherwise noted) Note 1: VCC7 should be connected to the highest supply that is connected to the device VCCx pin. The exception is that VCC2 and VCC4 can be higher than VCC7.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 SWCS046U – MARCH 2010 – REVISED JUNE 2014 5.5 www.ti.com I/O Pullup and Pulldown Characteristics (1) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT –45% 8 +45% kΩ µA SDA_SDI, SCL_SCK, SDASR_EN2, SCLSR_EN1 Programmable pullup (DFT, default inactive) Grounded, VDDIO = 1.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 www.ti.com 5.6 SWCS046U – MARCH 2010 – REVISED JUNE 2014 Digital I/O Voltage Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER MIN TYP MAX UNIT 0.3 x VCC7 V Related I/O: PWRON Low-level input voltage, VIL High-level input voltage, VIH 0.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 SWCS046U – MARCH 2010 – REVISED JUNE 2014 5.7 www.ti.com I2C Interface and Control Signals over operating free-air temperature range (unless otherwise noted) NO. PARAMETER TEST CONDITIONS MIN TYP MAX INT1 rise and fall times, CL = 5 to 35 pF 5 10 ns NRESPWRON rise and fall times, CL = 5 to 35 pF 5 10 ns 10 80 ns 3.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 www.ti.com 5.8 SWCS046U – MARCH 2010 – REVISED JUNE 2014 Power Consumption over operating free-air temperature range (unless otherwise noted) All current consumption measurements are relative to the FULL chip, all VCC inputs set to VBAT voltage. PARAMETER Device BACKUP state Device OFF state TYP MAX VBAT = 2.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 SWCS046U – MARCH 2010 – REVISED JUNE 2014 www.ti.com 5.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 www.ti.com SWCS046U – MARCH 2010 – REVISED JUNE 2014 5.12 Backup Battery Charger over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Backup battery charging current VBACKUP = 0 to 2.4 V, BBCHEN = 1 350 500 700 µA End-of-charge backup battery voltage (1) VCC7 = 3.6 V, BBSEL = 10 –3% 3.15 +3% VCC7 = 3.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 SWCS046U – MARCH 2010 – REVISED JUNE 2014 www.ti.com 5.14 VIO SMPS over operating free-air temperature range (unless otherwise noted) PARAMETER Input voltage (VCCIO and VCC7) VIN DC output voltage (VOUT) TEST CONDITIONS MIN 2.7 5.5 VOUT = 1.5 V or 1.8 V, IOUT > 800 mA 3.2 5.5 VOUT = 2.5 V, IOUT > 800 mA 4.0 5.5 VOUT = 3.3 V, IOUT > 800 mA 4.4 5.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 www.ti.com SWCS046U – MARCH 2010 – REVISED JUNE 2014 VIO SMPS (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER Ground current (IQ) TEST CONDITIONS MIN TYP Off MAX UNIT 1 PWM mode, IOUT = 0 mA, VIN = 3.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 SWCS046U – MARCH 2010 – REVISED JUNE 2014 www.ti.com 5.15 VDD1 SMPS over operating free-air temperature range (unless otherwise noted) PARAMETER Input voltage (VCC1 and VCC7) VIN TEST CONDITIONS IOUT ≤ 1200 mA VOUT = 0.6 V to 1.5 V, VGAIN_SEL = 00, IOUT > 1200 mA 2.5 V ≤ VOUT ≤ 3.3 V, VGAIN_SEL = 10 or 11, IOUT > 1200 mA DC output voltage (VOUT) MIN TYP MAX 2.7 5.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 www.ti.com SWCS046U – MARCH 2010 – REVISED JUNE 2014 VDD1 SMPS (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP Duty cycle MAX UNIT 100 Minimum on time tON(MIN) % 35 ns 1 MΩ P-channel MOSFET VFB1 internal resistance 0.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 SWCS046U – MARCH 2010 – REVISED JUNE 2014 www.ti.com 5.16 VDD2 SMPS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS Input voltage (VCC2 and VCC4) VIN IOUT ≤ 1200 mA VOUT = 0.6 V to 1.5 V, VGAIN_SEL = 00, IOUT > 1200 mA 2.5 V ≤ VOUT ≤ 3.3 V, VGAIN_SEL = 10 or 11, IOUT > 1200 mA DC output voltage (VOUT) MIN TYP 2.7 5.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 www.ti.com SWCS046U – MARCH 2010 – REVISED JUNE 2014 VDD2 SMPS (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VFB2 internal resistance Discharge resistor for power-down sequence RDIS Ground current (IQ) MIN TYP 0.5 1 30 Off PWM mode, IOUT = 0 mA, VIN = 3.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 SWCS046U – MARCH 2010 – REVISED JUNE 2014 www.ti.com 5.17 VDD3 SMPS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS Input voltage VIN MIN MAX UNIT 5.5 V 5 5.25 3 DC output voltage (VOUT) 4.65 Rated output current IOUTmax 100 N-channel MOSFET TYP VIN = 3.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 www.ti.com SWCS046U – MARCH 2010 – REVISED JUNE 2014 5.18 VDIG1 and VDIG2 LDO over operating free-air temperature range (unless otherwise noted) PARAMETER Input voltage (VCC6) VIN TEST CONDITIONS MIN TYP MAX UNIT VOUT (VDIG1) = 1.2 V at 300 mA / 1.5 V at 100 mA and VOUT (VDIG2) = 1.2 V / 1.1 V / 1.0 V at 300 mA 1.7 5.5 VOUT (VDIG1) = 1.5 V and VOUT (VDIG2) = 1.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 SWCS046U – MARCH 2010 – REVISED JUNE 2014 www.ti.com VDIG1 and VDIG2 LDO (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX SEL = 11, IOUT = 0 to IOUTmax –3% 1.8 +3% SEL = 10 IOUT = 0 to IOUTmax, VIN = VINmin to 4 V –3% 1.2 +3% SEL = 01 IOUT = 0 to 100 mA/IOUTmax, VIN= VINmin to 4 V –3% 1.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 www.ti.com SWCS046U – MARCH 2010 – REVISED JUNE 2014 5.19 VAUX33 and VMMC LDO over operating free-air temperature range (unless otherwise noted) PARAMETER Input voltage (VCC3) VIN TEST CONDITIONS MIN TYP MAX VOUT (VAUX33) = 1.8 V / 2 V and VOUT (VMMC) = 1.8 V 2.7 5.5 VOUT (VAUX33) = 2.8 V 3.2 5.5 VOUT (VAUX33) = 3.3 V 3.6 5.5 VOUT (VMMC) = 2.8 V at 200 mA 3.2 5.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 SWCS046U – MARCH 2010 – REVISED JUNE 2014 www.ti.com VAUX33 and VMMC LDO (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER Rated output current IOUTmax TEST CONDITIONS On mode Low-power mode Load current limitation (shortcircuit protection) On mode, VOUT = VOUTmin – 100 mV Dropout voltage VDO Dropout voltage VDO VIN = 3.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 www.ti.com SWCS046U – MARCH 2010 – REVISED JUNE 2014 5.20 VAUX1 and VAUX2 LDO over operating free-air temperature range (unless otherwise noted) PARAMETER Input voltage (VCC4) VIN TEST CONDITIONS MIN TYP MAX VOUT (VAUX1) = 1.8 V and VOUT (AUX2) = 1.8 V 2.7 5.5 VOUT (VAUX1) = 2.5 V 3.2 5.5 VOUT (VAUX1) = 2.8 V at Iload = 200 mA and 2.85 V at Iload = 200mA 3.2 5.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 SWCS046U – MARCH 2010 – REVISED JUNE 2014 www.ti.com VAUX1 and VAUX2 LDO (continued) over operating free-air temperature range (unless otherwise noted) TEST CONDITIONS MIN TYP Load current limitation (shortcircuit protection) PARAMETER MAX UNIT On mode, VOUT = VOUTmin – 100 mV 350 500 mA Dropout voltage VDO On mode, VOUTtyp = 2.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 www.ti.com SWCS046U – MARCH 2010 – REVISED JUNE 2014 5.21 VDAC and VPLL LDO over operating free-air temperature range (unless otherwise noted) PARAMETER Input voltage (VCC5) VIN TEST CONDITIONS MIN TYP MAX VOUT(VDAC) = 1.8 V and VOUT(VPLL) = 1.8 V / 1.1 V / 1.0 V 2.7 5.5 VOUT(VDAC) = 2.6 V and VOUT(VPLL) = 2.5 V 3.0 5.5 VOUT(VDAC) = 2.8 V / 2.85 V 3.2 5.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 SWCS046U – MARCH 2010 – REVISED JUNE 2014 www.ti.com VDAC and VPLL LDO (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX SEL = 11, IOUT = 0 to IOUTmax –3% 2.5 +3% SEL = 10, IOUT = 0 to IOUTmax, default BOOT[1:0 = 00 or 01 –3% 1.8 +3% SEL = 01, IOUT = 0 to IOUTmax –3% 1.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 www.ti.com SWCS046U – MARCH 2010 – REVISED JUNE 2014 5.22 Timing and Switching Characteristics 5.22.1 Switch-On/-Off Sequences and Timing Time slot length can be selected to be 0.5 ms or 2 ms through the EEPROM for an OFF-to-ACTIVE transition or through the value programmed in the register DEVCTRL2_REG for a SLEEP-to-ACTIVE transition. 5.22.1.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 SWCS046U – MARCH 2010 – REVISED JUNE 2014 www.ti.com Table 5-1. Fixed Boot Mode: 00 (continued) Register Bit TPS65910 Boot 00 Description Boot sequence time slot duration: TSLOT_LENGTH 0: 0.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 www.ti.com SWCS046U – MARCH 2010 – REVISED JUNE 2014 Table 5-2 lists the 00 Boot mode timing characteristics. Table 5-2.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 SWCS046U – MARCH 2010 – REVISED JUNE 2014 www.ti.com 5.22.1.2 BOOT1 = 0, BOOT0 = 1 Table 5-3 provides details about the EEPROM setting for the BOOT modes. The power-up sequence for this boot mode is provided in Figure 5-2. Table 5-3.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 www.ti.com SWCS046U – MARCH 2010 – REVISED JUNE 2014 Table 5-3.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 SWCS046U – MARCH 2010 – REVISED JUNE 2014 www.ti.com 5.22.2 Power Control Timing 5.22.2.1 Device Turn-On/Off With Rising/Falling Input Voltage Figure 5-3 shows the device turn-on/-off with rising/falling input voltage. VMBCH threshold VMBDCH threshold VMBLO threshold VMBHI threshold VBNPR threshold VCC7 VRTC 1.8V VBACKUP > VBNPR VIO 1.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 www.ti.com SWCS046U – MARCH 2010 – REVISED JUNE 2014 Figure 5-5 shows the long-press turn-off timing characteristics.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 SWCS046U – MARCH 2010 – REVISED JUNE 2014 www.ti.com 5.22.2.3 Device SLEEP State Control Figure 5-6 shows the device SLEEP state control timing characteristics. tACT2SLP tSLP2ACT SLEEP 1.8 V PWM mode 1.8 V Low-power mode 1.8 V PWM mode 1.8 V Active mode 1.8 V Low-power mode 1.8 V Active mode 3.3 V Pulse skip mode 3.3 V Low-power mode 3.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 www.ti.com SWCS046U – MARCH 2010 – REVISED JUNE 2014 5.22.2.4 Power Supplies State Control Through the SCLSR_EN1 and SDASR_EN2 Signals Figure 5-7 andFigure 5-8 show the power supplies state control through the SCLSR_EN1 and SDASR_EN2 signals timing characteristics. Switch-on sequence Switch-off sequence Device on NRESPWRON tdEN SCLSR_EN1 tdVEN VDIG1 tdEN 1.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 SWCS046U – MARCH 2010 – REVISED JUNE 2014 www.ti.com 5.22.2.5 VDD1 and VDD2 Voltage Control Through SCLSR_EN1 and SDASR_EN2 Signals Figure 5-9 shows the VDD1 and VDD2 voltage control through the SCLSR_EN1 and SDASR_EN2 signals timing characteristics. SCLSR_EN2 tdDVSEN tdDVSENL 1.2 V VDD1/VFB1 tdDVSEN tdDVSENL 0.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 www.ti.com SWCS046U – MARCH 2010 – REVISED JUNE 2014 6 Detailed Description 6.1 Power Reference The bandgap voltage reference is filtered by using an external capacitor connected across the VREF output and the analog ground REFGND (see Section 5.3, Recommended Operating Conditions). The VREF voltage is distributed and buffered inside the device. 6.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 SWCS046U – MARCH 2010 – REVISED JUNE 2014 www.ti.com Sleep: Device SLEEP enable conditions are met and some selected regulated power supplies are in lowpower mode. Figure 6-1 shows the transitions of the state-machine.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 www.ti.com SWCS046U – MARCH 2010 – REVISED JUNE 2014 Device power-on enable conditions: If none of the device power-on disable conditions is met, the following conditions are available to turn on and/or maintain the ON state of the device: • PWRON signal low level. • Or PWRHOLD signal high level. • Or DEV_ON control bit set to 1 (default inactive).
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 SWCS046U – MARCH 2010 – REVISED JUNE 2014 6.3.2 www.ti.com Switch-On/-Off Sequences The power sequence is the automated switching on of the device resources when an off-to-active transition takes place. The device supports three embedded power sequences selectable by the device BOOT pins.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 www.ti.com 6.3.3.6 SWCS046U – MARCH 2010 – REVISED JUNE 2014 PWRON A falling edge on this signal causes after tdbPWRONF debouncing delay (defined in Figure 5-4 and Table 5-5) an OFF-to-ACTIVE state or SLEEP-to-ACTIVE state transition of the device and makes the corresponding interrupt (PWRON_IT) active. The PWRON input is connected to an external push-button.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 SWCS046U – MARCH 2010 – REVISED JUNE 2014 www.ti.com When a supply is controlled through SCLSR_EN1 or SCLSR_EN2 signals, its state is no longer driven by the device SLEEP state. 6.3.3.9 GPIO_CKSYNC GPIO_CKSYNC is a configurable open-drain digital I/O: directivity, debouncing delay and internal pullup can be programmed in the GPIO0_REG register.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 www.ti.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 SWCS046U – MARCH 2010 – REVISED JUNE 2014 6.4 www.ti.com 32-kHz RTC Clock The TPS65910 device can provide a 32-kHz clock to the platform through the CLK32KOUT output, the source of this 32-kHz clock can be: • 32-kHz crystal connected from OSC32IN to OSC32KOUT pins • A square-wave 32-kHz clock signal applied to OSC32IN input (OSC32KOUT kept floating).
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 www.ti.com 6.5 SWCS046U – MARCH 2010 – REVISED JUNE 2014 RTC The RTC, which is driven by the 32-kHz clock, provides the alarm and timekeeping functions. The RTC is kept supplied when the device is in the OFF or the BACKUP state.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 SWCS046U – MARCH 2010 – REVISED JUNE 2014 6.5.1 www.ti.com Time Calendar Registers All the time and calendar information are available in these dedicated registers, called TC registers. Values of the TC registers are written in BCD format. 1. Year data ranges from 00 to 99 – Leap year = Year divisible by four (2000, 2004, 2008, 2012...) – Common year = other years 2.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 www.ti.com SWCS046U – MARCH 2010 – REVISED JUNE 2014 Hours Seconds 4 3 58 59 0 1 6 58 2 59 0 1 2 Compensation event Hours 3 Seconds 59 4 0 1 Compensation event swcs046-015 Figure 6-5. RTC Compensation Scheduling This drift can be balanced to compensate for any inaccuracy of the 32-kHz oscillator.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 SWCS046U – MARCH 2010 – REVISED JUNE 2014 6.7 www.ti.com Backup Registers As part of the RTC the device contains five 8-bit registers which can be used for storage by the application firmware when the external host is powered down. These registers retain their content as long as the VRTC is active. 6.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 www.ti.com SWCS046U – MARCH 2010 – REVISED JUNE 2014 6.10 Interrupts Table 6-2.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 SWCS046U – MARCH 2010 – REVISED JUNE 2014 www.ti.com 6.12 Functional Registers 6.12.1 TPS65910_FUNC_REG Registers Mapping Summary Table 6-3.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 www.ti.com SWCS046U – MARCH 2010 – REVISED JUNE 2014 Table 6-3.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 SWCS046U – MARCH 2010 – REVISED JUNE 2014 www.ti.com 6.12.2 TPS65910_FUNC_REG Register Descriptions Table 6-4.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 www.ti.com SWCS046U – MARCH 2010 – REVISED JUNE 2014 Table 6-7.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 SWCS046U – MARCH 2010 – REVISED JUNE 2014 www.ti.com Table 6-10.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 www.ti.com SWCS046U – MARCH 2010 – REVISED JUNE 2014 Table 6-13.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 SWCS046U – MARCH 2010 – REVISED JUNE 2014 www.ti.com Table 6-16.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 www.ti.com SWCS046U – MARCH 2010 – REVISED JUNE 2014 Table 6-18. RTC_STATUS_REG Address Offset 0x11 Physical Address Instance Description RTC status register: NOTES: A dummy read of this register is necessary before each I2C read in order to update the status register value.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 SWCS046U – MARCH 2010 – REVISED JUNE 2014 www.ti.com Bits Field Name Description 1:0 EVERY Interrupt period 00: every second 01: every minute 10: every hour 11: every day Type Reset RW 0x0 Table 6-20. RTC_COMP_LSB_REG Address Offset 0x13 Physical Address Instance Description RTC compensation register (LSB) Notes: This register must be written in 2-complement.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 www.ti.com SWCS046U – MARCH 2010 – REVISED JUNE 2014 Table 6-23. RTC_RESET_STATUS_REG Address Offset 0x16 Physical Address Instance Description RTC register for reset status Type RW 7 6 5 4 3 2 1 0 RESET_STAT US Reserved Bits Field Name Description Type Reset 7:1 Reserved Reserved bit RO R returns 0s 0x0 RW 0x0 0 RESET_STATUS Table 6-24.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 SWCS046U – MARCH 2010 – REVISED JUNE 2014 www.ti.com Table 6-26. BCK3_REG Address Offset 0x19 Physical Address Instance Description Backup register which can be used for storage by the application firmware when the external host is powered down. These registers will retain their content as long as the VRTC is active.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 www.ti.com SWCS046U – MARCH 2010 – REVISED JUNE 2014 Table 6-29. PUADEN_REG Address Offset 0x1C Physical Address Instance Description Pull-up/pull-down control register.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 SWCS046U – MARCH 2010 – REVISED JUNE 2014 www.ti.com Table 6-31.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 www.ti.com SWCS046U – MARCH 2010 – REVISED JUNE 2014 Table 6-33.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 SWCS046U – MARCH 2010 – REVISED JUNE 2014 www.ti.com Table 6-34. VDD1_OP_REG Address Offset 0x22 Physical Address Instance Description VDD1 voltage selection register. This register can be accessed by both control and smartreflex I2C interfaces depending on SR_CTL_I2C_SEL register bit value.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 www.ti.com SWCS046U – MARCH 2010 – REVISED JUNE 2014 Table 6-36.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 SWCS046U – MARCH 2010 – REVISED JUNE 2014 www.ti.com Table 6-37. VDD2_OP_REG Address Offset 0x25 Physical Address Instance Description VDD2 voltage selection register. This register can be accessed by both control and smartreflex I2C interfaces depending on SR_CTL_I2C_SEL register bit value.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 www.ti.com SWCS046U – MARCH 2010 – REVISED JUNE 2014 Table 6-39. VDD3_REG Address Offset 0x27 Physical Address Instance Description VDD2 voltage selection register for smartreflex. This register can be accessed by both control and smartreflex I2C interfaces depending on SR_CTL_I2C_SEL register bit value.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 SWCS046U – MARCH 2010 – REVISED JUNE 2014 www.ti.com Table 6-41. VDIG2_REG Address Offset 0x31 Physical Address Instance Description VDIG2 regulator control register Type RW 7 6 5 4 3 Reserved (1) 2 1 SEL 0 ST Bits Field Name Description Type Reset 7:4 Reserved Reserved bit RO R returns 0s 0x0 3:2 SEL Supply voltage (EEPROM bits): SEL[1:0] = 00 : 1.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 www.ti.com SWCS046U – MARCH 2010 – REVISED JUNE 2014 Table 6-43. VAUX2_REG Address Offset 0x33 Physical Address Instance Description VAUX2 regulator control register Type RW 7 6 5 4 3 Reserved (1) 2 1 SEL 0 ST Bits Field Name Description Type Reset 7:4 Reserved Reserved bit RO R returns 0s 0x0 3:2 SEL Supply voltage (EEPROM bits): SEL[1:0] = 00 : 1.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 SWCS046U – MARCH 2010 – REVISED JUNE 2014 www.ti.com Table 6-45. VMMC_REG Address Offset 0x35 Physical Address Instance Description VMMC regulator control register Type RW 7 6 5 4 3 Reserved (1) 2 1 SEL 0 ST Bits Field Name Description Type Reset 7:4 Reserved Reserved bit RO R returns 0s 0x0 3:2 SEL Supply voltage (EEPROM bits): SEL[1:0] = 00 : 1.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 www.ti.com SWCS046U – MARCH 2010 – REVISED JUNE 2014 Table 6-47. VDAC_REG Address Offset 0x37 Physical Address Instance Description VDAC regulator control register Type RW 7 6 5 4 3 Reserved (1) 2 1 SEL 0 ST Bits Field Name Description Type Reset 7:4 Reserved Reserved bit RO R returns 0s 0x0 3:2 SEL Supply voltage (EEPROM bits): SEL[1:0] = 00 : 1.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 SWCS046U – MARCH 2010 – REVISED JUNE 2014 www.ti.com Table 6-49.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 www.ti.com SWCS046U – MARCH 2010 – REVISED JUNE 2014 Table 6-51.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 SWCS046U – MARCH 2010 – REVISED JUNE 2014 www.ti.com Table 6-52.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 www.ti.com SWCS046U – MARCH 2010 – REVISED JUNE 2014 Table 6-53. SLEEP_KEEP_LDO_ON_REG Address Offset 0x41 Physical Address Instance Description When corresponding control bit=0 in EN1/2_ LDO_ASS register (default setting): Configuration Register keeping the full load capability of LDO regulator (ACTIVE mode) during the SLEEP state of the device.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 SWCS046U – MARCH 2010 – REVISED JUNE 2014 www.ti.com Table 6-54.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 www.ti.com SWCS046U – MARCH 2010 – REVISED JUNE 2014 Table 6-55. SLEEP_SET_LDO_OFF_REG Address Offset 0x43 Physical Address Instance Description Configuration Register turning-off LDO regulator during the SLEEP state of the device.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 SWCS046U – MARCH 2010 – REVISED JUNE 2014 www.ti.com Table 6-56. SLEEP_SET_RES_OFF_REG Address Offset 0x44 Physical Address Instance Description Configuration Register turning-off SMPS regulator during the SLEEP state of the device. Corresponding *_KEEP_ON control bit in SLEEP_KEEP_RES_ON2 register should be 0 to make this *_SET_OFF control bit effective.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 www.ti.com SWCS046U – MARCH 2010 – REVISED JUNE 2014 Table 6-57. EN1_LDO_ASS_REG Address Offset 0x45 Physical Address Instance Description Configuration Register setting the LDO regulators, driven by the multiplexed SCLSR_EN1 signal.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 SWCS046U – MARCH 2010 – REVISED JUNE 2014 www.ti.com Table 6-58. EN1_SMPS_ASS_REG Address Offset 0x46 Physical Address Instance Description Configuration Register setting the SMPS Supplies driven by the multiplexed SCLSR_EN1 signal.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 www.ti.com SWCS046U – MARCH 2010 – REVISED JUNE 2014 Table 6-59. EN2_LDO_ASS_REG Address Offset 0x47 Physical Address Instance Description Configuration Register setting the LDO regulators, driven by the multiplexed SDASR_EN2 signal.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 SWCS046U – MARCH 2010 – REVISED JUNE 2014 www.ti.com Table 6-60. EN2_SMPS_ASS_REG Address Offset 0x48 Physical Address Instance Description Configuration Register setting the SMPS Supplies driven by the multiplexed SDASR_EN2 signal.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 www.ti.com SWCS046U – MARCH 2010 – REVISED JUNE 2014 Table 6-61. RESERVED Address Offset 0x49 Physical Address Instance Description Reserved register Type RW 7 6 5 4 3 2 1 0 RESERVED Bits Field Name Description Type Reset 7:0 RESERVED Reserved bit RW 0 1 0 Table 6-62.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 SWCS046U – MARCH 2010 – REVISED JUNE 2014 www.ti.com Table 6-64. INT_MSK_REG Address Offset 0x51 Physical Address Instance Description Interrupt mask register: When *_IT_MSK is set to 1, the associated interrupt is masked: INT1 signal is not activated, but *_IT interrupt status bit is updated.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 www.ti.com SWCS046U – MARCH 2010 – REVISED JUNE 2014 Table 6-66. INT_MSK2_REG Address Offset 0x53 Physical Address Instance Description Interrupt mask register: When *_IT_MSK is set to 1, the associated interrupt is masked: INT1 signal is not activated, but *_IT interrupt status bit is updated.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 SWCS046U – MARCH 2010 – REVISED JUNE 2014 www.ti.com Table 6-68.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 www.ti.com SWCS046U – MARCH 2010 – REVISED JUNE 2014 7 Device and Documentation Support 7.1 7.1.1 Device Support Development Support TI offers an extensive line of development tools, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 SWCS046U – MARCH 2010 – REVISED JUNE 2014 www.ti.com For orderable part numbers of TPS65910x devices in the RSL package types, see the Package Option Addendum of this document, the TI website (www.ti.com), or contact your TI sales representative. 7.2 Documentation Support The following documents describe the TPS65910 device.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 www.ti.com 7.4 SWCS046U – MARCH 2010 – REVISED JUNE 2014 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 SWCS046U – MARCH 2010 – REVISED JUNE 2014 7.9 www.ti.com Additional Acronyms Additional acronyms used in this data sheet are described below.
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TPS65910, TPS65910A, TPS65910A3, TPS659101 TPS659102, TPS659103, TPS659104, TPS659105 TPS659106, TPS659107, TPS659108, TPS659109 www.ti.com SWCS046U – MARCH 2010 – REVISED JUNE 2014 8 Mechanical Packaging and Orderable Information 8.1 Packaging Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 19-Jun-2014 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
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PACKAGE MATERIALS INFORMATION www.ti.com 19-Jun-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS659101A1RSLR VQFN RSL 48 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2 TPS659102A1RSLR VQFN RSL 48 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2 TPS659102A1RSLR VQFN RSL 48 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 19-Jun-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS659101A1RSLR VQFN RSL 48 2500 367.0 367.0 38.0 TPS659102A1RSLR VQFN RSL 48 2500 367.0 367.0 38.0 TPS659102A1RSLR VQFN RSL 48 2500 367.0 367.0 38.0 TPS659106A1RSLR VQFN RSL 48 2500 367.0 367.0 38.0 TPS659108A1RSLR VQFN RSL 48 2500 367.0 367.0 38.0 TPS659109A1RSLR VQFN RSL 48 2500 367.0 367.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.