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TPS65930/TPS65920

Integrated Power Management

\Audio Codec (TPS65930 Only)

Silicon Revision 1.2

Data Manual

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Literature Number: SWCS037G

May 2008–Revised April 2011

Summary of content (117 pages)

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TPS65930/TPS65920 Integrated Power Management \Audio Codec (TPS65930 Only) Silicon Revision 1.2 Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com Contents 1 2 3 4 2 ........................................................................................................................ 9 1.1 Features .................................................................................................................... 10 1.2 TPS65920 and TPS65930 Device Block Diagrams ................................................................... 11 Terminal Description ....................
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com 5 6 7 8 9 10 11 ................................................................. ......................................................................................................................... 5.1.1 Backup Battery .................................................................................................. 5.2 EPC .......................................................................................................
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 11.1 11.2 www.ti.com Clock Features ............................................................................................................. 83 Input Clock Specifications ................................................................................................ 84 16 .................................................................................. 84 11.2.2 HFCLKIN ....................................................................
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com List of Figures 1-1 TPS65920 Block Diagram ....................................................................................................... 12 1-2 TPS65930 Block Diagram ....................................................................................................... 12 2-1 PBGA Bottom View ..............................................................................................................
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com 11-14 32KCLKOUT and HFCLKOUT Clock Stabilization Time .................................................................... 93 11-15 ........................................................................................................... I C Interface—Transmit and Receive in Slave Mode ........................................................................ I2S Interface—I2S Master ModeI ............................................
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com List of Tables 2-1 Ball Characteristics ............................................................................................................... 13 2-2 Signal Description ................................................................................................................ 17 3-1 Absolute Maximum Ratings .....................................................................................................
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com 7-10 OTG ID Electrical Characteristics .............................................................................................. 76 8-1 MADC Electrical Characteristics 8-2 8-3 9-1 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 11-12 12-1 12-2 12-3 12-4 12-5 12-6 12-7 12-8 12-9 12-10 13-1 14-1 15-1 15-2 15-3 8 ...............................................................................................
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com Integrated Power Management \Audio Codec (TPS65930 Only) Check for Samples: TPS65930/TPS65920 1 Introduction The TPS65920/TPS65930 devices are power-management ICs for OMAP™ and other mobile applications. The devices include power-management, a universal serial bus (USB) high-speed (HS) transceiver, light -emitting diode (LED) drivers, an analog-to-digital converter (ADC), a real-time clock (RTC), and embedded power control (EPC).
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 • 1.1 1 www.ti.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com 1.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com 2 Terminal Description Figure 2-1 shows the ball locations for the 139 -ball plastic ball grid array (PBGA) package. Use this array with Table 2-1 to locate signal names and ball grid numbers. 037-003 Figure 2-1. PBGA Bottom View 2.1 Ball Characteristics Table 2-1 describes the terminal characteristics and the signals multiplexed on each pin. The following list describes the table column headers: 1.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com Table 2-1. Ball Characteristics (continued) TPS65920 Ball[1] TPS65930 Ball[1] E7 E7 P2 Pin Name[2] Reference Level RL[5] L5 J7 Buffer Strength (mA)[7] GPIO1 D I/O IO_1P8 JTAG.TMS D I IO_1P8 GPIO2 D I/O IO_1P8 TEST1 D I/O IO_1P8 GPIO15 D I/O IO_1P8 TEST2 D I/O IO_1P8 GPIO6 D I/O IO_1P8 PWM0 D O IO_1P8 TEST3 D I/O IO_1P8 2 GPIO7 D I/O IO_1P8 2 VIBRA.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com Table 2-1.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com Table 2-1. Ball Characteristics (continued) TPS65920 Ball[1] TPS65930 Ball[1] G14 G14 A2 A2 B1 A/D [3] Type[4] VPLL1.OUT A Power VMMC1.IN A Power VBAT B1 VMMC1.OUT A Power VMMC1.OUT M7 M7 VINTUSB1P5. OUT A Power VINTUSB1P5.OUT N8 N8 VINTUSB1P8. OUT A Power VINTUSB1P8.OUT K1 K1 VDAC.IN A Power VBAT L2 L2 VDAC.OUT A Power VDAC.OUT H13 H13 VINT.IN A Power VBAT H1 H1 VINTANA1.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com Table 2-1. Ball Characteristics (continued) TPS65920 Ball[1] TPS65930 Ball[1] H5 H5 K5 K5 H6 A/D [3] Type[4] KPD.R1 D KPD.R2 D H6 KPD.R3 K8 K8 L8 L8 2.2 Pin Name[2] PU[6] (kΩ) PD[6] (kΩ) Reference Level RL[5] Min Typ Max I IO_1P8 8 10 12 I IO_1P8 8 10 12 D I IO_1P8 8 10 12 KPD.R4 D I IO_1P8 8 10 12 KPD.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com Table 2-2. Signal Description (continued) Signal Name Module CONTROL Description Type Open drain/I 2 IC Smart Reflex I2C TDM ANA.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com Table 2-2. Signal Description (continued) Signal Name Module VMIC BIAS Description Type MICBIAS1. OUT Analog microphone bias 1 Power VMIC1.OUT Digital microphone power supply 1 Power MICBIAS.GND Dedicated ground for microphones Power GND Default Configuration After Reset Released E2 MICBIAS1.OUT Power Floating D2 MICBIAS.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com Table 2-2. Signal Description (continued) Module TEST USB CP Signal Name Description Type Default Configuration After Reset Released TPS65920 Ball TPS65930 Ball P14 P14 TEST.RESET Signal Type Internal Pull or Not I PD Features Not Used (1) TEST.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com Table 2-2. Signal Description (continued) Module Signal Name Description Type TPS65920 Ball TPS65930 Ball Default Configuration After Reset Released Signal Internal Pull or Not Type Features Not Used (1) VDD1.IN VDD1 dc-dc input voltage Power D13 D13 VDD1.IN Power VBAT VDD1.IN VDD1 dc-dc input voltage Power D12 D12 VDD1.IN Power VBAT VDD1.IN VDD1 dc-dc input voltage Power D14 D14 VDD1.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com Table 2-2. Signal Description (continued) Module Keypad Signal Name Description Type TPS65920 Ball TPS65930 Ball Default Configuration After Reset Released Signal Type Internal Pull or Not Features Not Used (1) KPD.C0 Keypad column 0 Open drain G4 G4 KPD.C0 OD Floating KPD.C1 Keypad column 1 Open drain G3 G3 KPD.C1 OD Floating KPD.C2 Keypad column 2 Open drain E5 E5 KPD.C2 OD Floating KPD.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com 3 Electrical Characteristics 3.1 Absolute Maximum Ratings Table 3-1 lists the absolute maximum ratings. Table 3-1. Absolute Maximum Ratings Parameter Main battery supply voltage Test Conditions (1) Voltage on any input Supply represents the voltage applied to the power supply pin associated with the input Storage temperature range 3.2 Max Unit 2.1 4.5 V 0.0 1.0*Supply V –55 125 °C At 1.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com Table 3-2. VBAT Minimum Required Per VBAT Ball and Associated Maximum Current (continued) Category Internal module supplied 3.3 Pin and Module Maximum Current Specified (mA) Output Voltage (V) VBAT Minimum (V) VINTDIG (LDO) 80 1.0 / 1.2 / 1.3 / 1.5 Maximum (2.7, output voltage selected + 250 mV) VRRTC (LDO) 30 1.5 Maximum (2.7, output voltage selected + 250 mV) VBACKUP (LDO) 1 2.5 / 3.0 / 3.1 / 3.2 Maximum (2.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com Table 3-4. Digital I/O Electrical Characteristics (continued) VOL (V) VOH (V) VIL (V) VIL (V) Pin Name Max Freq (MHz) Load (pF) Rise Fall Time (ns) Output Mode Time (ns) Min Max Min Max Min Max Min Max SYSEN 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL CLKEN 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3 CLKREQ 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3 INT1 0 0.45 RL–0.45 RL 0 0.35×RL 0.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com Table 3-4. Digital I/O Electrical Characteristics (continued) VOL (V) VOH (V) VIL (V) VIL (V) Pin Name Min Max Min Max Min Max Min 0 0.45 RL–0.45 RL 0 0.35×RL 0.35×RL KPD.C0 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL KPD.C1 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL KPD.C2 0 0.45 RL–0.45 RL 0 0.35×RL KPD.C3 0 0.45 RL–0.45 RL 0 KPD.C4 0 0.45 RL–0.45 RL KPD.C5 0 0.45 RL–0.45 KPD.C6 0 0.45 KPD.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com 4 Power Module This section describes the electrical characteristics of the voltage regulators and timing characteristics of the supplies digitally controlled in the TPS65920 and TPS65930 devices . Figure 4-1 is the power provider block diagram. Main battery VPLL1.OUT VPLLA3R.IN VPLL1 VINT.IN 1.0/1.2/1.3/1.8 V 40 mA CVPLL1.OUT VMMC1.OUT CVMMC1.OUT VAUX2.OUT CVAUX2.OUT VMMC1 1.85/2.85 /3.0/3.15 V 220 mA VAUX2 1.3/1.5/1.7/1.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 4.1 www.ti.com Power Providers Table 4-1 summarizes the power providers. Table 4-1. Summary of the Power Providers Usage Type Voltage Range (V) Default Voltage Maximum Current VAUX2 External LDO 1.3, 1.5, 1.7, 1.8, 1.9, 2.0, 2.1, 2.2, 2.3, 2.4, 2.5, 2.8 1.8 V 100 mA VMMC1 External LDO 1.85, 2.85, 3.0, 3.15 3.0 V 220 mA VPLL1 External LDO 1.0, 1.2, 1.3, 1.8, 2.8, 3.0 1.8 V 40 mA VDAC External LDO 1.2, 1.3, 1.8 1.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com 4.1.1 VDD1 dc-dc Regulator 4.1.1.1 VDD1 dc-dc Regulator Characteristics The VDD1 dc-dc regulator is a stepdown dc-dc converter with a configurable output voltage. The programming of the output voltage and the characteristics of the dc-dc converter are SmartReflex-compatible. The regulator can be put in sleep mode to reduce its leakage (PFM) or in power-down mode when it is not in use.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com Table 4-3.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com Device VDD1.IN (D14) VDD1.IN (D13) VDD1.IN (D12) VDD1.SW (C11) LVDD1 VDD1.SW (C12) VDD1.SW (C13) CVDD1.OUT VDD1.GND (A12) VDD1.GND (B11) VDD1.GND (B12) 030-009 Figure 4-3. VDD1 dc-dc Application Schematic NOTE For the component values, see Table 14-1. Power Module Copyright © 2008–2011, Texas Instruments Incorporated Submit Documentation Feedback focus.ti.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 4.1.2 www.ti.com VDD2 dc-dc Regulator 4.1.2.1 VDD2 dc-dc Regulator Characteristics The VDD2 dc-dc regulator is a programmable output stepdown dc-dc converter with an internal field effect transistor (FET). Like the VDD1 regulator, the VDD2 regulator can be placed in sleep or power-down mode and is SmartReflex-compatible. The VDD2 regulator differs from VDD1 in its current load capability. Table 4-4 describes the regulator characteristics.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com See Table 2-2 for how to connect the VDD1/2 dc-dc converter when it is not in use. Figure 4-4 shows the efficiency of the VDD2 dc-dc regulator in active mode and sleep mode. VDD2 EFFICIENCY vs OUTPUT CURRENT Output voltage = 1.3 V, Vbat = 3.6 V 90 80 70 Effciency (%) 60 50 40 30 20 10 0 0.0001 0.001 0.01 0.1 1 ILOAD (A) SWCS037-019 Figure 4-4. VDD2 dc-dc Regulator Efficiency 4.1.2.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com Device VDD2.IN (M12) VDD2.IN (M13) LVDD2 VDD2.SW (N11) VDD2.SW (P11) CVDD2.OUT VDD2.GND (N12) VDD2.GND (P12) 030-010 Figure 4-5. VDD2 dc-dc Application Schematic NOTE For the component values, see Table 14-1. 34 Power Module Copyright © 2008–2011, Texas Instruments Incorporated Submit Documentation Feedback focus.ti.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com 4.1.3 VIO dc-dc Regulator 4.1.3.1 VIO dc-dc Regulator Characteristics The I/O and memory dc-dc regulator is a 600-mA stepdown dc-dc converter (internal FET) with two output voltage settings. It supplies the memories and all I/O ports in the application and is one of the first power providers to switch on in the power-up sequence.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com Figure 4-6 shows the efficiency of the VIO dc-dc regulator in active mode and sleep mode. VIO EFFICIENCY vs OUTPUT CURRENT Output voltage = 1.2 V, Vbat = 3.8 V 100 90 80 70 Effciency (%) 60 50 40 30 20 10 0 0.0001 0.001 0.01 0.1 1 ILOAD (A) SWCS037-020 Figure 4-6. VIO dc-dc Regulator Efficiency 4.1.3.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com Device VIO.IN (M2) VIO.IN (M3) VIO.SW (N4) LVIO VIO.SW (P4) CVIO.OUT VIO.GND (N3) VIO.GND (P3) 030-011 Figure 4-7. VIO dc-dc Application Schematic NOTE For the component values, see Table 14-1. Power Module Copyright © 2008–2011, Texas Instruments Incorporated Submit Documentation Feedback focus.ti.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 4.1.4 www.ti.com VDAC LDO Regulator The VDAC programmable LDO regulator is a high-PSRR, low-noise linear regulator that powers the host processor dual-video DAC. It is controllable with registers through I2C and can be powered down. Table 4-6 describes the regulator characteristics. Table 4-6. VDAC LDO Regulator Characteristics Parameter Test Conditions Min Typ 0.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com 4.1.5 VPLL1 LDO Regulator The VPLL1 programmable LDO regulator is a high-PSRR, low-noise, linear regulator used for the host processor PLL supply. Table 4-7 describes the regulator characteristics. Table 4-7. VPLL1 LDO Regulator Characteristics Parameter Test Conditions Min Typ 0.3 1 Max Unit Output Load Conditions Filtering capacitor Connected from VPLL1.OUT to analog ground Filtering capacitor ESR 20 2.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 4.1.6 www.ti.com VMMC1 LDO Regulator The VMMC1 LDO regulator is a programmable linear voltage converter that powers the multimedia card (MMC) slot. It includes a discharge resistor and overcurrent protection (short-circuit). This LDO regulator can also be turned off automatically when MMC card extraction is detected. The VMMC1 LDO can be powered through an independent supply other than the battery; for example, a charge pump.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com 4.1.7 VAUX2 LDO Regulator The VAUX2 general-purpose LDO regulator powers the auxiliary devices. Table 4-9 describes the regulator characteristics. Table 4-9. VAUX2 LDO Regulator Characteristics Parameter Test Conditions Min Typ 0.3 1 Max Unit Output Load Conditions Filtering capacitor Connected from VAUX2.OUT to analog ground Filtering capacitor ESR 20 2.7 μF 600 mΩ Electrical Characteristics VIN Input voltage 2.7 3.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 4.1.8 www.ti.com Output Load Conditions Table 4-10 lists the regulators that power the device, and the output loads associated with them. Table 4-10. Output Load Conditions Regulator VINTDIG LDO Parameter Filtering capacitor Test Conditions Connected from VINTDIG.OUT to analog ground Filtering capacitor ESR VINTANA1 LDO Filtering capacitor Filtering capacitor Connected from VINTANA1.OUT to analog ground 600 mΩ 2.7 μF 600 mΩ 2.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com 4.1.9 Charge Pump The charge pump generates a 4.8-V (nominal) power supply voltage from the battery to the VBUS pin. The input voltage range is 2.7 to 4.5 V for the battery voltage. The charge pump operating frequency is 1 MHz. The charge pump tolerates 7 V on VBUS when it is in power-down mode. The charge pump integrates a short-circuit current limitation at 450 mA. Table 4-11 lists the charge pump output load conditions. Table 4-11.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com 4.1.10 USB LDO Short-Circuit Protection Scheme The short-circuit current for the LDOs and dc-dcs in the TPS65920 and TPS65930 devices is approximately twice the maximum load current. When the output of the block is shorted to ground, the power dissipation can exceed the 1.2-W requirement if no action is taken.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com 4.2 Power References The bandgap voltage reference is filtered (resistance/capacitance [RC] filter) using an external capacitor connected across the VREF output and an analog ground (REFGND). The VREF voltage is scaled, distributed, and buffered in the device. The bandgap is started in fast mode (not filtered), and is set automatically by the power state-machine in slow mode (filtered, less noisy) when required.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com Table 4-13. Backup Battery Charger Characteristics (continued) Parameter Test Conditions Backup battery charging current End backup battery charging voltage: VBBCHGEND 4.3.2 Min Typ Max VBACKUP = 2.8 V, BBCHEN = 1, BBISEL = 00 10 25 45 Unit μA VBACKUP = 2.8 V, BBCHEN = 1, BBISEL = 01 105 150 270 μA VBACKUP = 2.8 V, BBCHEN = 1, BBISEL = 10 350 500 900 μA VBACKUP = 2.8 V, BBCHEN = 1, BBISEL = 11 0.7 1 1.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com Table 4-15.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com Table 4-17 lists the regulator states according to the mode in use. Table 4-17.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com 4.5 Power Management 4.5.1 Boot Modes Table 4-18 lists the modes corresponding to BOOT0–BOOT1. Table 4-18. BOOT Mode Description 4.5.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com Vbkup User_Action Starting_Event is main battery insertion Vbat 61 ms - 2 cycle32k Sequence_Start Starting_Event is charger insertion VAC 61 ms - 2 cycle32k Sequence_Start Starting_Event is VBUS insertion Vbus 61 ms - 2 cycle32k Sequence_Start Starting_Event is PWRON button PWRON Pushbutton debouncing - 30 ms Sequence_Start Starting_Event is PWRON rising when device is in slave mode PWRON 0 ms Sequence_Start 030-012 Figure 4-8.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com 4.5.3.2 Power-On Sequence Figure 4-9 describes the timing and control that must occur in the OMAP3 mode. Sequence_Start is a symbolic internal signal to ease the description of the power sequences. It occurs according to the events shown in Figure 4-8. Sequence_Start 4608 ms battery detection REGEN 1068 ms - 3 MHz oscillator setting + clock switch VIO 1.8 V 1179 ms for VIO stabilization VPLL1 1.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com PWRON 4791 ms – 3 MHz oscillator setting + internal reg REGEN 1068 ms for external supply ramp VIO 1.8 V 1179 ms for VIO dc-dc stablilization VPLL1 1.8 V 1022 ms VDD2 1.2 V 1099 ms for VDD2 stabilization VDD1 1.2 V 1175 ms for VDD1 stabilization 32KCLKOUT 61 ms SYSEN 1099 ms for VDD2 stabilization CLKEN 1953 ms for digital clock setting HFCLKOUT 64 ms NRESPWRON 030-022 Figure 4-10.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com 4.5.4 Power-Off Sequence This section describes the signal behavior required to power down the system. 4.5.4.1 Power-Off Sequence Figure 4-11 shows the timing and control that occur during the power-off sequence in master modes. VBAT DEVOFF(register) 18 ms NRESPWRON 1.2 ms REGEN 18 ms 32KCLKOUT 1.2 ms DCDCs 1.2 ms LDOs 18 ms SYSEN 18 ms HFCLKOUT 126 ms CLKEN 3.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 5 www.ti.com Real-Time Clock and Embedded Power Controller The TPS65930 and TPS65920 devices contain an RTC to provide clock and timekeeping functions and an EPC to provide battery supervision and control. 5.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com 6 Audio/Voice Module (TPS65930 Device Only) NOTE This section applies only to the TPS65930 device. Figure 6-1 is the audio/voice module block diagram. HFCLKIN High-speed 2 I C (Control) Audio TDM/I2S interface Main mic Bias LDOs Carkit Speak/mic Monaural auxiliary input Class-D predriver H-bridge vibrator Audio/voice module Device 037-004 Figure 6-1. Audio/Voice Module Block Diagram 6.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 6.1.1.1 www.ti.com Predriver Output Characteristics Table 6-1 lists the predriver output characteristics. Table 6-1.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com NOTE For other component values, see Table 14-1. 6.1.2 Vibrator H-Bridge A digital signal from the pulse width modulated generator is fed to the vibrator H-bridge driver. The vibrator H-bridge is a differential driver that drives vibrator motors. The differential output allows dual rotation directions. 6.1.2.1 Vibrator H-Bridge Output Characteristics Table 6-2 lists the vibrator H-bridge output characteristics. Table 6-2.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com NOTE For other component values, see Table 14-1. Example of ferrite: BLM 18BD221SN1. 6.1.3 Carkit Output The USB-CEA carkit uses the DP/DM pad to output audio signals (see the CEA-936–Mini-USB Analog Carkit specification). Figure 6-4 shows the carkit output downlink full path characteristics for audio and USB. Digital PGA gain = 0 dB 0 dBFs Amp 0 dB Analog PGA gain = 0 dB DAC USB Amp –0.6 dB 1.35 VPP 037-052 Figure 6-4.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com 6.1.4 Digital Audio Filter Module Figure 6-5 shows the digital audio filter downlink full path characteristics for the audio interface. High-pass filter Audio interface Low-pass Filter Digital modulator Randomizer DAC 037-051 Figure 6-5. Digital Audio Filter Downlink Path Characteristics The HPF can be bypassed. It is controlled by the MISC_SET_2 ARX_HPF_BYP bit set to address 0x49.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com Table 6-5. Boost Electrical Characteristics Versus FS Frequency (FS ≤ 22.05 kHz) FS = 8 kHz FS = 11.025 kHz FS = 12 kHz FS = 16 kHz FS = 22.05 kHz Frequency (Hz) 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 10 4.51 5.13 5.62 5.10 5.51 5.80 5.22 5.58 5.83 5.54 5.77 5.92 5.76 5.89 5.97 12 4.08 4.83 5.46 4.80 5.32 5.71 4.95 5.41 5.76 5.36 5.66 5.87 5.65 5.83 5.94 15.2 3.43 4.32 5.18 4.28 4.97 5.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com 6.2 Audio Uplink (TX) Module The audio uplink path includes two input amplification stages: • MIC_MAIN_P, MIC_MAIN_M (differential main handset input) • AUXR (common terminal: single-ended auxiliary) NOTE If two audio inputs are needed, and mic bias is not needed, the AUXR input can be used with MIC_MAIN to provide the two inputs. 6.2.1 Microphone Bias Module A bias generator provides an external voltage of 2.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com Figure 6-6 and Figure 6-7 show the external components and application schematics for the analog microphone. Device On board RMM.O MICBIAS1.OUT CMM.B CMM.P MIC.MAIN.P RMM.MP MIC.MAIN.M CMM.M CMM.O MICBIAS.GND 037-005 Figure 6-6. Analog Microphone Pseudodifferential NOTE For other component values, see Table 14-1. 62 Audio/Voice Module (TPS65930 Device Only) Submit Documentation Feedback focus.ti.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com ON BOARD Device RMM.BP MICBIAS1.OUT RMM.GM /2 CMM.B CMM.P MIC.MAIN.P 47pF CMM.PM Close to Device Close to Device MIC.MAIN.M CMM.M CMM.GM RMM.GM /2 CMM.GP MICBIAS.GND 037-006 Figure 6-7. Analog Microphone Differential NOTE For other component values, see Table 14-1. NOTE To improve the rejection, ensure that MICBIAS_GND is as clean as possible.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com The silicon microphone is the integration of mechanical elements and electronics on a common silicon substrate through microfabrication technology. The complementary metal oxide semiconductor (CMOS) MEMS microphone is more like an analog IC than a classical microphone, or electric condenser microphone (ECM). It is powered as an IC with a direct connection to the power supply.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com 6.2.2 FM Radio/Auxiliary Input The auxiliary input AUXR/FMR can be used as FM radio input. The amplification stage output is connected to the ADC input. The FM radio input can also be output through an audio output stage. 6.2.2.1 External Components Figure 6-9 shows the external components on the auxiliary input. On board Chip CAUXR AUXR CAUXR.M 037-008 Figure 6-9.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com Table 6-10. Uplink Characteristics (continued) Parameter Test Conditions Peak-to-peak single-ended input voltage (0 dBFs) Min Input impedance (2) Idle channel noise Crosstalk A/D to D/A Max Unit 1.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com 6.2.5 Carkit Input The USB-CEA carkit uses the DP pad to input the audio signal. Figure 6-11 shows the uplink carkit full path uplink characteristics for audio and USB. Amp CEA –1.02 dB Amp 0 to 30 dB ADC Digital PGA gain = 0 to 31 dB 037-009 Figure 6-11. Carkit Input Uplink Path Characteristics Table 6-11 lists the USB-CEA carkit audio electrical characteristics. Table 6-11.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 6.2.6 www.ti.com Digital Audio Filter Module Figure 6-12 shows the digital audio filter uplink full path characteristics for the audio interface. A/D output Error cancellation SINC filter differentiator 4th order SINC filter integrator 4th order 1st order highpass filter Low-pass filter Audio interface 037-017 Figure 6-12. Digital Audio Filter Uplink Path Characteristics The high-pass filter (HPF) can be bypassed.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com 7 USB Transceiver 7.1 USB Transceiver The TPS65920/TPS65930 device includes a USB OTG transceiver with the CEA carkit interface that supports USB 480 Mbps HS, 12 Mbps full-speed (FS), and USB 1.5 Mbps low-speed (LS) through a 4-pin ULPI. The carkit block ensures the interface between the phone and a carkit device. The TPS65920/TPS65930 USB supports the CEA carkit standard. Figure 7-1 is a block diagram of the USB 2.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 • www.ti.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com HSU0 HSU1 HSU1 UCLK HSU5 HSU4 STP HSU2 HSU2 DIR_&_NXT HSU3 HSU6 HSU3 DATA[7:0] Data_OUT HSU7 Data_IN 037-049 Figure 7-3. HS-USB Interface—Transmit and Receive Modes (ULPI 8-bit) NOTE ULPI data [7:0] lines are set to 1 after USB PHY power up, and before the clock signal is stable. The input timing requirements are given by considering a rising or falling time of 1 ns (see Table 7-1). Table 7-1.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com UART data are sent and received on the USB D+/D– pads. D+/D– are also used in this mode to carry audio I/O signals. Table 7-3 assumes testing over the recommended operating conditions (see the CEA-936A specification). Table 7-3.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com Table 7-4. USB-CEA Carkit UART Timings Notation Parameter Min Max Unit CK1 td(UART_TXH-DM) Delay time, UART_TX rising edge to DM transition 4.0 11 ns CK2 td(UART_TXL-DM) Delay time, UART_TX falling edge to DM transition 4.0 11 ns 205 234 CK3 td(DPH-UART_RX) Delay time, DP rising edge to UART_RX transition At 38.4 MHz At 19.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com Table 7-5.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com 7.1.4.3 CEA/UART Driver Table 7-7 lists the characteristics of the CEA/UART driver. Table 7-7. CEA/UART Driver Parameter Comments Min Typ Max Unit 1 μs 2.4 3.3 3.6 V 0 0.1 0.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 7.1.5.1 www.ti.com OTG VBUS Electrical Characteristics Table 7-9 lists the electrical characteristics of the OTG VBUS. Table 7-9. OTG VBUS Electrical Characteristics Parameter Comments Min Typ Max Unit 15 μs 0.5 0.6 0.7 V VBUS Wake-Up Comparator VBUS wake-up delay DELVBUS_WK_UP VBUS wake-up threshold VVBUS_WK_UP VBUS Comparators A-device session valid VA_SESS_VLD 0.8 1.1 1.4 V A-device VBUS valid VA_VBUS_VLD 4.4 4.5 4.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 8 MADC 8.1 General Description www.ti.com The TPS65920/TPS65930 device provides the MADC resource to the host processors in the system (hardware and software conversion modes). The MADC generates interrupt signals to the host processors. Interrupts are handled primarily by the MADC internal secondary interrupt handler and secondly at the upper level (outside the MADC) by the TPS65920/TPS65930 interrupt primary handler. 8.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com 8.3 Channel Voltage Input Range Table 8-2 lists the analog input voltage minimum and maximum values. Table 8-2. Analog Input Voltage Range Channel Min Typ Max Unit Prescaler ADIN0: General-purpose input 0 1.5 V No prescaler DC current source for battery identification through external resistor (10 μA typical) ADIN2: General-purpose input (1) 0 2.5 V Prescaler in the MADC to be in range 0 to >1.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com Table 8-3 is illustrated in Figure 8-1, which is a conversion sequence general timing diagram. The Busy parameter indicates that a conversion sequence is running, and the channel N result register parameter corresponds to the result register of the RT/GP selected channel.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com 9 LED Drivers 9.1 General Description Two arrays of parallel LEDs are driven (dedicated for the phone light). The parallel LEDs are supplied by VBAT, and the external resistor value is given for each LED. The TPS65920/TPS65930 device supports two open-drain LED drivers for the keypad backlight, having drain connections tolerant of the main battery voltage. Figure 9-1 is the LED driver block diagram.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 10 www.ti.com Keyboard 10.1 Keyboard Connection The keyboard is connected to the chip using: • KBR (5 :0) input pins for row lines • KBC (5 :0) output pins for column lines Figure 10-1 shows the keyboard connection. Device VCC Internal pullup Keyboard controller 6x6 Keyboard matrix kbd_r_0 kbd_r_1 kbd_r_2 kbd_r_3 kbd_r_4 kbd_r_5 kbd_c_0 kbd_c_1 kbd_c_2 kbd_c_3 kbd_c_4 kbd_c_5 037-014 Figure 10-1.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com 11 Clock Specifications The TPS65920/TPS65930 device includes several I/O clock pins. The TPS65920/TPS65930 device has two sources of high-stability clock signals: the external high-frequency clock (HFCLKIN) input and an onboard 32-kHz oscillator (an external 32-kHz signal can be provided). Figure 11-1 is the clock overview. Device OR 32KXIN OR 32KCLKOUT 32KXOUT 32 kHz OR HFCLKIN HFCLKOUT 030-002 Figure 11-1. Clock Overview 11.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com 11.2 Input Clock Specifications The clock system accepts two input clock sources: • 32-kHz crystal oscillator clock or sinusoidal/squared clock • HFCLKIN high-frequency input clock 11.2.1 Clock Source Requirements Table 11-1 lists the input clock requirements. Table 11-1. TPS65920/TPS65930 Input Clock Source Requirements Pad Clock Frequency 32KXIN 32KXOUT HFCLKIN (1) 32.768 kHz 19.2, 26, 38.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com CLKREQ pin. As a result, the TPS65920/TPS65930 device immediately sets CLKEN to 1 to warn the clock provider in the system about the clock request and starts a timer (maximum of 5.2 ms using the 32.768-kHz clock). When the timer expires, the TPS65920/TPS65930 device opens a gated clock, the timer automatically reloads the defined value, and a high-frequency output clock signal is available through the HFCLKOUT pin.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com When the external clock signal is present on the HFCLKIN ball, it is possible to use this clock instead of the internal RC oscillator and then synchronize the system on the same clock. The RC oscillator can then go to idle mode. Table 11-2 lists the input clock electrical characteristics of the HFCLKIN input clock. Table 11-2.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com 11.2.3.1 External Crystal Description Figure 11-5 shows the 32-kHz oscillator block diagram with crystal in master mode.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com Table 11-4. Crystal Electrical Characteristics (continued) Parameter Min Typ Max Unit 75 kΩ Crystal ESR (2) Crystal shunt capacitance, CO 1 pF Crystal tolerance at room temperature, 25°C –30 30 ppm Crystal tolerance versus temperature range (–40°C to 85°C) –200 200 ppm 1 μW 0.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com used if the oscillator is in bypass mode. Current control circuit and mode selection Bias generator and startup circuit Signal swing limiting circuit Y Signal shaping (1) VBATOK Square/sine wave: Vpp = VRRTC or VIO_1P8V XI XO DC level: DC Vpp/2 Internal GND (1) VBATOK Internal GND 037-041 (1) Switches close by default and open only if register access enables very-low-power mode when VBAT < 2.7 V. Figure 11-7.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com Current control circuit and mode selection Bias generator and startup circuit Signal swing limiting circuit Y Signal shaping (1) VBATOK XI (1) VBATOK XO Floating Square wave: Vpp = VIO_1P8V Internal GND Internal GND 037-040 (1) Switches close by default and open only if register access enables very-low-power mode when VBAT < 2.7 V. Figure 11-9.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com Figure 11-10 shows the 32-kHz square- or sine-wave input clock. CK0 CK1 CK1 32KX 037-038 Figure 11-10. 32-kHz Square- or Sine-Wave Input Clock 11.3 Output Clock Specifications The TPS65920/TPS65930 device provides two output clocks: • 32KCLKOUT • HFCLKOUT 11.3.1 32KCLKOUT Output Clock Figure 11-11 is the block diagram for the 32.768-kHz clock output. IO_1P8 (1.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com Table 11-9. 32KCLKOUT Output Clock Electrical Characteristics Name Parameter Description Min f Frequency CL Load capacitance VOUT Output clock voltage, depending on output reference level IO_1P8 (see Section 2) VOH Voltage output high VOL (1) Typ Max Unit 32.768 kHz 40 pF 1.8 (1) V VOUT – 0.45 VOUT V 0 0.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com Figure 11-13 shows the HFCLKOUT output clock waveform. CHO1 CHO2 CHO2 HFCLKOUT 037-036 Figure 11-13. HFCLKOUT Output Clock 11.3.3 Output Clock Stabilization Time Figure 11-14 shows the 32KCLKOUT and HFCLKOUT clock stabilization time. XIN Starting_Event Tstartup CLK32KOUTEN CLK32KOUT CLKEN Delay1 HFCLKOUTEN HFCLKOUT Delay2 NRESPWRON 037-034 NOTE: Tstartup, Delay1, and Delay2 depend on the boot mode (see Section 4.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 12 www.ti.com Timing Requirements and Switching Characteristics 12.1 Timing Parameters The timing parameter symbols used in the timing requirement and switching characteristic tables are created in accordance with JEDEC Standard 100. To shorten the symbols, some pin names and other related terminologies are abbreviated, as shown in Table 12-1. Table 12-1.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com 12.2 Target Frequencies Table 12-2 assumes testing over the recommended operating conditions. Table 12-2. TPS65920/TPS65930 Interface Target Frequencies I/O Interface SmartReflex inter-integrated circuit (I2C™) Interface Designation 2 I C General-purpose I2C USB USB JTAG Voice/Bluetooth® pulse code modulation (PCM) interface (1) (2) 1.5 V Slave HS mode 3.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com 12.3 I2C Timing The TPS65920/TPS65930 device provides two I2C HS slave interfaces (one for general-purpose and one for SmartReflex). These interfaces support standard mode (100 Kbps), fast mode (400 Kbps), and HS mode (3.4 Mbps). The general-purpose I2C module embeds four slave hard-coded addresses (ID1 = 48h, ID2 = 49h, ID3 = 4Ah, and ID4 = 4Bh). The SmartReflex I2C module uses one slave hard-coded address (ID5).
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com Table 12-4. I2C Interface—Switching Requirements (1) Notation Parameter (2) Min Max Unit Slave HS Mode I1 tw(SCLL) Pulse duration, SCL low 160 ns I2 tw(SCLH) Pulse duration, SCL high 60 ns 1.3 (3) µs 0.6 µs 4.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com 12.4.1 I2S Right- and Left-Justified Data Format Table 12-5 and Table 12-6 assume testing over the recommended operating conditions (see Figure 12-2 and Figure 12-3). Right channel Left channel I2S.SYNC I1 I2 I0 I1 I2 I2 I2S.CLK I4 I4 I3 I2S.DIN 23 22 1 22 1 I5 I2S.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com The input timing requirements in Table 12-5 are given by considering a rising or falling time of 6.5 ns. Table 12-5. I2S Interface—Timing Requirements Notation Parameter Min Max Unit Master Mode I3 tsu(DIN-CLKH) Setup time, I2S.DIN valid to I2S.CLK high2 25 ns I4 th(DIN-CLKH) Hold time, I2S.DIN valid from I2S.CLK high. 0 ns Slave Mode (1) (2) I0 tc(CLK) Cycle time, I2S.CLK (1) I1 tw(CLK) Pulse duration, I2S.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com 12.4.2 TDM Data Format Table 12-7 and Table 12-8 assume testing over the recommended operating conditions (see Figure 12-4). Channel 1 Channel 2 Channel 3 Channel 4 I2S.SYNC T0 T1 T2 T2 T1 T2 T2 I2S.CLK I2S.DIN T4 T4 T4 T4 T4 T4 T4 T4 T3 T3 T3 T3 T3 T3 T3 T3 23 22 1 T5 I2S.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com The timing requirements listed in Table 12-7 are valid on the following conditions of input slew and output load: • Rise and fall time range of inputs (SYNC, DIN) is tR/tF = 1.0 ns/6.5 ns • Capacitance load range of outputs (CLK, SYNC, DOUT) is CLoad = 1 pF/30 pF Table 12-7. TDM Interface Master Mode—Timing Requirements Notation Parameter T3 tsu(DIN-CLKH) Setup time, TDM.DIN valid to TDM.CLK high T4 th(DIN-CLKH) Hold time, TDM.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com JL1 JL2 JL2 JTAG.TCK JL3 JL4 JL5 JL6 JTAG.TDI JTAG.TMS JL7 JTAG.TDO jtag_inter_time_wcs019 Figure 12-5. JTAG Interface Timing The input timing requirements are given by considering a rising or falling edge of 7 ns. Table 12-9. JTAG Interface—Timing Requirements Notation Parameter Min Max Unit Clock JL1 tc(TCK) Cycle time, JTAG.TCK period JL2 tw(TCK) Pulse duration, JTAG.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com 13 Debouncing Time Table 13-1 lists the characteristics of debouncing. Table 13-1.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 14 www.ti.com External Components Table 14-1 lists the TPS65920/TPS65930 device external components. Table 14-1. TPS65920/TPS65930 External Components Function Component Reference Value Note Link Power Supplies Capacitor CVDD1.IN 10 μF Range ± 50% ESR min = 1 mΩ ESR max = 20 mΩ Taiyo Yuden: JMK212BJ106KD Capacitor CVDD1.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com Table 14-1. TPS65920/TPS65930 External Components (continued) Function Component Capacitor Reference CVMMC1.IN Value Note 1 μF Range: 0.3 to 2.7 μF ESR min = 20 mΩ ESR max = 600 mΩ VMMC1 Link Figure 4-1 Capacitor CVMMC1.OUT 1 μF Range: 0.3 to 2.7 μF ESR min = 20 mΩ ESR max = 600 mΩ VAUX12S Capacitor CVAUX12S.IN 1 μF Range: 0.3 to 2.7 μF ESR min = 20 mΩ ESR max = 600 mΩ Figure 4-1 VAUX2 Capacitor CVAUX2.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com Table 14-1. TPS65920/TPS65930 External Components (continued) Function MIC main (pseudo differential mode) Component Silicon MIC Auxiliary right Value CMM.M 100 nF Capacitor CMM.P 100 nF Capacitor CMM.O 47 pF Resistor RMM.O ~500 Ω Resistor RMM.MP ~1.7 kΩ Capacitor CMM.B 0 to 200 pF Capacitor CMM.M 100 nF Capacitor CMM.P 100 nF Capacitor CMM.PM 47 pF Capacitor CMM.O 47 pF CMM.GM 47 pF CMM.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com 15 TPS65920/TPS65930 Package 15.1 TPS65920/TPS65930 Standard Package Symbols Figure 15-1 shows the printed device reference. Pin 1 indicator o YMLLLLS $ 037-028 Figure 15-1. Printed Device Reference Table 15-1 lists the fields and their meanings. Table 15-1.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com 15.3 Mechanical Data Figure 15-2 is the bottom view of the TPS65920/TPS65930 mechanical package. 037-016 Figure 15-2. TPS65920/TPS65930 Mechanical Package Bottom View Figure 15-3 shows the ball size. 0.35 mm 0.41 (±0.05) mm 037-027 Figure 15-3. Ball Size 108 TPS65920/TPS65930 Package Copyright © 2008–2011, Texas Instruments Incorporated Submit Documentation Feedback focus.ti.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.com 15.4 ESD Specifications The device has built-in ESD protection to the limits specified below. It is recommended that the leads are shorted together, or the device placed in conductive foam, during storage or handling to prevent electrostatic damage.
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 16 Glossary ADC Analog-to-digital converter ALC Automatic level control ASIC Application-specific integrated circuit BGA Ball grid array BW Signal bandwidth CMOS Complementary metal oxide semiconductor CMT Cellular mobile telephone CPU Central processing unit DAC Digital-to-analog converter DBB Digital baseband DCR Data capture record DM Data manual DSP Digital signal processor DVFS Dynamic voltage and frequency scaling
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TPS65930/TPS65920 SWCS037G – MAY 2008 – REVISED APRIL 2011 www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 3-Dec-2013 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line.
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PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS65920A2ZCHR NFBGA ZCH 139 1000 330.0 24.4 10.4 10.4 2.3 16.0 24.0 Q1 TPS65930A2ZCHR NFBGA ZCH 139 1000 330.0 24.4 10.4 10.4 2.3 16.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS65920A2ZCHR NFBGA ZCH 139 1000 336.6 336.6 41.3 TPS65930A2ZCHR NFBGA ZCH 139 1000 336.6 336.6 41.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.