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TPS65950

Integrated Power Management/Audio Codec

Silicon Revision 1.2

Data Manual

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Literature Number: SWCS032E

October 2008–Revised January 2011

Summary of content (171 pages)

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TPS65950 Integrated Power Management/Audio Codec Silicon Revision 1.2 Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 www.ti.com Contents 1 2 3 4 2 ...................................................................................................................... 1.1 Features .................................................................................................................... 1.2 TPS65950 Block Diagram ................................................................................................ Terminal Description .........................
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 4.5.2.1 4.5.3 5 6 C027.0 Mode ....................................................................................... 59 4.5.2.2 C021.M Mode ...................................................................................... 59 Power-On Sequence ........................................................................................... 59 ................................................................. 59 .......................
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 www.ti.com 10 .......................................................................................... 92 .............................................................................. 93 6.2.8 Carkit Input ...................................................................................................... 93 6.2.9 Digital Audio Filter Module .................................................................................... 94 6.2.
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TPS65950 www.ti.com ...................................................................................................... ........................................................................................................................ 11.1 Keyboard Connection ................................................................................................... Clock Specifications ........................................................................................................ 12.1 Features ..
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 www.ti.com List of Figures 1-1 TPS65950 Block Diagram ....................................................................................................... 13 2-1 PBGA Bottom View .............................................................................................................. 14 4-1 Power Provider Block Diagram .................................................................................................
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 6-34 Voice Uplink Frequency Response With FS = 16 kHz (Frequency Range 6200 to 7000 Hz) .......................... 97 7-1 USB 2.0 PHY Overview ......................................................................................................... 99 7-2 USB System Application Schematic.......................................................................................... 101 7-3 MCPC UART and Handshake Mode Data Flow ..........
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 www.ti.com List of Tables 2-1 Ball Characteristics ............................................................................................................... 15 2-2 Signal Description ................................................................................................................ 20 3-1 Absolute Maximum Ratings .....................................................................................................
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 6-15 Boost Electrical Characteristics Versus FS Frequency (FS ≥ 24 kHz) ..................................................... 83 6-16 Analog Microphone Bias Module Characteristics ............................................................................ 85 6-17 Characteristics of Analog Microphone Bias Module With a Bias Resistor ................................................
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 www.ti.com 12-11 HFCLKOUT Output Clock Electrical Characteristics ....................................................................... 142 12-12 HFCLKOUT Output Clock Switching Characteristics ...................................................................... 142 13-1 Timing Parameters 13-2 TPS65950 Interface Target Frequencies ....................................................................................
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 Integrated Power Management/Audio Codec Check for Samples: TPS65950 1 Introduction The TPS65950 device is a highly integrated power-management and audio coder/decoder (codec) integrated circuit (IC) that supports the power and peripheral requirements of the OMAP™ application processors.
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TPS65950 www.ti.com • • • • • • • • 1.
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TPS65950 www.ti.com 1.2 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 TPS65950 Block Diagram Figure 1-1 is a block diagram of the TPS65950.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 2 www.ti.com Terminal Description Figure 2-1 shows the ball locations for the 209-ball plastic ball grid array (PBGA) package and is used with Table 2-1 to locate signal names and ball grid numbers. 032-088 Figure 2-1. PBGA Bottom View 2.1 Corner Balls The four corner balls (see the following list) are not usable for functional pins: • Test • TestV1 • Test.RESET • TestV2 The eight corner adjacent balls are: • RFID.EN • UART1.TXD • JTAG.
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TPS65950 www.ti.com 2.2 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 Ball Characteristics Table 2-1 describes the terminal characteristics and the signals multiplexed on each pin. The following list describes the column headings in Table 2-1: 1. Ball: Ball number(s) associated with each signal(s) 2. Pin Name: Names of all the signals that are multiplexed on each ball 3. A/D: Analog or digital signal 4.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 www.ti.com Table 2-1. Ball Characteristics (continued) Pin Name[2] Reference Level RL[5] PU[6] (kΩ) PD[6] (kΩ) Buffer Strength (mA)[10] A/D [3] Type[4] GPIO7 D I/O IO_1P8 VIBRA.SYNC D I IO_1P8 PWM1 D O IO_1P8 4 Test4 D I/O IO_1P8 2 START.
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 Table 2-1. Ball Characteristics (continued) Pin Name[2] Ball[1] A/D [3] Type[4] Reference Level RL[5] D11 VBAT.RIGHT A Power VBAT B11 IHF.RIGHT.P A O VBAT B12 IHF.RIGHT.M A O VBAT C12 GND.RIGHT A Power GND GND C11 GND.RIGHT A Power GND GND A6 EAR.P A O VINTANA2.OUT A7 EAR.M A O VINTANA2.OUT B4 HSOL A O VINTANA2.OUT PreDriv.LEFT A O VINTANA2.OUT VMID A Power VINTANA2.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 www.ti.com Table 2-1. Ball Characteristics (continued) Pin Name[2] Ball[1] A/D [3] Type[4] Reference Level RL[5] PU[6] (kΩ) PD[6] (kΩ) Min[7] Typ[8] Max[9] Min Typ Max 75 100 202 59 100 144 Buffer Strength (mA)[10] NXT D O IO_1P8 GPIO11 D I/O IO_1P8 2 DATA0 D I/O IO_1P8 16 UART4.TXD D I IO_1P8 DATA1 D I/O IO_1P8 UART4.RXD D O IO_1P8 2 DATA2 D I/O IO_1P8 16 UART4.
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 Table 2-1. Ball Characteristics (continued) Ball[1] Pin Name[2] A/D [3] Type[4] Reference Level RL[5] J2 VINTANA2.OUT A Power VINTANA2.OUT B6 VINTANA2.OUT A Power VINTANA2.OUT L16 VINTDIG.OUT A Power VINTDIG.OUT E15 VDD1.IN A Power VBAT E14 VDD1.IN A Power VBAT D14 VDD1.IN A Power VBAT D16 VDD1.SW A O VBAT D15 VDD1.SW A O VBAT C14 VDD1.SW A O VBAT E13 VDD1.FB A I C16 VDD1.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 www.ti.com Table 2-1. Ball Characteristics (continued) Pin Name[2] Ball[1] C3 C5 A2 2.3 A/D [3] Type[4] GPIO16 D I/O IO_1P8 BT.PCM.VDR D I/O IO_1P8 DIG.MIC.CLK0 D O IO_1P8 GPIO17 D I/O IO_1P8 BT.PCM.VDX D I/O IO_1P8 DIG.MIC.CLK1 D O IO_1P8 RFID.EN D O VMMC2.
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 Table 2-2. Signal Description (continued) Signal Name Module CONTROL VREF 2 IC SmartReflex I2C PCM TDM ANA.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 www.ti.com Table 2-2. Signal Description (continued) Module Hands-free Signal Name AUX input VMIC BIAS Signal Type (1) Internal Pull or Not Unused Features(2) Battery voltage input Power D10 VBAT.LEFT Power Battery voltage input Power D9 VBAT.LEFT Power VBAT IHF.LEFT.P Hands-free speaker output left (P) O B9 IHF.LEFT.P O Floating IHF.LEFT.M Hands-free speaker output left (M) VBAT O B10 IHF.LEFT.
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 Table 2-2. Signal Description (continued) Signal Name Module Type(1) Description Signal RTSO/ CLK64K.OUT/ BERCLK.OUT Ready-to-send output/ 64-kHz output clock/ Bit error ratio (BER) clock out in test mode ADCIN5 GP ADC input 5 Clear-to-send input/ BERDATAOUT in test mode ADCIN3 GP ADC input 3 MCPC ULPI OD/ CMOS/ I/O I GP ADC input 4 I RXAF USB PHY Internal Pull or Not Unused Features(2) N11 RTSO/ CLK64K.OUT/ BERCLK.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 www.ti.com Table 2-2. Signal Description (continued) Signal Name Module Test USB CP Type(1) Description Configuration By Default After Reset Released Ball Signal Test.RESET Reset T2 device (except power state-machine) TestV1 Analog test TestV2 Analog test I Type (1) Test.
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 Table 2-2. Signal Description (continued) Module Signal Name Type(1) Description Ball Configuration By Default After Reset Released Signal Type (1) Internal Pull or Not Unused Features(2) VDD1.IN VDD1 dc-dc input voltage Power E15 VDD1.IN Power VBAT VDD1.IN VDD1 dc-dc input voltage Power E14 VDD1.IN Power VBAT VDD1.IN VDD1 dc-dc input voltage Power D14 VDD1.IN Power VBAT VDD1.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 www.ti.com Table 2-2. Signal Description (continued) Module Keypad Bluetooth/ digital microphone RFID Signal Name Type(1) Description Ball Configuration By Default After Reset Released Signal Type (1) Internal Pull or Not Unused Features(2) KPD.C0 Keypad column 0 OD G8 KPD.C0 OD Floating KPD.C1 Keypad column 1 OD H7 KPD.C1 OD Floating KPD.C2 Keypad column 2 OD G6 KPD.C2 OD Floating KPD.
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 3 Electrical Characteristics 3.1 Absolute Maximum Ratings Table 3-1 lists the absolute maximum ratings. Table 3-1. Absolute Maximum Ratings Parameter Main battery supply voltage Test Conditions Min (1) Voltage on any input Where supply represents the voltage applied to the power supply pin associated with the input Storage temperature range Ambient temperature range Junction temperature (TJ) 3.2 Max Unit 2.1 4.5 V 0.0 1.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 www.ti.com Table 3-2. VBAT Min Required Per VBAT Ball and Associated Maximum Current (continued) Category Internal module supplied Pin and Module Maximum Current Specified (mA) Output Voltage (V) VBAT Minimum (V) VAUX1 (LDO) 200 1.5 / 1.8 / 2.5 / 2.8 / 3.0 Maximum (2.7, output voltage selected + 250 mV) VAUX2 (LDO) 100 1.3 / 1.5 / 1.6 / 1.7 / 1.8 / 1.9 / 2.0 / 2.1 / 2.2 / 2.3 / 2.4 / 2.5 / 2.8 Maximum (2.
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 Table 3-4. Digital I/O Electrical Characteristics VOL (V) VOH (V) VIL (V) VIH (V) Min Max Min Max Min Max Min Max Max Freq (MHz) 0 0.45 RL–0.45 RL 0 0.35xRL 0.65xRL RL 33 30 5.2 5.2 0 0.45 RL–0.45 RL 0 0.35xRL 0.65xRL RL 33 30 5.2 5.2 0 0.45 RL–0.45 RL 0 0.35xRL 0.65xRL RL 3 30 5.2 5.2 0 0.45 RL–0.45 RL 0 0.35xRL 0.65xRL RL 3 30 5.2 5.2 0 0.45 RL–0.45 RL 0 0.35xRL 0.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 www.ti.com Table 3-4. Digital I/O Electrical Characteristics (continued) VOL (V) VOH (V) VIL (V) VIH (V) Min Max Min Max Min Max Min Max Max Freq (MHz) 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 60 10 1.0 1.0 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 30 10 1.0 1.0 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 30 10 1.0 1.0 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 30 10 1.0 1.0 0 0.45 RL–0.45 RL 0 0.
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TPS65950 www.ti.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 4 www.ti.com Power Module This section describes the electrical characteristics of the voltage regulators and timing characteristics of the supplies digitally controlled in the TPS65950. Figure 4-1 is a block diagram of the power provider.
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 Main battery VPLL1.OUT VPLLA3R.IN VPLL1 VINT.IN 1.0/1.2/1.3/1.8 V 40 mA CVPLL1.OUT VPLL2 VPLL2.OUT 0.7/1.0/1.2/1.3/1.5/1.8/1.85 VPLLA3R.IN VDAC.IN /2.5/2.6/2.8/2.85/3.0/3.15 V 100 mA CVPLL2.OUT VMMC1.OUT CVMMC1.OUT VMMC2.OUT CVMMC2.OUT VAUX1.OUT VMMC1 1.85/2.85 /3.0/3.15 V 220 mA VMMC2 1.0/1.2/1.3/1.5/1.8/1.85/ 2.5/2.6/2.8/2.85 /3.0/3.15 V 100 mA VAUX1 VMMC1.IN VDAC.IN VMMC2.IN VDAC.IN VAUX2.OUT CVAUX2.OUT VAUX3.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 4.1 www.ti.com Power Providers Table 4-1 lists the power providers. Table 4-1. Summary of the Power Providers Name Use Type VAUX1 External LDO VAUX2 External LDO VAUX3 External LDO VAUX4 External LDO VMMC1 External VMMC2 External VPLL1 External Voltage Range (V) Default Voltage Depending on Boot Mode (1) Maximum Current OMAP2 Mode OMAP3 Mode 1.5, 1.8, 2.5, 2.8, 3.0 3.0 V 3.0 V 200 mA 1.3, 1.5, 1.7, 1.8, 1.9, 2.0, 2.
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TPS65950 www.ti.com 4.1.1 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 VDD1 dc-dc Regulator 4.1.1.1 VDD1 dc-dc Regulator Characteristics The VDD1 dc-dc regulator is a stepdown dc-dc converter with a configurable output voltage. The programming of the output voltage and the characteristics of the dc-dc converter are SmartReflex-compatible. The regulator can be put in sleep mode to reduce its leakage (PFM) or power-down mode when it is not being used.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 www.ti.com Table 4-3. VDD1 dc-dc Regulator Characteristics (continued) Parameter Comments Min Typ Max Unit 0.7 1 1.3 μH 0.1 Ω Value DCR External coil External capacitor (1) Saturation current for TPS65950A2 1.8 Saturation current for TPS65950A3 2.1 Value 8 Equivalent series resistance (ESR) at switching frequency 0 A 10 12 μF 20 mΩ See Table 2-2 for how to connect the VDD1/2 dc-dc converter when it is not used.
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 Device VDD1.IN (D14) VDD1.IN (E14) VDD1.IN (E15) VDD1.SW (C14) LVDD1 VDD1.SW (D15) VDD1.SW (D16) CVDD1.OUT VDD1.GND (B15) VDD1.GND (C15) VDD1.GND (C16) 032-005 Figure 4-3. VDD1 dc-dc Application Schematic NOTE For the component values, see Table 15-1.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 4.1.2 www.ti.com VDD2 dc-dc Regulator 4.1.2.1 VDD2 dc-dc Regulator Characteristics The VDD2 dc-dc regulator is a programmable output stepdown dc-dc converter with an internal field effect transistor (FET). Like the VDD1 regulator, the VDD2 regulator can be placed in sleep or power-down mode and is SmartReflex-compatible. The VDD2 regulator differs from VDD1 in its current load capability. Table 4-4 lists the characteristics of the regulator.
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 See Table 2-2 for how to connect the VDD2 dc-dc converter when it is not used. Figure 4-4 shows the efficiency of the VDD2 dc-dc regulator in active and sleep modes. Output voltage = 1.3 V, VBAT = 3.6 V 90 80 70 Effciency (%) 60 50 40 30 20 10 0 0.0001 0.001 0.01 0.1 1 Iload (A) 032-006 Figure 4-4. VDD2 dc-dc Regulator Efficiency 4.1.2.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 www.ti.com Device VDD2.IN (D13) VDD2.IN (P14) LVDD2 VDD2.SW (T13) VDD2.SW (R14) CVDD2.OUT VDD2.GND (T14) VDD2.GND (R15) 032-007 Figure 4-5. VDD2 dc-dc Application Schematic NOTE For the component values, see Table 15-1.
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TPS65950 www.ti.com 4.1.3 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 VIO dc-dc Regulator 4.1.3.1 VIO dc-dc Regulator Characteristics The I/Os and memory dc-dc regulator is a 600-mA stepdown dc-dc converter (internal FET) with two output voltage settings. It supplies the memories and all I/O ports in the application and is one of the first power providers to switch on in the power-up sequence.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 www.ti.com Figure 4-6 shows the efficiency of the VIO dc-dc regulator in active and sleep modes. Output voltage = 1.2 V, VBAT = 3.8 V 100 90 80 70 Effciency (%) 60 50 40 30 20 10 0 0.0001 0.001 0.01 0.1 1 Iload (A) 032-008 Figure 4-6. VIO dc-dc Regulator Efficiency in Active Mode 4.1.3.2 External Components and Application Schematic Figure 4-7 is an application schematic with the external components of the VIO dc-dc regulator.
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 Device VIO.IN (R4) VIO.IN (P3) VIO.SW (R3) LVIO VIO.SW (T4) CVIO.OUT VIO.GND (R2) VIO.GND (T3) 032-009 Figure 4-7. VIO dc-dc Application Schematic NOTE For the component values, see Table 15-1.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 4.1.4 www.ti.com VDAC LDO Regulator The VDAC programmable LDO regulator is a high power-supply ripple rejection (PSRR), low-noise, linear regulator that powers the host processor dual-video DAC. It is controllable with registers through I2C and can be powered down. Table 4-6 lists the characteristics of the regulator. Table 4-6. VDAC LDO Regulator Characteristics Parameter Test Conditions Min Typ 0.
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TPS65950 www.ti.com 4.1.5 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 VPLL1 LDO Regulator The VPLL1 programmable LDO regulator is high-PSRR, low-noise, linear regulator used for the host processor phase-locked loop (PLL) supply. Table 4-7 lists the characteristics of the regulator. Table 4-7. VPLL1 LDO Regulator Characteristics Parameter Test Conditions Min Typ 0.3 1 Max Unit Output Load Conditions Filtering capacitor Connected from VPLL1.OUT to analog ground Filtering capacitor ESR 20 2.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 4.1.6 www.ti.com VPLL2 LDO Regulator The VPLL2 programmable LDO regulator is a high-PSRR, low-noise, linear regulator used for the host processor PLL supply. Table 4-8 lists the characteristics of the regulator. Table 4-8. VPLL2 LDO Regulator Characteristics Parameter Test Conditions Min Typ 0.3 1 Max Unit Output Load Conditions Filtering capacitor Connected from VPLL2.OUT to analog ground Filtering capacitor ESR 20 2.
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TPS65950 www.ti.com 4.1.7 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 VMMC1 LDO Regulator The VMMC1 LDO regulator is a programmable linear voltage converter that powers the multimedia channel (MMC) slot. It includes a discharge resistor and overcurrent (short -ircuit) protection. This LDO regulator can also be turned off automatically when MMC card extraction is detected. The VMMC1 LDO can be powered through an independent supply other than the battery; for example, a charge pump (CP).
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 4.1.8 www.ti.com VMMC2 LDO Regulator The VMMC2 LDO regulator is a programmable linear voltage converter that powers MMC slot 2. It includes a discharge resistor and overcurrent (short-circuit) protection. The VMMC2 LDO can be powered through an independent supply other than the battery (for example, a CP). In this case, the input from the VMMC2 LDO can be higher than the battery voltage. Table 4-10 lists the characteristics of the regulator.
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TPS65950 www.ti.com 4.1.9 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 VSIM LDO Regulator The VSIM voltage regulator is a programmable, low-dropout, linear voltage regulator that supplies the subscriber identity module (SIM)-card and the SIM-card driver. This LDO regulator can be turned off automatically when SIM card extraction is detected. Table 4-11 lists the characteristics of the regulator. Table 4-11. VSIM LDO Regulator Characteristics Parameter Test Conditions Min Typ 0.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 www.ti.com 4.1.10 VAUX1 LDO Regulator The VAUX1 GP LDO regulator powers the auxiliary devices. The VAUX1 regulator can also support an inductive load such as a vibrator. While operating in vibrator mode, the VAUX1 LDO has the following features: • Programmable, register-controlled, soft-start function • Enabled through the VIBRA.
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 4.1.11 VAUX2 LDO Regulator The VAUX2 GP LDO regulator powers the auxiliary devices. Table 4-13 lists the characteristics of the regulator. Table 4-13. VAUX2 LDO Regulator Characteristics Parameter Test Conditions Min Typ 0.3 1 Max Unit Output Load Conditions Filtering capacitor Connected from VAUX2.OUT to analog ground Filtering capacitor ESR 20 2.7 μF 600 mΩ Electrical Characteristics VIN Input voltage 2.7 3.6 4.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 www.ti.com 4.1.12 VAUX3 LDO Regulator The VAUX3 GP LDO regulator powers the auxiliary devices. Table 4-14 lists the characteristics of the regulator. Table 4-14. VAUX3 LDO Regulator Characteristics Parameter Test Conditions Min Typ 0.3 1 Max Unit Output Load Conditions Filtering capacitor Connected from VAUX3.OUT to analog ground Filtering capacitor ESR 20 2.7 μF 600 mΩ Electrical Characteristics VIN Input voltage 2.7 3.6 4.
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 4.1.13 VAUX4 LDO Regulator The VAUX4 GP LDO regulator powers the auxiliary devices. The VAUX4 regulator has an independent supply input pin and can be preregulated by an external voltage. Table 4-15 lists the characteristics of the regulator. Table 4-15. VAUX4 LDO Regulator Characteristics Parameter Test Conditions Min Typ 0.3 1 Max Unit Output Load Conditions Filtering capacitor Connected from VAUX4.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 www.ti.com 4.1.14 Internal LDOs Table 4-16 lists the regulators that power the device, and the output loads associated with them. Table 4-16. Output Load Conditions Regulator VINTDIG LDO Parameter Test Conditions Filtering capacitor Connected from VINTDIG.OUT to analog ground Filtering capacitor ESR VINTANA1 LDO Filtering capacitor Connected from VINTANA1.OUT to analog ground Filtering capacitor μF 600 mΩ 2.7 μF 600 mΩ 2.7 μF 0.
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 4.1.16 USB LDO Short-Circuit Protection Scheme The short-circuit current for the LDOs and dc-dc converters in TPS65950 is approximately twice the maximum load current. In certain cases when the output of the block is shorted to ground, the power dissipation can exceed the 1.2-W requirement if no action is taken.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 4.3 www.ti.com Power Control 4.3.1 Backup Battery Charger If the backup battery is rechargeable, it can be recharged from the main battery. A programmable voltage regulator powered by the main battery allows recharging of the backup battery. The backup battery charge must be enabled using a control bit register. Recharging starts when two conditions are met: • Main battery voltage > backup battery voltage • Main battery > 3.
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TPS65950 www.ti.com 4.3.3 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 VRRTC LDO Regulator The VRRTC voltage regulator is a programmable, low dropout, linear voltage regulator supplying (1.5 V) the embedded real-time clock (32.768-kHz oscillator) and dedicated I/Os of the digital host counterpart. The VRRTC regulator is also the supply voltage of the power-management digital state-machine.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 4.4 www.ti.com Power Consumption Table 4-22 describes the power consumption, depending on the use cases. NOTE Typical power consumption is obtained in nominal operating conditions with the TPS65950 in stand-alone mode. Table 4-22. Power Consumption Mode Description Typical Consumption Backup Only the RTC date is maintained with a couple of registers in the backup domain. No main source is connected. Consumption is on the backup battery.
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TPS65950 www.ti.com 4.5 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 Power Management 4.5.1 Boot Modes The modes corresponding to the BOOT0–BOOT1 combination value are listed in Table 4-24. Table 4-24. BOOT Mode Description 4.5.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 www.ti.com Vbkup User_Action Starting_Event is main battery insertion Vbat 61 ms - 2 cycle32k Sequence_Start Starting_Event is charger insertion VAC 61 ms - 2 cycle32k Sequence_Start Starting_Event is VBUS insertion Vbus 61 ms - 2 cycle32k Sequence_Start Starting_Event is PWRON button PWRON Pushbutton debouncing - 30 ms Sequence_Start Starting_Event is PWRON rising when device is in slave mode PWRON 0 ms Sequence_Start 032-010 Figure 4-8.
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 Sequence_Start 4638 ms battery detection REGEN 1068 ms - 3 MHz oscillator setting + clock switch VIO 1.8 V 1072 ms for VIO stabilization VDD1 1.3 V 1007 ms for VDD1 stabilization VDD2 1.3 V 1052 ms for VDD2 stabilization VPLL1 1.3 V 122 ms for LDO stabilization 32KCLKOUT 610 ms SYSEN 2034 ms for DcDc I/O stabilization CLKEN 3418 ms 5.2 ms HFCLKOUT 61 ms NRESPWRON 032-011 Figure 4-9. Timings—OMAP2 Power-On Sequence 4.5.3.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 www.ti.com Sequence_Start 4608 ms battery detection REGEN 1068 ms - 3 MHz oscillator setting + clock switch VIO 1.8 V 1179 ms for VIO stabilization VPLL1 1.8 V 1022 ms for LDO stabilization and start DcDc ramping VDD2 1.2 V 1099 ms for VDD2 stabilization and VDD1 start ramping VDD1 1.2 V 1175 ms for VDD1 stabilization 32KCLKOUT 61 ms SYSEN 1179 ms for VIO stabilization CLKEN 1953 ms ~ 5.3 ms HFCLKOUT 61 ms NRESPWRON 032-012 Figure 4-10.
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TPS65950 www.ti.com 4.5.3.4 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 Power On in Slave_C021_Generic Mode Figure 4-11 describes the timing and control that must occur in the Slave_C021_Generic mode. Sequence_Start is a symbolic internal signal to ease the description of the power sequences and occurs according to the different events detailed in Figure 4-8. PWRON 4791 ms – 3 MHz oscillator setting + internal reg REGEN 1068 ms for external supply ramp VIO 1.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 www.ti.com VBAT DEVOFF(register) 18 ms NRESPWRON 1.2 ms REGEN 18 ms 32KCLKOUT 1.2 ms DCDCs 1.2 ms LDOs 18 ms SYSEN 18 ms HFCLKOUT 126 ms CLKEN 3.42 ms before detection of starting event NEXT_Startup_event 032-013 NOTE: All timings are typical values with the default setup (depending on the resynchronization between power domains, state machinery priority, etc.). Figure 4-12. Power-Off Sequence in Master Modes If the value of the HF clock is not 19.
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TPS65950 www.ti.com 5 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 Real-Time Clock and Embedded Power Controller The TPS65950 device contains an RTC to provide clock and timekeeping functions and an EPC to provide battery supervision and control. 5.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 6 www.ti.com Audio/Voice Module The audio codec in the device includes five DACs and two ADCs to provide multiple voice channels and stereo downlink channels that can support all standard audio sample rates through I2S/TDM format interfaces. The audio output stages on the device include stereo headset amplifiers, two integrated class-D amplifiers providing stereo differential outputs, predrivers for line outputs, and an earpiece amplifier.
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TPS65950 www.ti.com 6.1 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 Audio/Voice Downlink (RX) Module The audio/voice module includes the following output stages: • Mono/stereo single-ended headset amplifier • Stereo differential integrated class-D 8-Ω hands-free amplifiers • Predriver output signals for external class-D amplifiers (single-ended) • Mono differential earpiece amplifier • Vibrator H-bridge 6.1.1 Earphone Output 6.1.1.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 6.1.1.2 www.ti.com External Components and Application Schematic Figure 6-3 is a simplified schematic of the earphone speaker. Chip On Board EARP CEAR 32 W EARM 032-016 Figure 6-3. Earphone Speaker NOTE For the component values, see Table 15-1. 6.1.2 8-Ω Stereo Hands-Free The digital signal from the audio and/or voice interface is fed to two class-D amplifiers.
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 Table 6-2. 8-Ω Stereo Hands-Free Output Characteristics (continued) Parameter Test Conditions Gain range (1) Max Unit Audio path –75.6 34.4 dB Voice path –49.6 34.4 Absolute gain error Min Typ –1 Maximum output power (load impedance = 8 Ω) Peak-to-peak differential output voltage Total harmonic distortion (load impedance = 8 Ω, gain setting = 0 dB) (VBAT > 3.6 V) 1 VBAT > 3.6 V 400 VBAT > 4.0 V 700 VBAT > 3.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 www.ti.com On board Chip VBAT VBAT.RIGHT/LEFT CHFR/CHFL Ferrite chip bead IHF.RIGHT/LEFT.P LHFR.P/LHFL.P CHFR.P/CHFL.P 8W Ferrite chip bead IHF.RIGHT/LEFT.M LHFR.M/LHFL.M CHFR.M/CHFL.M GND.RIGHT/LEFT 032-018 Figure 6-5. 8-Ω Stereo Hands-Free NOTE For the component values, see Table 15-1. For ferrite bead, choose one with high impedance at high frequencies, but with very low impedance at low frequencies.
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 Table 6-3. Headset Output Characteristics (continued) Parameter Gain range Test Conditions (1) Min Typ 100 100 Max pF Audio path –92 30 Voice path –66 30 –1 1 Absolute gain error Maximum output power At 0.53 Vrms differential output voltage Load impedance = 16 Ω Peak-to-peak output voltage (0 dBFs) Default gain (2) Unit dB dB 17.56 mW 1.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 6.1.3.2 www.ti.com External Components and Application Schematic Figure 6-7 is a schematic of a headset 4-wire stereo jack without an external FET. Table 6-4 lists the output characteristics of this configuration. On board Chip 4-wire stereo jack Rsb Rb VHSMIC .OUT CHM.P HSMIC.P Cb CHM.O CHM.M HSMIC.M Rs Cs HSOL Rl Cl Cs Rs Rl HSOR Cl 032-20 Figure 6-7. Headset 4-Wire Stereo Jack Without an External FET Table 6-4.
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 NOTE For other component values, see Table 15-1. Table 6-5 is a schematic of a headset 4-wire stereo jack with an external FET. Table 6-5 lists the output characteristics of this configuration. On board Chip 4-wire stereo jack Rsb Rb VHSMIC .OUT CHM.P HSMIC .P CHM.O Cb CHM.M HSMIC .M Rs Cs HSOL Rl Cl Cs Rs Rl HSOR GPIO_6 ( MUTE ) Cl External FET 032-021 Figure 6-8. Headset 4-Wire Stereo Jack With an External FET Table 6-5.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 www.ti.com NOTE For other component values, see Table 15-1. Figure 6-9 is a schematic of a headset 5-wire stereo jack. Table 6-6 lists the output characteristics of this configuration. On board Chip 5-wire stereo jack Rsb VHSMIC.OUT Rb CHM.P HSMIC.P Cb CHM.O CHM.M HSMIC.M Rs HSOL Rl HSOVMID Cl Rs Rl HSOR Cl CHM.O 032-022 Figure 6-9. Headset 5-Wire Stereo Jack Table 6-6.
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 NOTE For other component values, see Table 15-1. Figure 6-10 is a schematic of a headset 4-wire stereo jack optimized. On board Chip 4-wire stereo jack Rsb VHSMIC.OUT Rb CHM.P HSMIC Cb CHM.O CHM.M HSMIC.M mA + Cs Rs Rl HSOL Ampli_HS – mA mA Cl Rl + – Cs Rs HSOR Ampli_HS Gain = –1 Cl 032-023 Figure 6-10. Headset 4-Wire Stereo Jack Optimized NOTE For other component values, see Table 15-1. 6.1.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 www.ti.com HSO HSO MUTE RAMP_DELAY Application mode RAMP_DELAY EXTMUTE VMID_EN HSR/L_GAIN(1:0) RAMP_EN V VMID dV/dt 0 t 0 t 0 t 032-024 Figure 6-11. Headset Pop-Noise Cancellation Diagram Table 6-7. Headset Pop-Noise Characteristics Parameter Test Conditions dv/dt Ramp of charge or discharge Pop-noise (A-weighted) ac-coupling capacitor = 47 μF Serial resistor = 33 Ω External FET: Rdson = 0.12 Ω 6.1.
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 Table 6-8. Predriver Output Characteristics Parameter Test Conditions Load impedance Min Typ Max Unit 10 kΩ 50 Gain range (1) pF Audio path –92 30 Voice path –66 30 Absolute gain error –1 1 (2) Peak-to-peak output voltage (0 dBFs) Default gain Total harmonic distortion At 0 dBFs –80 –75 At –6 dBFs –74 –69 At –20 dBFs –70 –65 At –60 dBFs –30 –25 –90 –85 Default gain (2) Load > 10 kΩ // 50 pF 1.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 www.ti.com NOTE For other component values, see Table 15-1. 6.1.6 Vibrator H-Bridge A digital signal from the pulse width modulated generator is fed to the vibrator H-bridge driver. The vibrator H-bridge is a differential driver that drives vibrator motors. The differential output allows dual rotation directions. 6.1.6.1 Vibrator H-Bridge Output Characteristics Table 6-9 lists the output characteristics of the vibrator H-bridge. Table 6-9.
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 NOTE For other component values, see Table 15-1. Example of ferrite: BLM 18BD221SN1. 6.1.7 Carkit Output The USB-CEA carkit uses the DP/DM pad to output audio signals (see the CEA-936A: Mini-USB Analog Carkit Interface Specification). The MCPC carkit uses the RXAF analog pad to output audio signals. Figure 6-14 shows the carkit output downlink full path characteristics for audio and USB.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 www.ti.com Table 6-10. MCPC and USB-CEA Carkit Audio Downlink Electrical Characteristics (continued) Parameter Conditions Phone speaker amplifier output impedance at 1 kHz 6.1.8 Max Unit USB-CEA (DP/DM) Min Typ 200 Ω MCPC (RXAF) 200 Digital Audio Filter Module Figure 6-15 shows the digital audio filter downlink full path characteristics of the audio interface.
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TPS65950 www.ti.com 6.1.9.1 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 Voice Downlink Filter (Sampling Frequency at 8 kHz) Figure 6-17 shows the voice downlink frequency response with FS = 8 kHz. Table 6-12 lists the voice filter frequency responses relative to the reference gain at 1 kHz with FS = 8 kHz. Voice Downlink (RX) Filter 8 kHz 2 1.5 1 Gain (dB) 0.5 Rx_8K_1st_HPF Specification Rx_8K_3rd_HPF 0 –0.5 –1 –1.5 –2 –2.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 6.1.9.2 www.ti.com Voice Downlink Filter (Sampling Frequency at 16 kHz) Figure 6-18 shows the voice downlink frequency response with FS = 16 kHz. Table 6-13 lists the voice filter frequency responses relative to the reference gain at 1 kHz with FS = 16 kHz. Voice Downlink (RX) Filter 16 kHz 2 1.5 1 Gain (dB) 0.5 0 Rx_8K_1st_HPF Rx_8K_3rd_HPF Specification –0.5 –1 –1.5 –2 –2.
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 Table 6-14. Boost Electrical Characteristics Versus FS Frequency (FS ≤ 22.05 kHz) FS = 8 kHz FS = 11.025 kHz FS = 12 kHz FS = 16 kHz FS = 22.05 kHz Frequency (Hz) 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 10 4.51 5.13 5.62 5.10 5.51 5.80 5.22 5.58 5.83 5.54 5.77 5.92 5.76 5.89 5.97 12 4.08 4.83 5.46 4.80 5.32 5.71 4.95 5.41 5.76 5.36 5.66 5.87 5.65 5.83 5.94 15.2 3.43 4.32 5.18 4.28 4.97 5.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 6.2 www.ti.
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 Dig Mic Bia LDO PWDNZ MICBIAS2 1.8 V Analog microphone or digital microphone PWDN Analog Mic Bias Dig Mic Bia LDO PWDNZ 2 .2 V 1.8 V MICBIAS1 Analog microphone or digital microphone PWDN Analog Mic Bias Analog Mic Bias 2 .2 V 2 .2 V HSMICBIAS Analog microphone (headset mic) DIG.MIC.CLK1 (Muxed with Bluetooth interface) CLK = 50 *Fs DIG.MIC.CLK0 (Muxed with Bluetooth interface) Comp DIG.MIC.0 or MIC.SUB.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 www.ti.com Table 6-16. Analog Microphone Bias Module Characteristics (continued) Parameter Test Conditions Output noise Min Typ P-weighted 20 Hz to 6.6 kHz External capacitor 0 Internal resistance 50 Max Unit 1.8 μVRMS 200 pF 70 kΩ 60 NOTE If the value of the external capacitor is greater than 200 pF, the analog microphone bias becomes unstable. To stabilize it, a serial resistor must be added.
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 NOTE For other component values, see Table 15-1. On board Device RMM.BP/RMS.SP MICBIAS1/2.OUT RMM.GM /2 or RMS.GM/2 CMM.B/CMS.B CMM.P/CMS.P MIC.SUB.P/MIC.MAIN.P 47pF CMM.PM/CMS.PM Close to device Close to device MIC.SUB.M/MIC.MAIN.M CMM.M/CMS.M CMM.GM or CMS.GM RMM.GM /2 or RMS.GM/2 CMM.GP or CMS.GP MICBIAS.GND 032-034 Figure 6-21. Analog Microphone Differential NOTE For other component values, see Table 15-1.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 www.ti.com 2.75 V Audio PLL VMIC1/2.OUT 1.8 V Dig mic bia s(LDO) VRIO=1.8 V Digial MIC clock generator 50* Fs DIG.MIC.CLK0/1 50* Fs BUF DIGMIC left Q R Q S Audio digital filter Comparator DIG.MIC.0/1 0.9 V Audio digital filter Q S DIGMIC right Q R Comparator 032-035 Figure 6-22. Digital Microphone Bias Module Block Diagram Table 6-18 and Table 6-19 list the characteristics of the digital microphone bias module. Table 6-18.
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 Figure 6-23 is a timing diagram of the digital microphone bias module. DIG.MIC.CLK0/1 DIG.MIC.0/1 thold thold 032-036 Figure 6-23. Digital Microphone Bias Module Timing Diagram 6.2.1.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 www.ti.com Optional On board depending on dynamic of microphone 1 kW Device RSM MICBIAS1/2.OUT CSM CSM.P Silicon microphone SPM0204HE5-PB (SPM0102ND3-C) MIC.SUB.P/MIC.MAIN.P 4 1 Power Output GND GND 3 2 CSM.PG MIC.SUB.M/MIC.MAIN.M CSM.M MICBIAS.GND 032-037 Figure 6-24. Silicon Microphone Module Table 6-20 lists the characteristics of the silicon microphone module. Table 6-20.
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TPS65950 www.ti.com 6.2.4 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 FM Radio/Auxiliary Stereo Input The auxiliary inputs AUXL/FML and AUXR/FMR can be used as the left and right stereo inputs, respectively, of the FM radio. In that case (because both input amplifiers are busy), the other input terminals are discarded and set to a high-impedance state. Both microphone amplification stages amplify the FM radio stereo signal. Both amplification stage outputs are connected to the ADC input.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 www.ti.com 2.75 V Digital mic bias (LDO) MICBIAS 1.8 V Digital mic clock generator 50* Fs 50* Fs DIG.MIC.CLK BUF Comparator DIG.MIC 0.9 V Comparator DIG.MIC.CLK Left Left Right DIG.MIC Right 032-039 Figure 6-26. Example of PDM Interface Circuitry 6.2.6 Uplink Characteristics Figure 6-27 shows the uplink amplifier. Table 6-21 lists the characteristics of the uplink amplifier.
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 Table 6-21. Uplink Amplifier Characteristics Parameter Test Conditions Speech delay Min Typ Voice path Max 0.5 Gain range (1) Unit ms 0 61 –1 1 dB dB Absolute gain 0 dBFs at 1.02 kHz Peak-to-peak differential input voltage (0 dBFs) For differential input 0 dB gain setting 1.5 VPP Peak-to-peak single-ended input voltage (0 dBFs) For single-ended input 0 dB gain setting 1.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 www.ti.com Table 6-22. MCPC and USB-CEA Carkit Audio Uplink Electrical Characteristics Parameter Gain range Test Conditions Min (1) Absolute gain, 0 dBFs at 1.02 kHz (1) (2) (3) Speech delay Typ –1 60 USB-CEA default gain setting –1.5 1.5 MCPC default gain setting –1.5 1.5 Voice path Input common mode voltage (4) Phone microphone amplifier input impedance at 1 kHz Max 0.5 USB-CEA 1.
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 6.2.10 Digital Voice Filter Module Figure 6-30 shows the digital voice filter uplink full path characteristics of the voice interface. A/D output SINC filter integrator Error cancellation SINC filter differentiator Low-pass filter High-pass filter Voice interface 032-043 Figure 6-30.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 www.ti.com Voice Uplink (TX) Filter 8 kHz 2 Gain (dB) 0 –2 1st order HPF Specification 3rd order HPF –4 –6 –8 –10 3000 3100 3200 3300 3400 3500 3600 Frequency (Hz) 032-045 Figure 6-32. Voice Uplink Frequency Response With FS = 8 kHz (Frequency Range 3000 to 3600 Hz) Table 6-24 lists the voice filter frequency responses relative to reference gain at 1 kHz with FS = 8 kHz. Table 6-24.
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 6.2.10.2 Voice Uplink Filter (Sampling Frequency at 16 kHz) Figure 6-33 and Figure 6-34 show the voice uplink frequency response with a sampling frequency of 16 kHz. Voice Uplink (TX) Filter 16 kHz 2 0 Gain (dB) –2 1st order HPF Specification –4 –6 –8 –10 0 100 200 300 400 Frequency (Hz) 500 600 032-046 Figure 6-33.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 www.ti.com Table 6-25.
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TPS65950 www.ti.com 7 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 USB HS 2.0 OTG Transceiver The TPS65950 includes a USB OTG transceiver with CEA and MCPC carkit interfaces that support USB 480 Mbps HS, 12 Mbps full-speed (FS), and USB 1.5 Mbps low-speed (LS) through a 4-pin ULPI. The carkit block ensures the interface between the phone and a carkit device. The TPS65950 USB supports CEA and MCPC carkit standards. Figure 7-1 is a block diagram of the USB 2.0 physical layer (PHY).
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 • • • 7.2 www.ti.
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 VBAT C VBUS.FC C VINTUSB.1P8 C VBUS.IN C VBAT.USB .* C VINTUSB.1P5 VINTUSB.1P8 VUSB.3P1 VINTUSB.1P5 CP.CAPN CP.CAPP CP.IN CP.GND C VUSB.3P1 CP.OUT UCLK USB CP STP Device ID DIR DP/UART3.RXD NXT DATA0/RX DATA1/TX Host processor DM/UART3.TXD USB 2.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 7.2.1 www.ti.com MCPC Carkit Port Timing MCPC UART specification: • 11-pin MCPC ARIB-USBI analog carkit interface • Integrated 50 RRTSO resistor • UART signaling (from 600 bps to 460.8 kbps) • Audio (mono/stereo) signaling: In this mode, the ULPI data bus is redefined as a 4-pin UART interface, which exchanges data through a direct access to the FS/LS analog transmitter and receiver.
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 Figure 7-4 shows the MCPC UART and handshake mode timings. UART_TX CK5 CK6 CK7 CK8 CK9 CK10 CK11 CK12 DM DP UART_RX UART_CTS RTSO CTSI UART_RTS 032-051 Figure 7-4. MCPC UART and Handshake Mode Timings 7.2.2 USB-CEA Carkit Port Timing CEA carkit mode lets the link communicate through the USB PHY to a remote carkit in CEA audio + data during audio (DDA) mode as defined in the CEA-936A specification.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 www.ti.com Table 7-2.
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TPS65950 www.ti.com 7.2.3 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 HS USB Port Timing The ULPI interface supports an 8-bit data bus and the internal clock mode. The 4-bit data bus and the external clock mode are not supported. The HS functional mode supports an operating rate of 480 Mbps. Table 7-4 and Table 7-5 assume testing over the recommended operating conditions (see Figure 7-7).
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 7.2.4 www.ti.com PHY Electrical Characteristics The PHY is the physical signaling layer of the USB 2.0. It contains the drivers and receivers required for physical data and protocol signaling on the DP and DM lines. The PHY interfaces to the USB controller through UTMI. There are two main classes of transmitters and receivers in the PHY: • FS and LS transceivers. These are the legacy USB1.x transceivers.
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 Table 7-7. LS/FS Single-Ended Receivers (continued) Parameter Comments Min Typ Max Unit UART Receiver CEA VIH_SER DP_PULLDOWN asserted Serial interface input low VIL_SER DP_PULLDOWN asserted 2 Switching threshold VTH MCPC DP pullup RMCPCDP Internal pullup Open-drain input high level ZIH Internal MCPC DP pullup asserted Open-drain input low level ZIL External open-drain NMOS impedance to ground.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 www.ti.com Table 7-9. LS/FS Differential Transmitter (continued) Parameter Comments Min Max Unit 210 ns 200 μs –2 2 ns –1 1 ns CL = [200–600] pF on DP and DM Pullup R = 1.5 kΩ at 3.6 V for DM only –25 25 ns tUSDJ2 CL = [200–600] pF on DP and DM Pullup R = 1.5 kΩ at 3.6 V for DM only –10 10 ns Output signal cross-over voltage Vcrs Pulldowns R = 15 kΩ on DP and DM Pullup R = 1.5 kΩ at 3.6 V on DM only 1.
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 Table 7-11 lists the parameters of the HS differential transmitter. Table 7-11.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 7.2.4.8 www.ti.com Pullup/Pulldown Resistors Table 7-13 lists the parameters of the pullup/pulldown resistors. Table 7-13. Pullup/Pulldown Resistors Parameter Comments Min Typ Max 0.9 1.1 1.575 1.425 2.2 3.
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 Table 7-14. PHY DPLL Electrical Characteristics (continued) Parameter Comments Min Typ Max Unit 100 ps Frequency error (input) ±150 ppm Frequency error (output) ±500 ppm Phase-to-phase variation 35 ps Noise on digital 1.5-V supply 100 mV Noise on analog 1.5-V supply 50 mV Noise on analog 1.8-V supply 36 mV Deterministic period jitter (input) 7.2.4.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 7.2.5.1 www.ti.com OTG VBUS Electrical Table 7-16 lists the OTG VBUS electrical parameters. Table 7-16. OTG VBUS Electrical Parameter Comments Min Typ Max Unit 15 μs 0.5 0.6 0.7 V VBUS Wake-Up Comparator VBUS wake-up delay DELVBUS_WK_UP VBUS wake-up threshold VVBUS_WK_UP VBUS Comparators A-device session valid VA_SESS_VLD 0.8 1.1 1.4 V A-device VBUS valid VA_VBUS_VLD 4.4 4.5 4.6 V B-device session end VB_SESS_END 0.
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 USB HS 2.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 8 Battery Interface 8.1 General Description 8.1.1 www.ti.com Battery Charger Interface Overview The TPS65950 has a BCI for complete battery management. The main function of the BCI is to control the charging of either 1-cell Li-ion or Li-ion polymer batteries, or 1-cell Li-ion batteries with cobalt-nickel-manganese anodes.
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TPS65950 www.ti.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 www.ti.com Charger device VAC R3 T3 C3 ICTLAC1 TAC CCOMPAC ICTLAC2 RSCOMPAC RLIMITAC VCCS Rs To battery pack 032-056 Figure 8-2. Typical Application Schematic (In-Rush Current Limitation) 8.2.3 Configuration With BCI Not Used Figure 8-3 shows how to connect the BCI when it is not in use. The SUSPENDM bit must be set to disable the BCI internally.
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 USB driver Device VBUS I = 52 VAC µA maximum inside the BCI ICTLAC1 OPEN ICTLUSB1 OPEN ICTLAC2 OPEN ICTLUSB2 OPEN VPRECH CPRECH PCHGAC PCHGUSB VCCS VBATS BCIAUTO VBAT POWER Battery pack Provided by external charger device ADIN0 Th er m i s t o r ADCIN1 ID r es is t o r ADIN2 GND 032-057 Figure 8-3.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 8.3 www.ti.com Electrical Characteristics This section describes the electrical characteristics of the BCI in the TPS65950. 8.3.1 Main Charge Table 8-1 lists the electrical characteristics of the main charge. Table 8-1. Main Charge Electrical Characteristics VBAT = 3.6 V, RS = 0.22 Ω, unless otherwise specified Parameter VAC input voltage range Test Conditions (1) VBUS input voltage range (external) Min Typ Max dc voltage 4.8 5.
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 Table 8-1. Main Charge Electrical Characteristics VBAT = 3.6 V, RS = 0.22 Ω, unless otherwise specified (continued) Parameter Max Unit CHGIREG = (value relative to ICHG = 0.6 A), VAC = 5.4 V, C = 100 nF connected to ICTLAC1, VBAT threshold = 4.55 V, measure charge current from removal to 10% Miller compensation 150 μs CHGIREG = (value relative to ICHG = 0.6 A), VAC = 5.4 V, C = 100 nF connected to ICTLAC1, VBAT threshold = 4.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 www.ti.com Table 8-1. Main Charge Electrical Characteristics VBAT = 3.6 V, RS = 0.22 Ω, unless otherwise specified (continued) Parameter ADCIN1 dc current source for temperature measurement Constant current loop accuracy Min Typ Max Unit ADCIN1 = 1 V, ITHSENS[2:0] = 000 (maximum MADC input voltage = 0.875 V), after TRIM done by ISRCTRIM[3:0] Test Conditions 9.5 10 10.
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 Table 8-1. Main Charge Electrical Characteristics VBAT = 3.6 V, RS = 0.22 Ω, unless otherwise specified (continued) Parameter Battery Rs 8.3.2 Test Conditions Min Typ ESR (including FUSE) Max Unit 0.5 Ω Precharge During slow precharge and fast precharge, a precharge voltage loop is always enabled and limits the battery voltage charge to 3.6 V typical.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 www.ti.com Table 8-2. Precharge Electrical Characteristics RS = 0.22 Ω, unless otherwise specified (continued) Min Typ Max Unit Fast precharge loop accuracy Parameter After TRIMinG, PCHGAC or PCHGUSB floating, VAC = 5.4 V, VBAT = 3.0 V, VCCS–VBATS rising voltage, monitoring ICTLAC1 or ICTLUSB1 56 68.8 81.2 mV Precharge constant voltage loop limitation System did not start after VBAT > 3.2 V, VBATS input. 3.4 3.6 3.
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 Table 8-3. CV Mode Electrical Characteristics (1) Parameter Test Conditions Min Typ Max Unit Main charge constant voltage mode VAC = 5.4 V, ADCIN1 pin floating, LDOOK = 1 CBAT Battery node capacitor 37 ESR (including FUSE) VBAT regulated voltage, including dc (posttrim), dc load regulation, and dc line regulation Typical condition is VBAT for VAC = 5.4 V, ILOAD = 0.5 A 3.88 80 167 μF 0.4 0.5 Ω 4.0 4.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 8.4 www.ti.com Charge Sequence Timing Diagram Figure 8-4 is the charge sequence timing diagram. VBAT CHGV (BCI) 4.20V VBATOV4 (BCI) 3.95V VBAT>3.2V (Power) 3.2V POR (Power) 2.65V FASTPRECH (BCI 2.0V SLOWPRECH (BCI) 1.
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 Table 8-4. Precharge Detection Characteristics (continued) Symbol Parameter TCHECK Repeat time check process TPULSE DP pullup pulse width Comments Min Max Unit 500 ms 20 ms In main charge, the basic chargers and basic carkits indicate their default current limit, versus the value of the ID resistor, between the ID pin and the ground, and also versus the data bus D± connection type (shorted or not shorted).
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 9 MADC 9.1 General Description www.ti.com The TPS65950 shares the MADC resource with the host processors in the system (hardware and software conversion modes) and its BCI.
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TPS65950 www.ti.com 9.3 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 Channel Voltage Input Range Table 9-2 lists the channel voltage input ranges. Table 9-2. Analog Input Voltage Range Channel Min Typ Max Unit Prescaler ADIN0: Battery type/GP input 0 1.5 V No prescaler dc current source for battery identification through external resistor (10 μA typical) ADCIN1: Battery temperature 0 1.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 www.ti.com Table 9-3 shows the information in Figure 9-1. The Busy parameter shows that a conversion sequence is running, and the channel N result register parameter corresponds to the result register of RT/GP/BCI selected channel.
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TPS65950 www.ti.com 10 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 LED Drivers 10.1 General Description Two arrays of parallel LEDs are driven (dedicated for the phone light). The parallel LEDs are supplied by VBAT and the external resistor value is given for each of them. The TPS65950 has two open-drain LED drivers for keypad backlighting. The keypad backlighting must incorporate any required current limiting and be rated for operation at the main battery voltage.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 11 www.ti.com Keyboard 11.1 Keyboard Connection The keyboard is connected to the chip using: • KBR (7:0) input pins for row lines • KBC (7:0) output pins for column lines Figure 11-1 shows the keyboard connection. Device VCC Internal pullup Keyboard controller 8x8 Keyboard matrix kbd_r_0 kbd_r_1 kbd_r_2 kbd_r_3 kbd_r_4 kbd_r_5 kbd_r_6 kbd_r_7 kbd_c_0 kbd_c_1 kbd_c_2 kbd_c_3 kbd_c_4 kbd_c_5 kbd_c_6 kbd_c_7 032-061 Figure 11-1.
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TPS65950 www.ti.com 12 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 Clock Specifications The TPS65950 includes several I/O clock pins. The TPS65950 has two sources of high-stability clock signals: the external high-frequency clock (HFCLKIN) input and an onboard 32-kHz oscillator (an external 32-kHz signal can be provided). Figure 12-1 is an overview of the clocks. Device OR 32KXIN OR 32KCLKOUT 32KXOUT 32 kHz OR HFCLKIN HFCLKOUT 032-062 Figure 12-1. Clock Overview 12.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 www.ti.com 12.2 Input Clock Specifications The clock system accepts two input clock sources: • 32-kHz crystal oscillator clock or sinusoidal/squared clock • HFCLKIN high-frequency input clock 12.2.1 Clock Source Requirements Table 12-1 lists the input clock requirements. Table 12-1. TPS65950 Input Clock Source Requirements Pad Clock Frequency 32KXIN 32KXOUT HFCLKIN (1) 32.768 kHz 19.2, 26, 38.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 www.ti.com When a device needs a clock signal other than 32.768 kHz, it makes a clock request and activates the CLKREQ pin. As a result, the TPS65950 immediately sets CLKEN to 1 to warn the clock provider in the system about the clock request and starts a timer (maximum of 5.2 ms using the 32.768-kHz clock).
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 NOTE The timer default value must be the worst case (10 ms) for the clock providers. For legacy or workaround support, the signals NSLEEP1 and NSLEEP2 can also be used as a clock request even if it is not their primary goal. By default, this feature is disabled and must be enabled individually by setting the register bits associated with each signal.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 • • www.ti.com An external 32.768-kHz crystal through the 32KXIN/32KXOUT balls (see Figure 12-5). This configuration is available for master mode only (for more information, see Section 13, Timing Requirements and Switching Characteristics). An external square or sine wave of 32.768 kHz through 32KXIN with amplitude of 1.8 or 1.85 V (see Figure 12-7, Figure 12-8, and Figure 12-9).
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 Table 12-4. Crystal Electrical Characteristics (continued) Parameter Min Typ Internal capacitor on each input (Cint) Max pF Parallel input capacitance (Cpin) 1 Nominal load cap on each oscillator input CXIN and CXOUT (1) pF CXIN = CXOUT = Cosc*2 – (Cint + Cpin) pF 1.6 1.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 www.ti.com 12.2.3.2 External Clock Description Figure 12-7 and Figure 12-8 show the 32-kHz oscillator with a 32.768-kHz square or sine signal in master and slave modes. Figure 12-9 shows an external clock source when the oscillator is configured in bypass mode. Thus, there are three configurations: • A square- or sine-wave input can be applied to the 32KXIN pin with an amplitude of 1.85 or 1.8 V.
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 Current control circuit and mode selection Bias generator and startup circuit Signal swing limiting circuit Y Signal shaping (1) VBATOK XI XO (1) VBATOK Floating Internal GND Square/sine wave: Vpp = VRRTC or VIO_1P8V Internal GND 032-069 (1) Switches close by default and open only if register access enables very-low-power mode when VBAT < 2.7 V. Figure 12-8.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 www.ti.com Table 12-7 lists the electrical constraints required by the 32-kHz input square- or sine-wave clock used. Table 12-7. 32-kHz Input Square- or Sine-Wave Clock Source Electrical Characteristics Name Parameter Description Min Typ Max Unit f Frequency 32.
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 IO_1P8 (1.8 V) OR 32KXIN 32-kHz OSC OR 32KCLKOUT 32 kHz 32KXOUT RTC 032-072 Figure 12-11. 32.768-kHz Clock Output Block Diagram The TPS65950 has an internal 32.768-kHz oscillator connected to an external 32.768-kHz crystal through the 32KXIN/32KXOUT balls or an external digital 32.768-kHz clock through the 32KXIN input (see Figure 12-11). The TPS65950 also generates a 32.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 www.ti.com Table 12-10. 32KCLKOUT Output Clock Switching Characteristics (continued) Name CK2 CK3 (1) Parameter Description Min Typ Max Rise time, 32KCLKOUT (1) tR(32KCLKOUT) tF(32KCLKOUT) Fall time, 32KCLKOUT (1) Unit 16 ns 16 ns The output capacitive load is 30 pF. CK0 CK1 CK1 32KCLKOUT 032-073 Figure 12-12. 32KCLKOUT Output Clock 12.3.
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 12.3.3 Output Clock Stabilization Time Figure 12-14 shows the 32KCLKOUT and HFCLKOUT clock stabilization time. XIN Starting_Event Tstartup CLK32KOUTEN CLK32KOUT CLKEN Delay1 HFCLKOUTEN HFCLKOUT Delay2 NRESPWRON 032-075 NOTE: Tstartup, Delay1, and Delay2 depend on the boot mode (see Section 4.5, Power Management). NOTE: Ensure that the high frequency oscillator start-up time is in spec for the boot mode used.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 13 www.ti.com Timing Requirements and Switching Characteristics 13.1 Timing Parameters The timing parameter symbols used in the timing requirement and switching characteristic tables are created in accordance with JEDEC Standard 100. To shorten the symbols, some pin names and other related terminologies are abbreviated as shown in Table 13-1. Table 13-1.
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 Table 13-2. TPS65950 Interface Target Frequencies (continued) I/O Interface TDM/I2S Voice/Bluetooth PCM interface (1) (2) Target Frequency Interface Designation 1.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 www.ti.com Table 13-3. I2C Interface Timing Requirements (continued) Notation Parameter Min Max Unit Slave Standard Mode I3 tsu(SDA-SCLH) Setup time, SDA valid to SCL high 250 ns I4 th(SCLL-SDA) Hold time, SDA valid from SCL low 0 ns I7 tsu(SCLH-SDAL) Setup time, SCL high to SDA low 4.7 ns I8 th(SDAL-SCLL) Hold time, SCL low from SDA low 4 ns I9 tsu(SDAH-SCLH) Setup time, SDA high to SCL high 4 ns Table 13-4.
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 Right channel Left channel I2S.SYNC I1 I2 I0 I1 I2 I2 I2S.CLK I4 I4 I3 I2S.DIN 23 22 1 22 1 I5 I2S.DOUT I4 I3 0 8 dummy bits 0 8 dummy bits I3 23 22 1 22 1 I5 I5 23 I4 I3 0 8 dummy bits 23 0 8 dummy bits 23 22 I5 23 22 032-078 Figure 13-2. I2S Interface—I2S Master Mode Left channel Right channel I2S.SYNC I1 I6 I0 I1 I7 I6 I2S.CLK I4 I4 I3 23 I2S.DIN 22 1 22 1 I5 23 I2S.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 www.ti.com Table 13-5. I2S Interface—Timing Requirements (continued) Notation Parameter Min Max Unit I3 tsu(DIN-CLKH) Setup time, I2S.DIN valid to I2S.CLK high 5 ns I4 th(DIN-CLKH) Hold time, I2S.DIN valid from I2S.CLK high. 5 ns I6 tsu(SYNC-CLKH) Setup time, I2S.SYNC valid to I2S.CLK high 5 ns I7 th(SYNC-CLKH) Hold time, I2S.SYNC valid from I2S.CLK high 5 ns The capacitive load for Table 13-6 is 7 pF. Table 13-6.
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 Table 13-8 lists the master mode switching characteristics of the TDM interface. Table 13-8. TDM Interface Master Mode Switching Characteristics Notation (1) (2) Parameter Min (1) T0 tc(CLK) Cycle time, TDM.CLK T1 tw(CLK) Pulse duration, TDM.CLK high or low (2) T2 td(CLKL-SYNC) T5 td(CLKL-DOUT) Max 1/64 * Fs Unit ns 0.45*P 0.55*P ns Delay time, TDM.CLK rising edge to TDM.SYNC transition –10 10 ns Delay time, TDM.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 www.ti.com PCM.VFS P7 P7 P1 P6 P0 P6 P1 PCM.VCK P4 P4 P3 PCM.VDR 15 P3 14 1 P5 PCM.VDX 0 49 dummy bits 15 49 dummy bits 15 14 P5 15 14 1 0 14 032-082 Figure 13-6. Voice PCM Interface—Slave Mode (Mode 1) The timing requirements in Table 13-9 are valid on the following conditions of input slew and output load: • Rise and fall time range of inputs (SYNC, DIN) is tR/tF = 1.0 ns/6.
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 Table 13-10. Voice PCM Interface Switching Characteristics (Mode 1) (continued) Notation Parameter P2 td(VCK-VFS) Delay time, PCM.VCK transition to PCM.VFS transition P5 td(VCL-VDX) Delay time, PCM.VCK transition to PCM.VDX transition (3) Min Max –10 10 + Pvoice Unit ns –10 10 ns 0 20 ns Voice PCM Slave Mode P5 (3) td(VCL-VDX) Delay time, PCM.VCK transition to PCM.VDX transition When TPS65950 is master, the PCM.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 www.ti.com Table 13-11. JTAG Interface Timing Requirements Notation Parameter Min Max Unit Clock JL1 tc(TCK) Cycle time, JTAG.TCK period JL2 tw(TCK) Pulse duration, JTAG.TCK high or low (1) 30 0.48*P ns 0.52*P ns Read Timing (1) JL3 tsu(TDIV-TCKH) Setup time, JTAG.TDI valid before JTAG.TCK high 8 ns JL4 th(TDIV-TCKH) Hold time, JTAG.TDI valid after JTAG.TCK high 5 ns JL5 tsu(TMSV-TCKH) Setup time, JTAG.
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TPS65950 www.ti.com 14 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 Debouncing Time Table 14-1 lists the debouncing functions. Table 14-1. Debouncing Time Debouncing Functions Block Programmable Debouncing Time Default Battery monitoring No 580 μs 580 μs Main battery low threshold detection (<2.7 V) No 60 μs 60 μs Main battery plug detection (with charger connected) No 60 μs 60 μs BCI (automatic charge) No 1 x 50 ms 1 x 50 ms BCI No 9 x 50 ms 9 x 50 ms Power No 125.6 μs 125.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 www.ti.com Event1 Event2 31 ms 32K clock 50 ms 50-ms clock Event1 detected on 32K clock synchronized with 50-ms clock Event1 Debounced after 50 ms 50 ms dT Event2 Debounced after 50 ms + dT 50 ms + dT 032-084 Figure 14-1. Debouncing Sequence Chronogram Example Event 1 is correctly debounced after 50 ms. Event 2 is debounced after 50 ms + dT because the capture of the event is considered after the next rising edge of the 50-ms clock.
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TPS65950 www.ti.com 15 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 External Components Table 15-1 lists the external components of the TPS65950. Table 15-1. TPS65950 External Components Function Component Reference Value Note Link Power Supplies Capacitor CVDD1.IN 10 μF Range ± 50% ESR minimum = 1 mΩ ESR maximum = 20 mΩ Taiyo Yuden: JMK212BJ106KD Capacitor CVDD1.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 www.ti.com Table 15-1. TPS65950 External Components (continued) Function Component Capacitor Reference CVMMC1.IN Value Note 1 μF Range: 0.3 to 2.7 μF ESR minimum = 20 mΩ ESR maximum = 600 mΩ VMMC1 Capacitor CVMMC1.OUT 1 μF Range: 0.3 to 2.7 μF ESR minimum = 20 mΩ ESR maximum = 600 mΩ Capacitor CVMMC2.IN 1 μF Range: 0.3 to 2.7 μF ESR minimum = 20 mΩ ESR maximum = 600 mΩ VMMC2 Link Figure 4-1 Figure 4-1 Capacitor CVMMC2.
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 Table 15-1. TPS65950 External Components (continued) Function Component Reference Value Note Link MCPC 0.1 μF Capacitor CTXAF Capacitor CRXAF 1 μF Resistor RRTSO 22 Ω/100 Ω Diode DCTSI1 NNCD5.6J Diode DCTSI2 NNCD5.6J Diode DRTSO1 NNCD5.6J Diode DRTSO2 Figure 7-2 NNCD5.6J 32.768 kHz Capacitor CXIN 10 pF Capacitor CXOUT 10 pF Quartz X32.768kHz 32.768 kHz Range: 9 to 12.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 www.ti.com Table 15-1. TPS65950 External Components (continued) Function External class-D predriver right Vibrator H-bridge Main microphone (pseudodifferential mode) Submicrophone (pseudodifferential mode) Main microphone (differential mode) Component 158 Value CPR.O Capacitor CPR 1 μF Resistor RPR >15 kΩ Resistor RPR.M >15 kΩ Resistor RPR.O 10 kΩ Capacitor CPR.M 1 μF Ferrite bead LV.M Ferrite bead LV.P Capacitor CV.
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 Table 15-1. TPS65950 External Components (continued) Function VMIC2 Silicon microphone Auxiliary left Auxiliary right Component Reference Value Capacitor CVMIC2.OUT 1 μF Capacitor CSM 1 μF Capacitor CSM.P 100 nF Capacitor CSM.M 100 nF Capacitor CSM.PG 47 nF Resistor RSM >500 Ω Capacitor CAUXL 100 nF Capacitor CAUXL.M 47 pF Capacitor CAUXR 100 nF Capacitor CAUXR.M Note Link Range: 0.3 to 3.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 16 www.ti.com TPS65950 Package 16.1 TPS65950 Standard Package Symbols Table 15-1 shows the TPS65950 printed device reference. Pin 1 indicator o YMLLLLS $ 032-001 Figure 16-1. Printed Device Reference Table 16-1 lists the symbols used in the TPS65950 nomenclature. Table 16-1.
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TPS65950 www.ti.com SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 16.3 Mechanical Data Figure 16-2 is the top view of the TPS65950 mechanical package. 6.00 0.40 T R P N M L K J H G F E D C B A 5 15 13 11 9 7 3 1 16 14 12 10 8 6 4 2 Top View 032-086 Figure 16-2. TPS65950 Mechanical Package Top View Figure 16-3 shows the ball size. 0.22 mm 0.26(±0.05) mm 032-087 Figure 16-3.
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TPS65950 SWCS032E – OCTOBER 2008 – REVISED JANUARY 2011 www.ti.com 16.4 ESD Specifications The device has built-in ESD protection to the limits specified below. It is recommended that the leads are shorted together, or the device placed in conductive foam, during storage or handling to prevent electrostatic damage.
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PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS65950A2ZXNR NFBGA ZXN 209 2000 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q1 TPS65950A3ZXNR NFBGA ZXN 209 2000 330.0 16.4 7.3 7.3 1.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS65950A2ZXNR NFBGA ZXN 209 2000 336.6 336.6 31.8 TPS65950A3ZXNR NFBGA ZXN 209 2000 336.6 336.6 31.
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