Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - LDO voltage regulator Positive, fixed HTSSOP 20

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FEATURES DESCRIPTION

PWP PACKAGE

(TOP VIEW)

IN1

MR1

MR2

SEQ

GND

IN2

OUT1

SENSE1

/FB1

PG1

RESET

SENSE2

/FB2

OUT2

TPS70145, TPS70148

TPS70151, TPS70158

TPS70102

SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004

Dual-Output Low-Dropout Voltage Regulators

with Power-Up Sequencing for Split-Voltage DSP Systems

• Dual Output Voltages for Split-Supply

TPS701xx family devices are designed to provide a

Applications

complete power management solution for the

TMS320™ DSP family, processor power, ASIC,

• Selectable Power-Up Sequencing for DSP

FPGA, and digital applications where dual output

Applications

voltage regulators are required. Easy programmability

• Output Current Range of 500mA on Regulator

of the sequencing function makes the TPS701xx

1 and 250mA on Regulator 2

family ideal for any TMS320 DSP applications with

• Fast Transient Response

power sequencing requirements. Differentiated fea-

tures, such as accuracy, fast transient response, SVS

• Voltage Options: 3.3V/2.5V, 3.3V/1.8V,

supervisory circuit, manual reset inputs, and an

3.3V/1.5V, 3.3V/1.2V, and Dual Adjustable

enable function, provide a complete system solution.

Outputs

The TPS701xx family of voltage regulators offers very

• Open Drain Power-On Reset with 120ms Delay

low dropout voltage and dual outputs with power-up

• Open Drain Power Good for Regulator 1

sequence control, which is designed primarily for

• Ultra Low 190µA (typ) Quiescent Current

DSP applications. These devices have extremely low

noise output performance without using any added

• 1µA Input Current During Standby

filter bypass capacitors and are designed to have a

• Low Noise: 65µV

RMS

Without Bypass

fast transient response and be stable with 10µF low

Capacitor

ESR capacitors.

• Quick Output Capacitor Discharge Feature

These devices have fixed 3.3V/2.5V, 3.3V/1.8V,

• Two Manual Reset Inputs

3.3V/1.5V, 3.3V/1.2V, and adjustable/adjustable volt-

• 2% Accuracy Over Load and Temperature

age options. Regulator 1 can support up to 500mA,

and regulator 2 can support up to 250mA. Separate

• Undervoltage Lockout (UVLO) Feature

voltage inputs allow the designer to configure the

• 20-Pin PowerPAD™ TSSOP Package

source power.

• Thermal Shutdown Protection

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD, TMS320 are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (34 pages)

PAGE 1
TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004 Dual-Output Low-Dropout Voltage Regulators with Power-Up Sequencing for Split-Voltage DSP Systems FEATURES • • • • • • • • • • • • • • • • Dual Output Voltages for Split-Supply Applications Selectable Power-Up Sequencing for DSP Applications Output Current Range of 500mA on Regulator 1 and 250mA on Regulator 2 Fast Transient Response Voltage Options: 3.3V/2.5V, 3.3V/1.8V, 3.3V/1.5V, 3.3V/1.
PAGE 2
TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004 TPS70151 PWP 5V VIN1 0.1 µF 3.3 V VOUT1 250 kΩ PG1 PG1 MR2 MR2 >2 V <0.7 V 0.1 µF >2 V EN 250 kΩ RESET RESET EN MR1 I/O 10 µF VSENSE1 VIN2 DSP MR1 >2 V <0.7 V <0.7 V VSENSE2 SEQ 1.8 V VOUT2 Core 10 µF Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 170mV on regulator 1) and is directly proportional to the output current.
PAGE 3
TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004 RECOMMENDED OPERATING CONDITIONS Over operating temperature range (unless otherwise noted) MIN Input voltage, VI (1) Output current, IO (regulator 1) Output current, IO (regulator 2) Output voltage range (for adjustable option) Operating junction temperature, TJ (1) MAX UNIT 2.7 6 0 500 mA V 0 250 mA 1.22 5.
PAGE 5
TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004 ELECTRICAL CHARACTERISTICS (continued) Over recommended operating junction temperature range (TJ = -40°C to +125°C), VIN1 or VIN2 = VOUT(nom) + 1V, IO = 1mA, EN = 0, CO = 33µF, (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX 1.0 1.
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TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004 ELECTRICAL CHARACTERISTICS (continued) Over recommended operating junction temperature range (TJ = -40°C to +125°C), VIN1 or VIN2 = VOUT(nom) + 1V, IO = 1mA, EN = 0, CO = 33µF, (unless otherwise noted). PARAMETER TEST CONDITIONS MIN Dropout voltage (4) IO = 500mA, TJ = 25°C VIN1 = 3.2V Dropout voltage (4) IO = 500mA, VIN1 = 3.
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TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004 DEVICE INFORMATION (continued) Adjustable Voltage Version VOUT1 (2 Pins) VIN1 (2 Pins) Current Sense UVLO Shutdown 2.5 V − GND Reference Thermal Shutdown FB1 (see Note A) ENA_1 + ENA_1 Vref Vref PG1 FB1 Rising Edge Deglitch 0.95 × Vref VIN1 MR2 Shutdown FB2 UV Comp FB2 Falling Edge Deglitch 0.83 × Vref FB1 Falling Edge Deglitch 0.83 × Vref PG1 Comp 0.
PAGE 8
TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004 DEVICE INFORMATION (continued) RESET Timing Diagram (with VIN1 Powered Up) VIN2 VRES (see Note A) VRES t VOUT2 VIT +(see Note B) VIT +(see Note B) Threshold Voltage VIT − (see Note B) VIT − (see Note B) t RESET Output 120 ms Delay 120 ms Delay Output Undefined Output Undefined t NOTES: A. VRES is the minimum input voltage for a valid RESET.
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TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004 DEVICE INFORMATION (continued) Table 1. TERMINAL FUNCTIONS TERMINAL NAME NO.
PAGE 10
TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004 www.ti.com Power-Good The PG1 is an open drain, active high output terminal which indicates the status of the VOUT1 regulator. When the VOUT1 reaches 95% of its regulated voltage, PG1 will go to a high impedance state. It will go to a low impedance state when it is pulled below 95% (for example, an overload condition) of its regulated voltage.
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TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004 TYPICAL CHARACTERISTICS Table 2.
PAGE 12
TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004 TPS70145 OUTPUT VOLTAGE vs OUTPUT CURRENT TPS70151 OUTPUT VOLTAGE vs TEMPERATURE 1.201 3.286 VIN2 = 2.7 V TA = 25°C VOUT2 1.200 3.284 VIN1 = 4.3 V IO = 1 mA VOUT1 VO − Output Voltage − V VO − Output Voltage − V 3.282 1.199 1.198 1.197 3.280 3.278 3.276 3.274 3.272 1.196 3.270 1.195 0 0.05 0.1 0.15 0.2 0.25 3.268 −40 −25 −10 0.
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TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004 TPS70151 OUTPUT VOLTAGE vs TEMPERATURE GROUND CURRENT vs JUNCTION TEMPERATURE 210 1.799 VIN2 = 2.8 V IO = 250 mA VOUT2 1.798 Regulator 1 and Regulator 2 200 IOUT1 = 1 mA IOUT2 = 1 mA Ground Current − µ A VO − Output Voltage − V 1.797 1.796 1.795 1.794 1.793 190 180 IOUT1 = 250 mA IOUT2 = 500 mA 170 1.792 160 1.791 1.
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TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.
PAGE 15
TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004 OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY 10 VIN2 = 2.8 V VOUT2 = 1.8 V IO = 10 mA Output Spectral Noise Density − µV Hz Output Spectral Noise Density − µV Hz 10 1 0.1 0.01 100 1k 10 k f − Frequency − Hz 0.1 1k 10 k f − Frequency − Hz Figure 15. Figure 16.
PAGE 16
TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004 OUTPUT IMPEDANCE vs FREQUENCY OUTPUT IMPEDANCE vs FREQUENCY 100 CO = 33 µF IO = 250 mA VO = 1.8 V TA = 25 C 10 Z O − Output Impedance − Ω Z O − Output Impedance − Ω 100 1 0.1 0.01 10 100 1k 10 k 100 k 1M 10 1 0.1 0.01 10 M CO = 33 µF IO = 10 mA VO = 1.8 V TA = 25 C 10 100 10 k 100 k f − Frequency − Hz Figure 19. Figure 20.
PAGE 17
TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004 TPS70102 DROPOUT VOLTAGE vs INPUT VOLTAGE 300 TPS70102 DROPOUT VOLTAGE vs INPUT VOLTAGE 500 IO = 500 mA VIN1 IO = 250 mA VIN2 250 400 Dropout Voltage − mV Dropout Voltage − mV TJ = 125°C 200 TJ = 25°C 150 100 TJ= −40°C TJ = 125°C 300 TJ = 25°C 200 TJ = − 40°C 100 50 0 2.5 3 3.5 4 4.5 5 0 2.5 5.
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TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004 VI − Input Voltage − V 5.3 4.3 0 IO = 500 mA Co = 33 µF VOUT1 −50 20 40 60 2 10 0 IO = 250 mA Co = 33 µF VOUT2 −10 0 20 40 60 80 100 120 140 160 180 200 t − Time − µs Figure 28. OUTPUT VOLTAGE AND ENABLE VOLTAGE vs TIME (START-UP) OUTPUT VOLTAGE AND ENABLE VOLTAGE vs TIME (START-UP) 1 0 5 0 −5 0 2.8 Figure 27. VO = 3.3 V Co = 33 µF IO = 500 mA VOUT1 SEQ = Low 3 3.
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TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004 TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE vs OUTPUT CURRENT TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE vs OUTPUT CURRENT 10 REGION OF INSTABILITY ESR −Equivalent Series Resistance −Ω ESR −Equivalent Series Resistance −Ω 10 VO = 3.3V CO = 33 F TJ = 25 C 1 0.1 50 mΩ REGION OF INSTABILITY 0.01 REGION OF INSTABILITY 1 VO = 3.3 V CO = 33 F + 1 F TJ = 25 C 0.
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TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004 TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE vs OUTPUT CURRENT TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE vs OUTPUT CURRENT 10 REGION OF INSTABILITY ESR −Equivalent Series Resistance −Ω ESR −Equivalent Series Resistance −Ω 10 VO = 1.8 V CO = 33 F TJ = 25 C 1 0.1 50 mΩ REGION OF INSTABILITY 0.01 REGION OF INSTABILITY 1 VO = 1.8 V CO = 33 F + 1 F TJ = 25 C 0.
PAGE 21
TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004 APPLICATION INFORMATION TPS701xxPWP (Fixed Output Option) Sequencing Timing Diagrams This section provides a number of timing diagrams showing how this device functions in different configurations. VI VIN1 0.1 µF Application condition: MR2 is tied to PG1, VIN1 and VIN2 are tied to the same input voltage, the SEQ pin is tied to logic low and the device is toggled with the enable (EN) function.
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TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004 Application condition: MR2 is tied to PG1, VIN1 and VIN2 are tied to the same input voltage, the SEQ pin is tied to logic high and the device is toggled with the enable (EN) function. TPS701xxPWP (Fixed Output Option) VI VOUT1 VIN1 When the device is enabled (EN is pulled low), VOUT2 begins to power up. When it reaches 83% of its regulated voltage, VOUT1 begins to power up.
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TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004 Application condition: MR2 is tied to PG1, VIN1 and VIN2 are tied to the same input voltage, the SEQ pin is tied to logic high and MR1 is toggled. TPS701xxPWP (Fixed Output Option) VI VIN1 When the device is enabled (EN is pulled low), VOUT2 begins to power up. When it reaches 83% of its regulated voltage, VOUT1 begins to power up.
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TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004 Application condition: MR2 is tied to PG1, VIN1 and VIN2 are tied to the same input voltage, the SEQ pin is tied to logic high and VOUT1 faults out. TPS701xxPWP (Fixed Output Option) VI VOUT1 VIN1 VOUT2 begins to power up when the device is enabled (EN is pulled low). When VOUT2 reaches 83% of its regulated voltage, then VOUT1 begins to power up.
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TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004 Application condition: MR2 is tied to PG1, VIN1 and VIN2 are tied to same input voltage, the SEQ is tied to logic high, the device is enabled, and VOUT2 faults out. TPS701xxPWP (Fixed Output Option) VI VOUT1 VIN1 VOUT2 begins to power up when the device is enabled (EN is pulled low). When VOUT2 reaches 83% of its regulated voltage, VOUT1 begins to power up.
PAGE 26
TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004 Split Voltage DSP Application Figure 45 shows a typical application where the TPS70151 is powering up a DSP. In this application, by grounding the SEQ pin, VOUT1 (I/O) is powered up first, and then VOUT2 (core). TPS70151 PWP 5V VIN1 0.1 µF 10 µF VSENSE1 250 kΩ MR2 MR2 >2 V <0.7 V 0.1 µF >2 V 5V PG1 PG1 VIN2 DSP 3.3 V VOUT1 250 kΩ RESET RESET EN MR1 EN MR1 >2 V <0.7 V <0.
PAGE 27
TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004 Figure 46 shows a typical application where the TPS70151 is powering up a DSP. In this application, by pulling up the SEQ pin, VOUT2 (core) is powered up first, and then VOUT1 (I/O). TPS70151 PWP 5V VIN1 0.1 µF DSP 3.3 V VOUT1 10 µF VSENSE1 I/O 250 kΩ 5V PG1 PG1 VIN2 0.1 µF >2 V EN MR2 MR2 250 kΩ RESET RESET EN <0.7 V MR1 MR1 VSENSE2 SEQ 1.
PAGE 28
TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004 Input Capacitor For a typical application, an input bypass capacitor (0.1µF – 1µF) is recommended. This capacitor filters any high frequency noise generated in the line. For fast transient condition where droop at the input of the LDO may occur due to high inrush current, it is recommended to place a larger capacitor at the input as well.
PAGE 29
TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004 Iout LDO + VESR RESR − Vin RLOAD Vout Cout Figure 48. LDO Output Stage with Parasitic Resistances ESR In steady state (dc state condition), the load current is supplied by the LDO (solid arrow) and the voltage across the capacitor is the same as the output voltage (V(CO) = VOUT). This means no current is flowing into the CO branch.
PAGE 30
TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004 The figure also shows the impact of different ESRs on the output voltage. The left brackets show different levels of ESRs where number 1 displays the lowest and number 3 displays the highest ESR. From above, the following conclusions can be drawn: • The higher the ESR, the larger the droop at the beginning of load transient.
PAGE 31
www.ti.com TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004 Power Dissipation and Junction Temperature Specified regulator operation is assured to a junction temperature of 125°C; the maximum junction temperature should be restricted to 125°C under normal operating conditions. This restriction limits the power dissipation the regulator can handle in any given application.
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PACKAGE OPTION ADDENDUM www.ti.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.