Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - LDO voltage regulator Positive, fixed HTSSOP 24

GND/HEATSINK

IN1

IN2

OUT2

OUT1

SENSE2

/FB2

IN1

IN2

OUT2

OUT1

EN1

EN2

RESET

GND

NC=Nointernalconnection

GND/HEATSINK

PG2

PG1

SENSE1

/FB1

PWPPACKAGE

(TOPVIEW)

1.8 V

IN1

IN2

EN1

EN2

OUT1

SENSE1

PG1

RESET

PG2

SENSE2

OUT2

TPS70451PWP

5V

3.3V

I/O

PG2

Core

0.22 mF

RESET

22 mF

47 mF

0.22 mF

PG1

EN1

250kW

>2V

<0.7V

250kW

>2V

<0.7V

>2V

<0.7V

EN2

250kW

TPS70445, TPS70448

TPS70451, TPS70458

TPS70402

www.ti.com

SLVS307F –SEPTEMBER 2000–REVISED APRIL 2010

DUAL-OUTPUT, LOW DROPOUT VOLTAGE REGULATORS

WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS

Check for Samples: TPS70445, TPS70448, TPS70451, TPS70458, TPS70402

FEATURES

DESCRIPTION

• Dual Output Voltages for Split-Supply

The TPS704xx family of devices consists of

Applications

dual-output, low-dropout voltage regulators with

integrated SVS (RESET, POR, or power on reset)

• Independent Enable Functions (See Part

and power good (PG) functions. These devices are

Number TPS703xx for Sequenced Outputs)

capable of supplying 1 A and 2 A by regulator 1 and

• Output Current Range of 1 A on Regulator 1

regulator 2 respectively. Quiescent current is typically

and 2 A on Regulator 2

185 mA at full load. Differentiated features, such as

• Fast Transient Response

accuracy, fast transient response, SVS supervisory

circuit (power on reset), manual reset input, and

• Voltage Options: 3.3-V/2.5-V, 3.3-V/1.8-V,

independent enable functions provide a complete

3.3-V/1.5-V, 3.3-V/1.2-V, and Dual Adjustable

system solution.

Outputs

• Open Drain Power-On Reset with 120-ms Delay

• Open Drain Power Good for Regulator 1 and

Regulator 2

• Ultralow 185mA (typ) Quiescent Current

• 2mA Input Current During Standby

• Low Noise: 78mV

RMS

Without Bypass Capacitor

• Quick Output Capacitor Discharge Feature

• One Manual Reset Input

• 2% Accuracy Over Load and Temperature

• Undervoltage Lockout (UVLO) Feature

• 24-Pin PowerPAD™ TSSOP Package

• Thermal Shutdown Protection

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PowerPAD is a trademark of Texas Instruments.

3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (41 pages)

PAGE 1
TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 www.ti.com SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 DUAL-OUTPUT, LOW DROPOUT VOLTAGE REGULATORS WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS Check for Samples: TPS70445, TPS70448, TPS70451, TPS70458, TPS70402 FEATURES DESCRIPTION • The TPS704xx family of devices consists of dual-output, low-dropout voltage regulators with integrated SVS (RESET, POR, or power on reset) and power good (PG) functions.
PAGE 2
TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 www.ti.com The TPS704xx family of voltage regulators offers very low dropout voltage and dual outputs. These devices have extremely low noise output performance without using any added filter bypass capacitors and are designed to have a fast transient response and be stable with 47-mF low ESR capacitors. These devices have fixed 3.3-V/2.5-V, 3.3-V/1.8-V, 3.3-V/1.5-V, 3.3-V/1.2-V, and adjustable voltage options.
PAGE 3
TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 www.ti.com SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 www.ti.com DISSIPATION RATINGS PACKAGE AIR FLOW (CFM) TA ≤ +25°C DERATING FACTOR TA = +70°C TA = +85°C 0 3.067W 30.67mW/°C 1.687W 1.227W 250 4.115W 41.15mW/°C 2.265W 1.646W PWP (1) (1) This parameter is measured with the recommended copper heat sink pattern on a 4-layer PCB, 1 oz. copper on a 4-in by 4-in ground layer. For more information, refer to TI technical brief SLMA002.
PAGE 5
TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 www.ti.com SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 ELECTRICAL CHARACTERISTICS Over recommended operating junction temperature range (TJ = –40°C to +125°C), VIN1 or VIN2 = VOUT(nom) + 1 V, IO = 1 mA, EN = 0 V, COUT1 = 22 mF, and COUT2 = 47 mF (unless otherwise noted). PARAMETER 2.7 V < VIN < 6 V, TJ = +25°C FB connected to VO 2.7 V < VIN < 6 V, FB connected to VO 1.2 V Output (VOUT2) 2.7 V < VIN < 6 V, TJ = +25°C 1.5 V Output (VOUT2) 2.
PAGE 6
TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Over recommended operating junction temperature range (TJ = –40°C to +125°C), VIN1 or VIN2 = VOUT(nom) + 1 V, IO = 1 mA, EN = 0 V, COUT1 = 22 mF, and COUT2 = 47 mF (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 2.65 V VIN1/VIN2 Terminal UVLO threshold 2.4 UVLO hysteresis 110 mV PG1/PG2 Terminal V(PGx) ≤ 0.
PAGE 7
TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 www.ti.com SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 DEVICE INFORMATION Fixed Voltage Version VIN1 (2 Pins) VOUT1 (2 Pins) 2.5 V UVLO1 Comp 10kW Current Sense + (see Note A) + GND VSENSE1 ENA_1 Reference Thermal Shutdown ENA_1 Vref Vref PG1 VSENSE1 - 0.95 x Vref + Rising Edge Deglitch VIN1 PG1 Comp MR RESET 120 ms Delay ENA_1 EN1 PG2 Comp VSENSE2 - 0.95 x Vref + ENA_2 PG2 Rising Edge Deglitch Vref FB2 EN2 - 2.
PAGE 8
TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 www.ti.com Adjustable Voltage Version VOUT1 (2 Pins) VIN1 (2 Pins) 2.5 V UVLO1 Comp Current Sense + GND FB1 (see Note A) ENA_1 + Reference Thermal Shutdown ENA_1 Vref FB1 Vref PG1 FB1 - 0.95 x Vref + Rising Edge Deglitch VIN1 PG1 Comp MR RESET 120 ms Delay ENA_1 EN1 PG2 Comp FB2 - 0.95 x Vref + ENA_2 PG2 Rising Edge Deglitch Vref FB2 EN2 - 2.5 V UVLO2 Comp + - VIN2 (2 Pins) A.
PAGE 9
TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 www.ti.com SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 RESET Timing Diagram VIN1 VUVLO VUVLO VRES t VRES (see Note A) MR Input t RESET Output 120 ms Delay Output Undefined 120 ms Delay Output Undefined t NOTE A: VRES is the minimum input voltage for a valid RESET. The symbol VRES is not currently listed within EIA or JEDEC standards for semiconductor symbology.
PAGE 10
TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 www.ti.com PG2 Timing Diagram (assuming VIN1 already powered up) VIN2 t VOUT2 VIT+ (see Note A) Threshold Voltage VIT(see Note A) t PG2 Output t NOTE A: VIT- trip voltage is typically 5% lower than the output voltage (95%VO). VIT- to VIT+ is the hysteresis voltage. TERMINAL FUNCTIONS TERMINAL NAME NO.
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TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 www.ti.com SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 Detailed Description The TPS704xx low dropout regulator family provides dual regulated output voltages with independent enable functions. These devices provide fast transient response and high accuracy with small output capacitors, while drawing low quiescent current.
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TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 www.ti.com FB1 and FB2 FB1 and FB2 are input terminals used for adjustable-output devices and must be connected to the external feedback resistor divider. FB1 and FB2 connections should be as short as possible. It is essential to route them in such a way as to minimize or avoid noise pickup.
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TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 www.ti.
PAGE 14
TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) TPS70451 OUTPUT VOLTAGE vs JUNCTION TEMPERATURE TPS70451 OUTPUT VOLTAGE vs JUNCTION TEMPERATURE 1.834 VOUT1 VIN2 = 2.8 V VOUT2 1.824 3.334 3.314 VO - Output Voltage - V VO - Output Voltage - V 3.354 VIN1 = 4.3 V IO = 1 mA 3.294 IO = 1 A 3.274 3.254 1.814 IO = 2 A 1.804 IO = 1 mA 1.794 1.784 1.774 3.
PAGE 15
TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 www.ti.com SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 TYPICAL CHARACTERISTICS (continued) TPS70451 POWER-SUPPLY REJECTION RATIO vs FREQUENCY TPS70451 POWER-SUPPLY REJECTION RATIO vs FREQUENCY 0 VIN1 = 4.3 V PSRR - Power Supply Rejection Ratio - dB PSRR - Power Supply Rejection Ratio - dB -10 VOUT1 = 3.3 V -20 IO = 10 mA CO = 22 mF -30 -40 -50 -60 -70 -80 -90 10 100 1k 10 k 100 k VIN1 = 4.3 V -10 VOUT1 = 3.
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TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY 10 VIN1 = 4.3 V VIN2 = 2.8 V VOUT1 = 3.3 V VOUT2 = 1.8 V Output Spectral Noise Density - mV/ÖHz Output Spectral Noise Density - mV/ÖHz 10 COUT1 = 22 mF IO = 10 mA TJ = 25°C 1 0.1 0.01 100 1k 10 k 0.1 1k 10 k f - Frequency - Hz Figure 10. Figure 11.
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TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 www.ti.com SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 TYPICAL CHARACTERISTICS (continued) OUTPUT IMPEDANCE vs FREQUENCY OUTPUT IMPEDANCE vs FREQUENCY VOUT1 = 3.3 V VOUT1 = 3.3 V IO = 1 A CO = 22 mF CO = 22 mF ZO - Output Impedance - W ZO - Output Impedance - W IO = 10 mA 1 0.1 0.01 10 100 1k 10 k 100 k 1M 1 0.1 0.01 10 10 M 100 1k f - Frequency - Hz Figure 15. OUTPUT IMPEDANCE vs FREQUENCY OUTPUT IMPEDANCE vs FREQUENCY VOUT2 = 1.
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TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) TPS70451 DROPOUT VOLTAGE vs TEMPERATURE TPS70451 DROPOUT VOLTAGE vs TEMPERATURE 250 25 VOUT1 VOUT1 VIN1 = 3.2 V VIN1 = 3.2 V 20 IO = 1 A Dropout Voltage - mV Dropout Voltage - mV 200 150 100 50 IO = 100 mA 15 10 5 IO = 10 mA 0 -40 -25 -10 5 20 35 50 65 80 0 -40 -25 -10 95 110 125 T - Temperature - °C 5 20 IO = 1 mA 35 50 65 Figure 19.
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TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 www.ti.com SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 TYPICAL CHARACTERISTICS (continued) IO - Output Current - A LOAD TRANSIENT RESPONSE VIN1 = 4.3 V VOUT1 = 3.3 V 1 CO = 22 mF 0.5 0 DVO - Change in 50 0 -50 -100 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 Output Voltage - mV DVO - Change in Output Voltage - mV IO - Output Current - A LOAD TRANSIENT RESPONSE VOUT2 = 1.8 V IO = 2 A 2 CO = 47 mF 1 0 50 0 -50 0 2 0.
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TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) OUTPUT VOLTAGE AND ENABLE VOLTAGE vs TIME (START-UP) OUTPUT VOLTAGE AND ENABLE VOLTAGE vs TIME (START-UP) VO - Output Voltage - V 3 VOUT1 = 3.3 V IO = 1 A 2 CO = 22 mF VIN1 = 4.3 V 1 EN2 = High 0 Enable Voltage - V Enable Voltage - V VO - Output Voltage - V 4 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2 1 0 VOUT2 = 1.
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TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 www.ti.com SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 TYPICAL CHARACTERISTICS (continued) TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE(1) vs OUTPUT CURRENT TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE(1) vs OUTPUT CURRENT 10 10 VOUT1 = 3.3 V CO = 22 mF ESR - Equivalent Series Resistance - W ESR - Equivalent Series Resistance - W VOUT1 = 3.3 V REGION OF INSTABILITY 1 0.1 50 mW CO = 220 mF REGION OF INSTABILITY 1 0.
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TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 www.ti.com THERMAL INFORMATION Thermally-Enhanced TSSOP-24 (PWP— PowerPAD™) The thermally-enhanced PWP package is based on the 24-pin TSSOP, but includes a thermal pad [see Figure 33(c)] to provide an effective thermal contact between the IC and the printed wiring board (PWB). Traditionally, surface mount and power have been mutually exclusive terms.
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TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 www.ti.com SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 The thermal pad is directly connected to the substrate of the IC, which for the TPS704xx series is a secondary electrical connection to device ground. The heat-sink surface that is added to the PWP can be a ground plane or left electrically isolated. In TO220-type surface-mount packages, the thermal connection is also the primary electrical connection for a given terminal which is not always ground.
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TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 www.ti.com 3.5 3.5 TA = 25°C TA = 55°C 300 ft/min 3 PD - Power Dissipation Limit - W PD - Power Dissipation Limit - W 3 150 ft/min 2.5 2 Natural Convection 1.5 1 0.5 0 300 ft/min 2.5 2 150 ft/min 1.5 Natural Convection 1 0.5 0 0.3 2 4 Copper Heatsink Size - cm 0 8 6 2 0 2 0.3 4 6 Copper Heatsink Size - cm (a) 8 2 (b) 3.5 TA = 105°C PD - Power Dissipation Limit - W 3 2.5 2 1.
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TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 www.ti.com SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 Figure 36 is an example of a thermally-enhanced PWB layout for use with the new PWP package. This board configuration was used in the thermal experiments that generated the power ratings shown in Figure 34 and Figure 35. As discussed earlier, copper has been added on the PWB to conduct heat away from the device. RqJA for this assembly is illustrated in Figure 34 as a function of heat-sink area.
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TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 www.ti.com Comparing PD(total) with PD(max) reveals that the power dissipation in this example does not exceed the calculated limit. When it does, one of two corrective actions should be made: raising the power-dissipation limit by increasing the airflow or the heat-sink area, or lowering the internal power dissipation of the regulator by reducing the input voltage or the load current.
PAGE 27
TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 www.ti.com SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 APPLICATION INFORMATION TPS704xxPWP (Fixed Output Option) Sequencing Timing Diagrams This section provides a number of timing diagrams showing how this device functions in different configurations. VOUT1 VIN VOUT1 VIN1 0.22 mF VSENSE1 Application condition: VIN1 and VIN2 are tied to the same fixed input voltage greater than VUVLO. PG2 is tied to MR.
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TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 www.ti.com Application condition: VIN1 and VIN2 are tied to the same fixed input voltage greater than VUVLO. MR is initially logic high but is eventually toggled. TPS704xxPWP (Fixed Output Option) VIN EN1 and EN2 are initially high; therefore, both regulators are off, and PG1 and PG2 are at logic low. Since VIN1 is greater than VUVLO and MR is at logic high, RESET is also at logic high.
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TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 www.ti.com SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 Application condition: VIN1 and VIN2 are tied to same fixed input voltage greater than VUVLO. PG1 is tied to MR. EN1 and EN2 are initially high; therefore, both regulators are off, and PG1 (tied to MR) and PG2 are at logic low. Since MR is at logic low, RESET is also at logic low. When EN2 is taken to logic low, VOUT2 turns on. Later, when EN1 is taken to logic low, VOUT1 turns on.
PAGE 30
TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 www.ti.com APPLICATION INFORMATION Input Capacitor For a typical application, a ceramic input bypass capacitor (0.22 mF to 1 mF) is recommended. This capacitor should be as close to the input pins as possible. Due to the impedance of the input supply, large transient currents cause the input voltage to droop. If this droop causes the input voltage to drop below the UVLO threshold, the device turns off.
PAGE 31
TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 www.ti.com SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 Programming the TPS70402 Adjustable LDO Regulator The output voltage of the TPS70402 adjustable regulators is programmed using external resistor dividers as shown in Figure 41. Resistors R1 and R2 should be chosen for approximately a 50-mA divider current. Lower value resistors can be used, but offer no inherent advantage and waste more power.
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TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (February 2010) to Revision F • Page Changed Tube transport media, quatity values from 70 to 60 in Ordering Information table ..............................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 10-Jun-2014 Status (1) TPS70458PWPRG4 ACTIVE Package Type Package Pins Package Drawing Qty HTSSOP PWP 24 2000 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Op Temp (°C) Device Marking (4/5) -40 to 125 PT70458 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
PAGE 35
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) TPS70402PWPR HTSSOP PWP 24 2000 330.0 16.4 TPS70445PWPR HTSSOP PWP 24 2000 330.0 TPS70448PWPR HTSSOP PWP 24 2000 330.0 TPS70451PWPR HTSSOP PWP 24 2000 TPS70458PWPR HTSSOP PWP 24 2000 6.95 8.3 1.6 8.0 16.0 Q1 16.4 6.95 8.3 1.6 8.0 16.
PAGE 36
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS70402PWPR HTSSOP PWP 24 2000 367.0 367.0 38.0 TPS70445PWPR HTSSOP PWP 24 2000 367.0 367.0 38.0 TPS70448PWPR HTSSOP PWP 24 2000 367.0 367.0 38.0 TPS70451PWPR HTSSOP PWP 24 2000 367.0 367.0 38.0 TPS70458PWPR HTSSOP PWP 24 2000 367.0 367.0 38.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.