Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - LDO voltage regulator Positivbe, adjustable HTSSOP 20

FEATURES DESCRIPTION

PWP PACKAGE

(TOP VIEW)

IN1

MR1

MR2

SEQ

GND

IN2

OUT1

SENSE1

/FB1

PG1

RESET

SENSE2

/FB2

OUT2

TPS70745, TPS70748

TPS70751, TPS70758

TPS70702

SLVS291D – MAY 2000 – REVISED DECEMBER 2007

www.ti.com

Dual-Output, Low Dropout Voltage Regulators

with Power-Up Sequencing for Split-Voltage DSP Systems

• Dual Output Voltages for Split-Supply

TPS707xx family devices are designed to provide a

Applications

complete power management solution for the

TMS320™ DSP family, processor power, ASIC,

• Selectable Power-Up Sequencing for DSP

FPGA, and digital applications where dual output

Applications (See Part Number TPS708xx for

voltage regulators are required. Easy programmability

Independent Enable Outputs)

of the sequencing function makes the TPS707xx

• Output Current Range of 250mA on Regulator

family ideal for any TMS320 DSP applications with

1 and 125mA on Regulator 2

power sequencing requirements. Differentiated

features, such as accuracy, fast transient response,

• Fast Transient Response

SVS supervisory circuit, manual reset inputs, and an

• Voltage Options: 3.3V/2.5V, 3.3V/1.8V,

enable function, provide a complete system solution.

3.3V/1.5V, 3.3V/1.2V, and Dual Adjustable

Outputs The TPS707xx family of voltage regulators offer very

low dropout voltage and dual outputs with power-up

• Open Drain Power-On Reset with 120ms Delay

sequence control, which is designed primarily for

• Open Drain Power Good for Regulator 1

DSP applications. These devices have extremely low

• Ultralow 190 µ A (typ) Quiescent Current

noise output performance without using any added

filter bypass capacitors and are designed to have a

• 1 µ A Input Current During Standby

fast transient response and be stable with 10 µ F low

• Low Noise: 65 µ V

RMS

Without Bypass Capacitor

ESR capacitors.

• Quick Output Capacitor Discharge Feature

These devices have fixed 3.3V/2.5V, 3.3V/1.8V,

• Two Manual Reset Inputs

3.3V/1.5V, 3.3V/1.2V, and adjustable/adjustable

• 2% Accuracy Over Load and Temperature

voltage options. Regulator 1 can support up to

250mA, and regulator 2 can support up to 125mA.

• Undervoltage Lockout (UVLO) Feature

Separate voltage inputs allow the designer to

• 20-Pin PowerPAD™ TSSOP Package

configure the source power.

• Thermal Shutdown Protection

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2 PowerPAD, TMS320 are trademarks of Texas Instruments.

3 All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (40 pages)

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TPS70745, TPS70748 TPS70751, TPS70758 TPS70702 www.ti.com SLVS291D – MAY 2000 – REVISED DECEMBER 2007 Dual-Output, Low Dropout Voltage Regulators with Power-Up Sequencing for Split-Voltage DSP Systems FEATURES 1 • Dual Output Voltages for Split-Supply Applications • Selectable Power-Up Sequencing for DSP Applications (See Part Number TPS708xx for Independent Enable Outputs) • Output Current Range of 250mA on Regulator 1 and 125mA on Regulator 2 • Fast Transient Response • Voltage Options: 3.3V/2.5V, 3.
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TPS70745, TPS70748 TPS70751, TPS70758 TPS70702 www.ti.com SLVS291D – MAY 2000 – REVISED DECEMBER 2007 TPS70751 PWP 5V VIN1 0.1 mF 3.3 V VOUT1 250 kW PG1 PG1 MR2 MR2 >2 V <0.7 V 0.1 mF >2 V EN 250 kW RESET RESET EN MR1 I/O 10 mF VSENSE1 VIN2 DSP MR1 >2 V <0.7 V <0.7 V VSENSE2 SEQ 1.8 V VOUT2 Core 10 mF Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 83mV on regulator 1) and is directly proportional to the output current.
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TPS70745, TPS70748 TPS70751, TPS70758 TPS70702 www.ti.com SLVS291D – MAY 2000 – REVISED DECEMBER 2007 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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TPS70745, TPS70748 TPS70751, TPS70758 TPS70702 www.ti.com SLVS291D – MAY 2000 – REVISED DECEMBER 2007 RECOMMENDED OPERATING CONDITIONS Over operating temperature range (unless otherwise noted). Input voltage, VI (1)(regulator 1 and 2) Output current, IO (regulator 1) Output current, IO (regulator 2) MIN MAX 2.7 6 UNIT 0 250 mA mA V 0 125 Output voltage range (for adjustable option) 1.22 5.
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TPS70745, TPS70748 TPS70751, TPS70758 TPS70702 www.ti.com SLVS291D – MAY 2000 – REVISED DECEMBER 2007 ELECTRICAL CHARACTERISTICS (continued) Over recommended operating junction temperature range (TJ = –40°C to +125°C), VIN1 or VIN2 = VOUT(nom) + 1V, IO = 1mA, EN = 0V, and CO = 33µF (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX 1.0 1.
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TPS70745, TPS70748 TPS70751, TPS70758 TPS70702 www.ti.com SLVS291D – MAY 2000 – REVISED DECEMBER 2007 ELECTRICAL CHARACTERISTICS (continued) Over recommended operating junction temperature range (TJ = –40°C to +125°C), VIN1 or VIN2 = VOUT(nom) + 1V, IO = 1mA, EN = 0V, and CO = 33µF (unless otherwise noted).
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TPS70745, TPS70748 TPS70751, TPS70758 TPS70702 www.ti.com SLVS291D – MAY 2000 – REVISED DECEMBER 2007 DEVICE INFORMATION Fixed Voltage Version VOUT1 (2 Pins) VIN1 (2 Pins) - UVLO1 Comp 10 kW Current Sense + 2.5 V (see Note A) GND Reference Thermal Shutdown + ENA_1 Vref FB1 Vref FB1 - 0.95 x Vref + PG Comp VOUT2 UV Comp EN VSENSE1 ENA_1 FB2 - 0.83 x Vref + FB1 - 0.83 x Vref + FB2 - 0.
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TPS70745, TPS70748 TPS70751, TPS70758 TPS70702 www.ti.com SLVS291D – MAY 2000 – REVISED DECEMBER 2007 Adjustable Voltage Version VOUT1 (2 Pins) VIN1 (2 Pins) - UVLO Comp Current Sense (see Note A) GND Reference Thermal Shutdown + ENA_1 Vref Vref FB1 - 0.95 x Vref + PG Comp VOUT2 UV Comp EN FB2 - 0.83 x Vref + FB1 - 0.83 x Vref + FB2 - 0.
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TPS70745, TPS70748 TPS70751, TPS70758 TPS70702 www.ti.com SLVS291D – MAY 2000 – REVISED DECEMBER 2007 RESET Timing Diagram (with VIN1 Powered Up) VIN2 VRES (see Note A) VRES t VOUT2 VIT +(see Note B) VIT +(see Note B) Threshold Voltage VIT − (see Note B) Î Î Î Î Î Î RESET Output Output Undefined VIT − (see Note B) t 120 ms Delay Î Î Î Î Î Î 120 ms Delay Output Undefined t NOTES: A. VRES is the minimum input voltage for a valid RESET.
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TPS70745, TPS70748 TPS70751, TPS70758 TPS70702 www.ti.com SLVS291D – MAY 2000 – REVISED DECEMBER 2007 Table 1. TERMINAL FUNCTIONS TERMINAL NAME NO.
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www.ti.com TPS70745, TPS70748 TPS70751, TPS70758 TPS70702 SLVS291D – MAY 2000 – REVISED DECEMBER 2007 Power-Good The PG1 is an open drain, active high output terminal that indicates the status of the VOUT1 regulator. When the VOUT1 reaches 95% of its regulated voltage, PG1 goes to a high impedance state. It goes to a low impedance state when it is pulled below 95% (for example, doing an overload condition) of its regulated voltage. The open drain output of the PG1 terminal requires a pull-up resistor.
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TPS70745, TPS70748 TPS70751, TPS70758 TPS70702 www.ti.com SLVS291D – MAY 2000 – REVISED DECEMBER 2007 TYPICAL CHARACTERISTICS Table 2.
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TPS70745, TPS70748 TPS70751, TPS70758 TPS70702 www.ti.com SLVS291D – MAY 2000 – REVISED DECEMBER 2007 TPS70745 OUTPUT VOLTAGE vs OUTPUT CURRENT TPS70751 OUTPUT VOLTAGE vs TEMPERATURE 3.286 1.201 VIN2 = 2.7 V TA = 25°C VOUT2 1.200 3.284 VIN1 = 4.3 V IO = 1 mA VOUT1 VO − Output Voltage − V VO − Output Voltage − V 3.282 1.199 1.198 1.197 3.280 3.278 3.276 3.274 3.272 1.196 3.270 1.195 0 0.05 0.1 0.15 0.2 0.25 3.268 −40 −25 −10 0.
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TPS70745, TPS70748 TPS70751, TPS70758 TPS70702 www.ti.com SLVS291D – MAY 2000 – REVISED DECEMBER 2007 TPS70751 OUTPUT VOLTAGE vs TEMPERATURE GROUND CURRENT vs JUNCTION TEMPERATURE 210 1.799 VIN2 = 2.8 V IO = 250 mA VOUT2 1.798 Regulator 1 and Regulator 2 200 IOUT1 = 1 mA IOUT2 = 1 mA Ground Current − µ A VO − Output Voltage − V 1.797 1.796 1.795 1.794 1.793 190 180 IOUT1 = 250 mA IOUT2 = 500 mA 170 1.792 160 1.791 1.
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TPS70745, TPS70748 TPS70751, TPS70758 TPS70702 www.ti.com SLVS291D – MAY 2000 – REVISED DECEMBER 2007 TPS70751 POWER-SUPPLY REJECTION RATIO vs FREQUENCY TPS70751 POWER-SUPPLY REJECTION RATIO vs FREQUENCY 10 IO = 10 mA CO = 22 µF VOUT2 −20 PSRR − Power Supply Rejection Ratio − dB PSRR − Power Supply Rejection Ratio − dB −10 −30 −40 −50 −60 −70 −80 −90 10 100 1k 10 k f − Frequency − Hz 100 k −30 −40 −50 −60 10 100 1k 10 k f − Frequency − Hz 100 k Figure 12.
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TPS70745, TPS70748 TPS70751, TPS70758 TPS70702 www.ti.com SLVS291D – MAY 2000 – REVISED DECEMBER 2007 OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY 10 VIN2 = 2.8 V VOUT2 = 1.8 V IO = 10 mA Output Spectral Noise Density − µV Hz Output Spectral Noise Density − µV Hz 10 1 0.1 0.01 100 1k 10 k f − Frequency − Hz 0.1 1k 10 k f − Frequency − Hz Figure 15. Figure 16.
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TPS70745, TPS70748 TPS70751, TPS70758 TPS70702 www.ti.com SLVS291D – MAY 2000 – REVISED DECEMBER 2007 OUTPUT IMPEDANCE vs FREQUENCY OUTPUT IMPEDANCE vs FREQUENCY 100 CO = 33 mF IO = 250 mA VO = 1.8 V TA = 25°C 10 Z O - Output Impedance - W Z O - Output Impedance - W 100 1 0.1 0.01 10 100 1k 10 k 100 k 1M 10 1 0.1 0.01 10 M CO = 33 mF IO = 10 mA VO = 1.8 V TA = 25°C 10 100 100 k 10 k f - Frequency - Hz Figure 19. Figure 20.
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TPS70745, TPS70748 TPS70751, TPS70758 TPS70702 www.ti.com SLVS291D – MAY 2000 – REVISED DECEMBER 2007 TPS70702 DROPOUT VOLTAGE vs INPUT VOLTAGE 300 TPS70702 DROPOUT VOLTAGE vs INPUT VOLTAGE 500 IO = 500 mA VIN1 IO = 250 mA VIN2 250 400 Dropout Voltage − mV Dropout Voltage − mV TJ = 125°C 200 TJ = 25°C 150 100 TJ= −40°C TJ = 125°C 300 TJ = 25°C 200 TJ = − 40°C 100 50 0 2.5 3 3.5 4 4.5 5 0 2.5 5.
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TPS70745, TPS70748 TPS70751, TPS70758 TPS70702 www.ti.com SLVS291D – MAY 2000 – REVISED DECEMBER 2007 VI − Input Voltage − V 5.3 4.3 0 IO = 500 mA Co = 33 µF VOUT1 −50 20 40 60 2 10 0 IO = 250 mA Co = 33 µF VOUT2 −10 0 20 40 60 80 100 120 140 160 180 200 t − Time − µs Figure 28. OUTPUT VOLTAGE AND ENABLE VOLTAGE vs TIME (START-UP) OUTPUT VOLTAGE AND ENABLE VOLTAGE vs TIME (START-UP) 1 0 5 0 −5 0 2.8 Figure 27. VO = 3.3 V Co = 33 µF IO = 500 mA VOUT1 SEQ = Low 3 3.
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TPS70745, TPS70748 TPS70751, TPS70758 TPS70702 www.ti.com SLVS291D – MAY 2000 – REVISED DECEMBER 2007 TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE(1) vs OUTPUT CURRENT 10 REGION OF INSTABILITY REGION OF INSTABILITY ESR - Equivalent Series Resistance - W ESR - Equivalent Series Resistance - W 10 TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE(1) vs OUTPUT CURRENT V O = 3.3 V CO = 10 mF TJ = 25°C 1 0.1 50 mW REGION OF INSTABILITY VO = 3.3 V V O = 3.3 V CO C O = 6.
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TPS70745, TPS70748 TPS70751, TPS70758 TPS70702 www.ti.com SLVS291D – MAY 2000 – REVISED DECEMBER 2007 VI To Load IN OUT + EN CO GND R RL ESR Figure 35.
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TPS70745, TPS70748 TPS70751, TPS70758 TPS70702 www.ti.com SLVS291D – MAY 2000 – REVISED DECEMBER 2007 APPLICATION INFORMATION TPS707xxPWP (Fixed Output Option) Sequencing Timing Diagrams This section provides a number of timing diagrams showing how this device functions in different configurations. VOUT1 VI VIN1 0.
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TPS70745, TPS70748 TPS70751, TPS70758 TPS70702 www.ti.com SLVS291D – MAY 2000 – REVISED DECEMBER 2007 Application condition: VIN1 and VIN2 are tied to the same fixed input voltage greater than the VUVLO; SEQ is tied to logic high; PG1 is tied to MR2; MR1 is left unconnected and is therefore at logic high. EN is initially high; therefore, both regulators are off and PG1 and RESET are at logic low. With SEQ at logic high, when EN is taken to logic low, VOUT2 turns on.
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TPS70745, TPS70748 TPS70751, TPS70758 TPS70702 www.ti.com SLVS291D – MAY 2000 – REVISED DECEMBER 2007 Application condition: VIN1 and VIN2 are tied to the same fixed input voltage greater than the VUVLO; SEQ is tied to logic high; PG1 is tied to MR2; MR1 is initially at logic high but is eventually toggled. EN is initially high; therefore, both regulators are off and PG1 and RESET are at logic low. With SEQ at logic high, when EN is taken low, VOUT2 turns on.
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TPS70745, TPS70748 TPS70751, TPS70758 TPS70702 www.ti.com SLVS291D – MAY 2000 – REVISED DECEMBER 2007 Application condition: VIN1 and VIN2 are tied to the same fixed input voltage greater than the VUVLO; SEQ is tied to logic high; PG1 is tied to MR2; MR1 is left unconnected and is therefore at logic high. EN is initially high; therefore, both regulators are off and PG1 and RESET are at logic low. With SEQ at logic high, when EN is taken low, VOUT2 turns on.
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TPS70745, TPS70748 TPS70751, TPS70758 TPS70702 www.ti.com SLVS291D – MAY 2000 – REVISED DECEMBER 2007 Application condition: VIN1 and VIN2 are tied to the same fixed input voltage greater than the VUVLO; SEQ is tied to logic high; PG1 is tied to MR2; MR1 is left unconnected and is therefore at logic high. EN is initially high; therefore, both regulators are off and PG1 and RESET are at logic low. With SEQ at logic high, when EN is taken low, VOUT2 turns on.
PAGE 27
TPS70745, TPS70748 TPS70751, TPS70758 TPS70702 www.ti.com SLVS291D – MAY 2000 – REVISED DECEMBER 2007 Split Voltage DSP Application Figure 41 shows a typical application where the TPS70751 is powering up a DSP. In this application, by grounding the SEQ pin, VOUT1 (I/O) is powered up first, and then VOUT2 (core). TPS70751 PWP 5V VIN1 0.1 mF 10 mF VSENSE1 250 kW MR2 MR2 >2 V 5V >2 V <0.7 V 0.1 mF 250 kW RESET RESET EN MR1 EN I/O PG1 PG1 VIN2 DSP 3.3 V VOUT1 MR1 >2 V <0.7 V <0.
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TPS70745, TPS70748 TPS70751, TPS70758 TPS70702 www.ti.com SLVS291D – MAY 2000 – REVISED DECEMBER 2007 Figure 42 shows a typical application where the TPS70751 is powering up a DSP. In this application, by pulling up the SEQ pin, VOUT2 (core) is powered up first, and then VOUT1 (I/O). TPS70751 PWP 5V VIN1 0.1 mF DSP 3.3 V VOUT1 10 mF VSENSE1 I/O 250 kW 5V PG1 PG1 VIN2 0.1 mF >2 V EN MR2 MR2 250 kW RESET RESET EN <0.7 V MR1 MR1 VSENSE2 SEQ 1.
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TPS70745, TPS70748 TPS70751, TPS70758 TPS70702 www.ti.com SLVS291D – MAY 2000 – REVISED DECEMBER 2007 Input Capacitor For a typical application, an input bypass capacitor (0.1µF to 1µF) is recommended. This capacitor filters any high-frequency noise generated in the line. For fast transient conditions where droop at the input of the LDO may occur because of high inrush current, it is recommended to place a larger capacitor at the input as well.
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TPS70745, TPS70748 TPS70751, TPS70758 TPS70702 www.ti.com SLVS291D – MAY 2000 – REVISED DECEMBER 2007 Figure 44 shows the output capacitor and its parasitic resistances in a typical LDO output stage. Iout LDO + VESR RESR − Vin RLOAD Vout Cout Figure 44. LDO Output Stage with Parasitic Resistances ESR In steady state (dc state condition), the load current is supplied by the LDO (solid arrow) and the voltage across the capacitor is the same as the output voltage (V(CO) = VOUT).
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TPS70745, TPS70748 TPS70751, TPS70758 TPS70702 www.ti.com SLVS291D – MAY 2000 – REVISED DECEMBER 2007 IO VO 1 2 ESR 1 3 ESR 2 ESR 3 t1 t2 Figure 45. Correlation of Different ESRs and Their Influence on the Regulation of VO at a Load Step from Low-to-High Output Current Figure 45 also shows the impact of different ESRs on the output voltage. The left brackets show different levels of ESRs where number 1 displays the lowest and number 3 displays the highest ESR.
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TPS70745, TPS70748 TPS70751, TPS70758 TPS70702 www.ti.com SLVS291D – MAY 2000 – REVISED DECEMBER 2007 OUTPUT VOLTAGE PROGRAMMING GUIDE TPS70702 VI OUTPUT VOLTAGE IN 0.1 mF >2.7 V EN OUT VO <0.5V R1 + R1 R2 UNIT 2.5 V 174 169 kW 3.3 V 287 169 kW 3.6 V 324 169 kW FB GND R2 Figure 46.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 27-Aug-2009 provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) TPS70702PWPR HTSSOP PWP 20 2000 330.0 16.4 TPS70751PWPR HTSSOP PWP 20 2000 330.0 16.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.95 7.1 1.6 8.0 16.0 Q1 6.95 7.1 1.6 8.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS70702PWPR HTSSOP PWP 20 2000 367.0 367.0 38.0 TPS70751PWPR HTSSOP PWP 20 2000 367.0 367.0 38.
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