Datasheet

TPS714xx
SBVS116C –DECEMBER 2008– REVISED MARCH 2011 www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
AVAILABLE OPTIONS
(1)
PRODUCT V
OUT
(2)
XX is nominal output voltage (for example 33 = 3.3V, 01 = Adjustable)
TPS714xxyyyz YYY is Package Designator
Z is Package Quantity
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Custom output voltages are available on a quick-turn basis for prototyping. Production quantities are available; minimum package order
quantities apply. Contact factory for details and availability.
ABSOLUTE MAXIMUM RATINGS
Over operating temperature range, unless otherwise noted.
(1)
PARAMETER TPS714xx UNIT
V
IN
range –0.3 to +24 V
V
OUT
range - 0.3 to +9.9 V
V
FB range
-0.3 to +4 V
Peak output current Internally limited
Continuous total power dissipation See Power Dissipation Rating table
Junction temperature range, T
J
–40 to +125 °C
Storage temperature range –65 to +150 °C
Human body model (HBM) 2 kV
ESD rating
Charged device model (CDM) 500 V
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
POWER DISSIPATION RATING TABLE
DERATING FACTOR T
A
≤ 25°C POWER T
A
= +70°C POWER T
A
= +85°C POWER
BOARD PACKAGE R
θJA
°C/W ABOVE T
A
= +25°C RATING RATING RATING
High-K
(1)
DCK 315 3.18mW/°C 320mW 175mW 100mW
High-K
(1)
DRV 65 15.4mW/°C 1.54W 850mW 0.62W
(1) The JEDEC High-K (2s2p) board design used to derive this data was a 3 inch × 3 inch, multilayer board with 1-ounce internal power and
ground planes and 2-ounce copper traces on top and bottom of the board.
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