Datasheet

TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics, I
O
= 10 mA, EN = 0 V, C
O
= 4.7 µF (CSR
†
= 1 Ω), SENSE/FB shorted to OUT
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
‡
T
J
TPS72xxQ
UNIT
PARAMETER
TEST
CONDITIONS
‡
T
J
MIN TYP MAX
UNIT
Ground current (active mode)
EN ≤ 0.5 V
,
V
I
= V
O
+ 1 V
,
25°C 180 225
µA
Gro
u
nd
c
u
rrent
(acti
v
e
mode)
EN
≤
0.5
V,
0 mA ≤ I
O
≤ 250 mA
V
I
V
O
+
1
V,
–40°C to 125°C 325
µ
A
In
p
ut current (standby mode)
EN V
3V≤ V ≤ 10 V
25°C 0.5
µA
Inp
u
t
c
u
rrent
(standb
y
mode)
EN
=
V
I
,
3
V
≤
V
I
≤
10
V
–40°C to 125°C 1
µ
A
Out
p
ut current limit threshold
V
O
=0V
V
I
=10V
25°C 0.6 1
A
O
u
tp
u
t
c
u
rrent
limit
threshold
V
O
=
0
V
V
I
=
10
V
–40°C to 125°C 1.5
A
Pass-element leakage current in
EN V
I
3V≤ V
I
≤ 10 V
25°C 0.5
µA
g
standby mode
EN
=
V
I
,
3
V
≤
V
I
≤
10
V
–40°C to 125°C 1
µ
A
PG leakage current
V
PG
=10V
Normal o
p
eration
25°C 0.5
µA
PG
l
ea
k
age curren
t
V
PG
=
10
V
,
Normal
operation
–40°C to 125°C 0.5
µ
A
Output voltage temperature coefficient –40°C to 125°C 31 75 ppm/°C
Thermal shutdown junction temperature 165 °C
EN logic high (standby mode)
3 V ≤ V
I
≤ 6 V
40
°
Cto125
°
C
2
V
EN
l
og
i
c
hi
g
h
(
s
t
an
db
y mo
d
e
)
6 V ≤ V
I
≤ 10 V
–
40°C
to
125°C
2.7
V
EN logic low (active mode)
3V≤ V
I
≤ 10 V
25°C 0.5
V
EN
l
og
i
c
l
ow
(
ac
ti
ve mo
d
e
)
3
V
≤
V
I
≤
10
V
–40°C to 125°C 0.5
V
EN hysteresis voltage 25°C 50 mV
EN input current
0V≤ V
I
≤ 10 V
25°C –0.5 0.5
µA
EN
i
npu
t
curren
t
0
V
≤
V
I
≤
10
V
–40°C to 125°C –0.5 0.5
µ
A
Minimum V
I
for active
p
ass element
25°C 1.9 2.5
V
Minim
u
m
V
I
for
acti
v
e
pass
element
–40°C to 125°C 2.5
V
Minimum V
I
for valid PG
I
PG
= 300 µA
25°C 1.1 1.5
V
Minim
u
m
V
I
for
v
alid
PG
I
PG
=
300
µ
A
–40°C to 125°C 1.9
V
†
CSR(compensation series resistance) refers to the total series resistance, including the equivalent series resistance (ESR) of the capacitor, any
series resistance added externally, and PWB trace resistance to C
O
.
‡
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.