Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - LDO voltage regulator Positivbe, adjustable VQFN 20 (5x5)

TPS742xx

1V/div

Time(1ms/div)

C =0 F

C =0.001 F

C =0.0047 F

OUT

1.2V

ADJUSTABLEVOLTAGEVERSION

FIXEDVOLTAGEVERSION

TPS74201

GND

IN PG

BIAS

OUT

Optional

1 Fm

BIAS

1 Fm

TPS742xx

GND

SNS

IN PG

BIAS

OUT

Optional

1 Fm

BIAS

1 Fm

TPS742xx

www.ti.com

SBVS064L –DECEMBER 2005–REVISED NOVEMBER 2010

1.5A Ultra-LDO with Programmable Soft-Start

Check for Samples: TPS742xx

FEATURES

DESCRIPTION

• Soft-Start (SS) Pin Provides a Linear Startup

The TPS742xx low-dropout (LDO) linear regulators

with Ramp Time Set by External Capacitor

provide an easy-to-use robust power management

• 1% Accuracy Over Line, Load, and

solution for a wide variety of applications.

Temperature

User-programmable soft-start minimizes stress on the

• Supports Input Voltages as Low as 0.9V with

input power source by reducing capacitive inrush

External Bias Supply

current on start-up. The soft-start is monotonic and

well suited for powering many different types of

• Adjustable Output (0.8V to 3.6V)

processors and ASICs. The enable input and

• Fixed Output (0.9V to 3.6V)

power-good output allow easy sequencing with

• Ultra-Low Dropout: 55mV at 1.5A (typ)

external regulators. This complete flexibility permits

the user to configure a solution that will meet the

• Stable with Any or No Output Capacitor

sequencing requirements of FPGAs, DSPs, and other

• Excellent Transient Response

applications with special start-up requirements.

• Available in 5mm × 5mm × 1mm QFN and

A precision reference and error amplifier deliver 1%

DDPAK-7 Packages

accuracy over load, line, temperature, and process.

• Open-Drain Power-Good (5 × 5 QFN)

Each LDO is stable with low-cost ceramic output

• Active High Enable

capacitors and the family is fully specified from –40°C

to +125°C. The TPS742xx is offered in a small (5mm

× 5mm) QFN package, yielding a highly compact total

APPLICATIONS

solution size. For applications that require additional

• FPGA Applications

power dissipation, the DDPAK (KTW) package is also

• DSP Core and I/O Voltages

available.

• Post-Regulation Applications

• Applications with Special Start-Up Time or

Sequencing Requirements

• Hot-Swap and Inrush Controls

Figure 1. Turn-On Response

Figure 2. Typical Application Circuits

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (28 pages)

PAGE 1
TPS742xx TP S7 42x x TP S7 42 xx www.ti.com SBVS064L – DECEMBER 2005 – REVISED NOVEMBER 2010 1.5A Ultra-LDO with Programmable Soft-Start Check for Samples: TPS742xx FEATURES 1 • 2 • • • • • • • • • • Soft-Start (SS) Pin Provides a Linear Startup with Ramp Time Set by External Capacitor 1% Accuracy Over Line, Load, and Temperature Supports Input Voltages as Low as 0.9V with External Bias Supply Adjustable Output (0.8V to 3.6V) Fixed Output (0.9V to 3.6V) Ultra-Low Dropout: 55mV at 1.
PAGE 2
TPS742xx SBVS064L – DECEMBER 2005 – REVISED NOVEMBER 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
PAGE 3
TPS742xx www.ti.com SBVS064L – DECEMBER 2005 – REVISED NOVEMBER 2010 THERMAL INFORMATION TPS742xx (3) THERMAL METRIC (1) (2) RGW (20 PINS) KTW (7 PINS) qJA Junction-to-ambient thermal resistance (4) 30.5 20.1 qJCtop Junction-to-case (top) thermal resistance (5) 27.6 2.
PAGE 4
TPS742xx SBVS064L – DECEMBER 2005 – REVISED NOVEMBER 2010 www.ti.com ELECTRICAL CHARACTERISTICS At VEN = 1.1V, VIN = VOUT + 0.3V, CIN = CBIAS = 0.1mF, COUT = 10mF, IOUT = 50mA, VBIAS = 5.0V, and TJ = –40°C to +125°C, unless otherwise noted. Typical values are at TJ = +25°C. TPS742xx PARAMETER TEST CONDITIONS VIN Input voltage range MIN VBIAS Bias pin voltage range VREF Internal reference (Adj.) VOUT 0.796 Output voltage range VIN = 5V, IOUT = 1.5A, VBIAS = 5V VREF Accuracy (1) 2.
PAGE 5
TPS742xx www.ti.com SBVS064L – DECEMBER 2005 – REVISED NOVEMBER 2010 BLOCK DIAGRAMS IN Current Limit BIAS UVLO OUT Thermal Limit 0.73mA VOUT R1 SS CSS Soft-Start Discharge VOUT = 0.8 x (1 + 0.8V Reference R1 ) R2 FB PG Hysteresis and De-Glitch EN R2 0.9 ´ VREF GND Figure 3. Adjustable Voltage Version IN Current Limit BIAS UVLO OUT VOUT RSMALL SNS Thermal Limit 0.73mA R1 SS CSS Soft-Start Discharge R2 0.8V Reference PG EN Hysteresis and De-Glitch 0.
PAGE 6
TPS742xx SBVS064L – DECEMBER 2005 – REVISED NOVEMBER 2010 www.ti.com Table 1. Standard 1% Resistor Values for Programming the Output Voltage (1) (1) R1 (kΩ) R2 (kΩ) VOUT (V) Short Open 0.8 0.619 4.99 0.9 1.13 4.53 1.0 1.37 4.42 1.05 1.87 4.99 1.1 2.49 4.99 1.2 4.12 4.75 1.5 3.57 2.87 1.8 3.57 1.69 2.5 3.57 1.15 3.3 VOUT = 0.8 × (1 + R1/R2) Table 2. Standard Capacitor Values for Programming the Soft-Start Time (1) tSS(s) = (1) 6 CSS SOFT-START TIME Open 0.
PAGE 7
TPS742xx www.ti.com SBVS064L – DECEMBER 2005 – REVISED NOVEMBER 2010 PIN CONFIGURATIONS IN NC NC NC OUT 5 4 3 2 1 RGW PACKAGE 5 × 5 QFN-20 (TOP VIEW) KTW PACKAGE DDPAK-7 SURFACE-MOUNT IN 6 20 OUT IN 7 19 OUT IN 8 18 OUT PG 9 17 NC BIAS 10 16 FB/SNS 11 12 13 14 15 EN GND NC NC SS TPS742xx GND 1 2 3 4 5 6 7 SS OUT IN EN FB/ GND BIAS SNS PIN DESCRIPTIONS NAME KTW (DDPAK) RGW (QFN) IN 5 5–8 Unregulated input to the device. EN 7 11 Enable pin.
PAGE 8
TPS742xx SBVS064L – DECEMBER 2005 – REVISED NOVEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS At TJ = +25°C, VOUT = 1.5V, VIN = VOUT(TYP) + 0.3V, VBIAS = 3.3V, IOUT = 50mA, EN = VIN, CIN = 1mF, CBIAS = 4.7mF, CSS = 0.01mF, and COUT = 10mF, unless otherwise noted. LOAD REGULATION LOAD REGULATION 1.0 0.050 Referred to IOUT = 50mA 0.9 Referred to IOUT = 50mA 0.025 0.7 0.6 -40°C 0.5 0.4 +25°C 0.3 0 Change in VOUT (%) Change in VOUT (%) 0.8 0.2 +25°C -0.025 -0.050 -40°C -0.075 +125°C -0.
PAGE 9
TPS742xx www.ti.com SBVS064L – DECEMBER 2005 – REVISED NOVEMBER 2010 TYPICAL CHARACTERISTICS (continued) At TJ = +25°C, VOUT = 1.5V, VIN = VOUT(TYP) + 0.3V, VBIAS = 3.3V, IOUT = 50mA, EN = VIN, CIN = 1mF, CBIAS = 4.7mF, CSS = 0.01mF, and COUT = 10mF, unless otherwise noted. VBIAS DROPOUT VOLTAGE vs IOUT AND TEMPERATURE VBIAS PSRR vs FREQUENCY 1400 Power-Supply Rejection Ratio (dB) 80 Dropout Voltage (mV) 1300 1200 +25°C +125°C 1100 1000 -40°C 900 800 700 600 70 60 50 40 30 20 VIN = 1.
PAGE 10
TPS742xx SBVS064L – DECEMBER 2005 – REVISED NOVEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) At TJ = +25°C, VOUT = 1.5V, VIN = VOUT(TYP) + 0.3V, VBIAS = 3.3V, IOUT = 50mA, EN = VIN, CIN = 1mF, CBIAS = 4.7mF, CSS = 0.01mF, and COUT = 10mF, unless otherwise noted. IBIAS vs IOUT AND TEMPERATURE IBIAS vs VBIAS AND VOUT 2.85 3.0 2.8 2.65 2.25 2.05 +25°C 1.85 1.65 +125°C 2.6 2.45 Bias Current (mA) Bias Current (mA) +125°C -40°C 2.4 2.2 +25°C 2.0 1.8 1.6 -40°C 1.4 1.45 1.2 1.
PAGE 11
TPS742xx www.ti.com SBVS064L – DECEMBER 2005 – REVISED NOVEMBER 2010 TYPICAL CHARACTERISTICS (continued) At TJ = +25°C, VOUT = 1.5V, VIN = VOUT(TYP) + 0.3V, VBIAS = 3.3V, IOUT = 50mA, EN = VIN, CIN = 1mF, CBIAS = 4.7mF, CSS = 0.01mF, and COUT = 10mF, unless otherwise noted. VBIAS LINE TRANSIENT (1.5A) VIN LINE TRANSIENT COUT = 1000mF 10mV/div 10mV/div COUT = 2 x 470mF (OSCON) 10mV/div COUT = 100mF COUT = 100mF (Cer.) 10mV/div COUT = 10mF COUT = 10mF (Cer.
PAGE 12
TPS742xx SBVS064L – DECEMBER 2005 – REVISED NOVEMBER 2010 www.ti.com APPLICATION INFORMATION The TPS742xx belongs to a family of new generation ultra-low dropout regulators that feature soft-start and tracking capabilities. These regulators use a low current bias input to power all internal control circuitry, allowing the NMOS pass transistor to regulate very low input and output voltages. The use of an NMOS-pass FET offers several critical advantages for many applications.
PAGE 13
TPS742xx www.ti.com SBVS064L – DECEMBER 2005 – REVISED NOVEMBER 2010 TRANSIENT RESPONSE The TPS742xx was designed to have transient response within 5% for most applications without any output capacitor. In some cases, the transient response may be limited by the transient response of the input supply. This limitation is especially true in applications where the difference between the input and output is less than 300mV.
PAGE 14
TPS742xx SBVS064L – DECEMBER 2005 – REVISED NOVEMBER 2010 www.ti.com PROGRAMMABLE SOFT-START SEQUENCING REQUIREMENTS The TPS742xx features a programmable, monotonic, voltage-controlled soft-start that is set with an external capacitor (CSS). This feature is important for many applications because it eliminates power-up initialization problems when powering FPGAs, DSPs, or other processors.
PAGE 15
TPS742xx www.ti.com SBVS064L – DECEMBER 2005 – REVISED NOVEMBER 2010 OUTPUT NOISE The TPS742xx provides low output noise when a soft-start capacitor is used. When the device reaches the end of the soft-start cycle, the soft-start capacitor serves as a filter for the internal reference. By using a 0.001mF soft-start capacitor, the output noise is reduced by half and is typically 30mVRMS for a 1.2V output (10Hz to 100kHz).
PAGE 16
TPS742xx SBVS064L – DECEMBER 2005 – REVISED NOVEMBER 2010 THERMAL PROTECTION Thermal protection disables the output when the junction temperature rises to approximately +160°C, allowing the device to cool. When the junction temperature cools to approximately +140°C, the output circuitry is enabled. Depending on power dissipation, thermal resistance, and ambient temperature the thermal protection circuit may cycle on and off.
PAGE 17
TPS742xx www.ti.com SBVS064L – DECEMBER 2005 – REVISED NOVEMBER 2010 NOTE: When the device is mounted on an application PCB, it is strongly recommended to use ΨJT and ΨJB, as explained in the Estimating Junction Temperature section. ESTIMATING JUNCTION TEMPERATURE Using the thermal metrics ΨJT and ΨJB, shown in the Thermal Information table, the junction temperature can be estimated with corresponding formulas (given in Equation 6).
PAGE 18
TPS742xx SBVS064L – DECEMBER 2005 – REVISED NOVEMBER 2010 Looking at Figure 35, the RGW package thermal performance has negligible dependency on board size. The KTW package, however, does have a measurable dependency on board size. This dependency exists because the package shape is not point-symmetric to an IC center. In the KTW package, for example (see Figure 34), silicon is not beneath the measuring point of TT which is the center of the X and Y dimension, so that ΨJT has a dependency.
PAGE 19
TPS742xx www.ti.com SBVS064L – DECEMBER 2005 – REVISED NOVEMBER 2010 REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision K (August, 2010) to Revision L • Page Corrected equation for Table 2 .............................................................................................................................................
PAGE 20
PACKAGE OPTION ADDENDUM www.ti.
PAGE 21
PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
PAGE 22
PACKAGE MATERIALS INFORMATION www.ti.com 9-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS74201KTWR DDPAK/ TO-263 KTW 7 500 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2 TPS74201KTWT DDPAK/ TO-263 KTW 7 50 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2 TPS74201RGWR VQFN RGW 20 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.
PAGE 23
PACKAGE MATERIALS INFORMATION www.ti.com 9-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS74201KTWR DDPAK/TO-263 KTW 7 500 367.0 367.0 45.0 TPS74201KTWT DDPAK/TO-263 KTW 7 50 367.0 367.0 45.0 TPS74201RGWR VQFN RGW 20 3000 367.0 367.0 35.0 TPS74201RGWT VQFN RGW 20 250 210.0 185.0 35.
PAGE 24
PAGE 25
PAGE 26
PAGE 27
MECHANICAL DATA MPSF015 – AUGUST 2001 KTW (R-PSFM-G7) PLASTIC FLANGE-MOUNT 0.410 (10,41) 0.385 (9,78) 0.304 (7,72) –A– 0.006 –B– 0.303 (7,70) 0.297 (7,54) 0.0625 (1,587) H 0.055 (1,40) 0.0585 (1,485) 0.300 (7,62) 0.064 (1,63) 0.045 (1,14) 0.252 (6,40) 0.056 (1,42) 0.187 (4,75) 0.370 (9,40) 0.179 (4,55) 0.330 (8,38) H 0.296 (7,52) A 0.605 (15,37) 0.595 (15,11) 0.012 (0,305) C 0.000 (0,00) 0.019 (0,48) 0.104 (2,64) 0.096 (2,44) H 0.017 (0,43) 0.050 (1,27) C C F 0.034 (0,86) 0.
PAGE 28
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.