Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - LDO voltage regulator Positivbe, adjustable TO 263 7

TPS74401

GND

IN PG

OUT

Optional

1 Fm

BIAS

1 Fm

BIAS

TPS744xx

GND

SNS

IN PG

OUT

Optional

1 Fm

BIAS

1 Fm

BIAS

ADJUSTABLEVOLTAGEVERSION

FIXEDVOLTAGEVERSION

1V/div

500mV/div

Time(1ms/div)

C =0 F

C =0.001 F

C =0.0047 F

OUT

1.1V

TPS744xx

www.ti.com

SBVS066O –DECEMBER 2005–REVISED MARCH 2013

3.0A Ultra-LDO with Programmable Soft-Start

Check for Samples: TPS744xx

FEATURES

DESCRIPTION

• Soft-Start (SS) Pin Provides a Linear Startup

The TPS744xx low-dropout (LDO) linear regulators

with Ramp Time Set by External Capacitor

provide an easy-to-use robust power management

• 1% Accuracy Over Line, Load, and

solution for a wide variety of applications. User-

Temperature

programmable soft-start minimizes stress on the input

power source by reducing capacitive inrush current

• Supports Input Voltages as Low as 0.9V with

on start-up. The soft-start is monotonic and well-

External Bias Supply

suited for powering many different types of

• Adjustable Output (0.8V to 3.6V)

processors and ASICs. The enable input and power-

• Fixed Output (0.9V to 3.6V)

good output allow easy sequencing with external

regulators. This complete flexibility permits the user to

• Ultra-Low Dropout: 115mV at 3.0A (typ)

configure a solution that will meet the sequencing

• Stable with Any or No Output Capacitor

requirements of FPGAs, DSPs, and other

• Excellent Transient Response

applications with specific start-up requirements.

• Available in 5mm × 5mm × 1mm QFN and

A precision reference and error amplifier deliver 1%

DDPAK-7 Packages

accuracy over load, line, temperature, and process.

Each LDO is stable with low-cost ceramic output

• Open-Drain Power-Good (QFN only)

capacitors and the device family is fully specified from

• Active High Enable

–40°C to +125°C. The TPS744xx is offered in a small

(5mm × 5mm) QFN package, yielding a highly

APPLICATIONS

compact total solution size. For applications that

• FPGA Applications require additional power dissipation, the DDPAK

(KTW) package is also available.

• DSP Core and I/O Voltages

space

• Post-Regulation Applications

• Applications with Special Start-Up Time or

Sequencing Requirements

• Hot-Swap and Inrush Controls

space

Figure 1. Turn-On Response

Figure 2. Typical Application Circuits

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (29 pages)

PAGE 1
TPS744xx TP S7 44x x TP S7 44 xx www.ti.com SBVS066O – DECEMBER 2005 – REVISED MARCH 2013 3.0A Ultra-LDO with Programmable Soft-Start Check for Samples: TPS744xx FEATURES 1 • 2 • • • • • • • • • • Soft-Start (SS) Pin Provides a Linear Startup with Ramp Time Set by External Capacitor 1% Accuracy Over Line, Load, and Temperature Supports Input Voltages as Low as 0.9V with External Bias Supply Adjustable Output (0.8V to 3.6V) Fixed Output (0.9V to 3.6V) Ultra-Low Dropout: 115mV at 3.
PAGE 2
TPS744xx SBVS066O – DECEMBER 2005 – REVISED MARCH 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
PAGE 3
TPS744xx www.ti.com SBVS066O – DECEMBER 2005 – REVISED MARCH 2013 THERMAL INFORMATION TPS744xx (3) THERMAL METRIC (1) (2) RGW (20 PINS) KTW (7 PINS) θJA Junction-to-ambient thermal resistance (4) 35.4 26.6 θJCtop Junction-to-case (top) thermal resistance (5) 32.4 41.7 θJB Junction-to-board thermal resistance (6) 14.7 12.5 0.4 4.0 (7) ψJT Junction-to-top characterization parameter ψJB Junction-to-board characterization parameter (8) 14.8 7.
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TPS744xx SBVS066O – DECEMBER 2005 – REVISED MARCH 2013 www.ti.com ELECTRICAL CHARACTERISTICS At VEN = 1.1V, VIN = VOUT + 0.3V, CIN = CBIAS = 0.1μF, COUT = 10μF, IOUT = 50mA, VBIAS = 5.0V, and TJ = –40°C to +125°C, unless otherwise noted. Typical values are at TJ = +25°C. TPS744xx PARAMETER MAX UNIT VIN Input voltage range VOUT + VDO 5.5 V VBIAS Bias pin voltage range 2.375 5.25 V 0.804 V 3.6 V ±0.2 +1 % VOUT (NOM) + 0.3 ≤ VIN ≤ 5.5V, QFN 0.0005 0.05 VOUT (NOM) + 0.3 ≤ VIN ≤ 5.
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TPS744xx www.ti.com SBVS066O – DECEMBER 2005 – REVISED MARCH 2013 BLOCK DIAGRAMS IN Current Limit BIAS UVLO OUT Thermal Limit 0.73mA VOUT R1 SS CSS Soft-Start Discharge VOUT = 0.8 x (1 + 0.8V Reference R1 ) R2 FB PG Hysteresis and De-Glitch EN R2 0.9 ´ VREF GND Figure 3. Adjustable Voltage Version IN Current Limit BIAS UVLO OUT VOUT RSMALL SNS Thermal Limit 0.73mA R1 SS CSS Soft-Start Discharge R2 0.8V Reference PG EN Hysteresis and De-Glitch 0.9 ´ VREF GND Figure 4.
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TPS744xx SBVS066O – DECEMBER 2005 – REVISED MARCH 2013 www.ti.com Table 1. Standard 1% Resistor Values for Programming the Output Voltage (1) (1) R1 (kΩ) R2 (kΩ) VOUT (V) Short Open 0.8 0.619 4.99 0.9 1.13 4.53 1.0 1.37 4.42 1.05 1.87 4.99 1.1 2.49 4.99 1.2 4.12 4.75 1.5 3.57 2.87 1.8 3.57 1.69 2.5 3.57 1.15 3.3 VOUT = 0.8 × (1 + R1/R2) Table 2. Standard Capacitor Values for Programming the Soft-Start Time (1) tSS(s) = (1) 6 CSS SOFT-START TIME Open 0.
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TPS744xx www.ti.com SBVS066O – DECEMBER 2005 – REVISED MARCH 2013 PIN CONFIGURATIONS IN NC NC NC OUT 5 4 3 2 1 RGW PACKAGE 5 × 5 QFN-20 (TOP VIEW) KTW PACKAGE DDPAK-7 SURFACE-MOUNT IN 6 20 OUT IN 7 19 OUT IN 8 18 OUT PG 9 17 NC BIAS 10 16 FB/SNS 11 12 13 14 15 EN GND NC NC SS TPS744xx GND 1 2 3 4 5 6 7 SS OUT IN EN FB/ GND BIAS SNS PIN DESCRIPTIONS NAME KTW (DDPAK) RGW (QFN) IN 5 5–8 Unregulated input to the device. EN 7 11 Enable pin.
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TPS744xx SBVS066O – DECEMBER 2005 – REVISED MARCH 2013 www.ti.com TYPICAL CHARACTERISTICS At TJ = +25°C, VOUT = 1.5V, VIN = VOUT(TYP) + 0.3V, VBIAS = 3.3V, IOUT = 50mA, CIN = 1μF, CBIAS = 1μF, CSS = 0.01μF, and COUT = 10μF, unless otherwise noted. LOAD REGULATION 1.0 LOAD REGULATION 0.050 Referred to IOUT = 50mA 0.9 Referred to IOUT = 50mA 0.025 0.7 0.6 -40°C 0.5 0.4 +25°C 0.3 0.2 0.1 0 Change in VOUT (%) Change in VOUT (%) 0.8 -0.025 -40°C -0.075 +125°C -0.100 +125°C 0 +25°C -0.
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TPS744xx www.ti.com SBVS066O – DECEMBER 2005 – REVISED MARCH 2013 TYPICAL CHARACTERISTICS (continued) At TJ = +25°C, VOUT = 1.5V, VIN = VOUT(TYP) + 0.3V, VBIAS = 3.3V, IOUT = 50mA, CIN = 1μF, CBIAS = 1μF, CSS = 0.01μF, and COUT = 10μF, unless otherwise noted.
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TPS744xx SBVS066O – DECEMBER 2005 – REVISED MARCH 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) At TJ = +25°C, VOUT = 1.5V, VIN = VOUT(TYP) + 0.3V, VBIAS = 3.3V, IOUT = 50mA, CIN = 1μF, CBIAS = 1μF, CSS = 0.01μF, and COUT = 10μF, unless otherwise noted. NOISE SPECTRAL DENSITY Output Spectral Noise Density (mV/ÖHz) Output Spectral Noise Density (mV/ÖHz) NOISE SPECTRAL DENSITY 1 IOUT = 3A VOUT = 1.1V CSS = 1nF CSS = 0nF 0.1 CSS = 10nF 0.01 100 1k 10k 1 VOUT = 3.3V VOUT = 2.5V 0.1 VOUT = 1.
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TPS744xx www.ti.com SBVS066O – DECEMBER 2005 – REVISED MARCH 2013 TYPICAL CHARACTERISTICS (continued) At TJ = +25°C, VOUT = 1.5V, VIN = VOUT(TYP) + 0.3V, VBIAS = 3.3V, IOUT = 50mA, CIN = 1μF, CBIAS = 1μF, CSS = 0.01μF, and COUT = 10μF, unless otherwise noted. SOFT-START CHARGING CURRENT (ISS) vs TEMPERATURE LOW-LEVEL PG VOLTAGE vs PG CURRENT 1.0 VOL Low-Level PG Voltage (V) 765 750 ISS (nA) 735 720 705 690 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.
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TPS744xx SBVS066O – DECEMBER 2005 – REVISED MARCH 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) At TJ = +25°C, VOUT = 1.5V, VIN = VOUT(TYP) + 0.3V, VBIAS = 3.3V, IOUT = 50mA, CIN = 1μF, CBIAS = 1μF, CSS = 0.01μF, and COUT = 10μF, unless otherwise noted. LOAD TRANSIENT RESPONSE 50mV/div 50mV/div 50mV/div VBIAS LINE TRANSIENT (3A) COUT = 2 x 470mF (OSCON) COUT = 2 x 470mF (OSCON) 10mV/div COUT = 100mF Cer. COUT = 100mF (Cer.) 10mV/div COUT = 10mF Cer. COUT = 10mF (Cer.
PAGE 13
TPS744xx www.ti.com SBVS066O – DECEMBER 2005 – REVISED MARCH 2013 APPLICATION INFORMATION The TPS744xx belongs to a family of new generation ultra-low dropout regulators that feature soft-start and tracking capabilities. These regulators use a low current bias input to power all internal control circuitry, allowing the NMOS pass transistor to regulate very low input and output voltages. The use of an NMOS-pass FET offers several critical advantages for many applications.
PAGE 14
TPS744xx SBVS066O – DECEMBER 2005 – REVISED MARCH 2013 www.ti.com TRANSIENT RESPONSE The TPS744xx was designed to have transient response within 5% for most applications without any output capacitor. In some cases, the transient response may be limited by the transient response of the input supply. This limitation is especially true in applications where the difference between the input and output is less than 300mV.
PAGE 15
TPS744xx www.ti.com SBVS066O – DECEMBER 2005 – REVISED MARCH 2013 PROGRAMMABLE SOFT-START SEQUENCING REQUIREMENTS The TPS744xx features a programmable, monotonic, voltage-controlled soft-start that is set with an external capacitor (CSS). This feature is important for many applications because it eliminates power-up initialization problems when powering FPGAs, DSPs, or other processors.
PAGE 16
TPS744xx SBVS066O – DECEMBER 2005 – REVISED MARCH 2013 www.ti.com OUTPUT NOISE The TPS744xx provides low output noise when a soft-start capacitor is used. When the device reaches the end of the soft-start cycle, the soft-start capacitor serves as a filter for the internal reference. By using a 0.001μF soft-start capacitor, the output noise is reduced by half and is typically 19μVRMS for a 1.2V output (100Hz to 100kHz).
PAGE 17
TPS744xx www.ti.com THERMAL PROTECTION Thermal protection disables the output when the junction temperature rises to approximately +155°C, allowing the device to cool. When the junction temperature cools to approximately +140°C, the output circuitry is enabled. Depending on power dissipation, thermal resistance, and ambient temperature the thermal protection circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a result of overheating.
PAGE 18
TPS744xx SBVS066O – DECEMBER 2005 – REVISED MARCH 2013 NOTE: When the device is mounted on an application PCB, it is strongly recommended to use ΨJT and ΨJB, as explained in the Estimating Junction Temperature section. ESTIMATING JUNCTION TEMPERATURE Using the thermal metrics ΨJT and ΨJB, shown in the Thermal Information table, the junction temperature can be estimated with corresponding formulas (given in Equation 6). For backwards compatibility, an older θJC,Top parameter is listed as well. www.ti.
PAGE 19
TPS744xx www.ti.com Looking at Figure 37, the RGW package thermal performance has negligible dependency on board size. The KTW package, however, does have a measurable dependency on board size. This dependency exists because the package shape is not point-symmetric to an IC center. In the KTW package, for example (see Figure 36), silicon is not beneath the measuring point of TT which is the center of the X and Y dimension, so that ΨJT has a dependency.
PAGE 20
TPS744xx SBVS066O – DECEMBER 2005 – REVISED MARCH 2013 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision N (December 2012) to Revision O • Changed RGW and KTW values in Thermal Information table ............................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
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PACKAGE MATERIALS INFORMATION www.ti.com 9-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS74401KTWR DDPAK/ TO-263 KTW 7 500 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2 TPS74401KTWT DDPAK/ TO-263 KTW 7 50 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2 TPS74401RGWR VQFN RGW 20 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 9-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS74401KTWR DDPAK/TO-263 KTW 7 500 367.0 367.0 45.0 TPS74401KTWT DDPAK/TO-263 KTW 7 50 367.0 367.0 45.0 TPS74401RGWR VQFN RGW 20 3000 367.0 367.0 35.0 TPS74401RGWT VQFN RGW 20 250 210.0 185.0 35.
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MECHANICAL DATA MPSF015 – AUGUST 2001 KTW (R-PSFM-G7) PLASTIC FLANGE-MOUNT 0.410 (10,41) 0.385 (9,78) 0.304 (7,72) –A– 0.006 –B– 0.303 (7,70) 0.297 (7,54) 0.0625 (1,587) H 0.055 (1,40) 0.0585 (1,485) 0.300 (7,62) 0.064 (1,63) 0.045 (1,14) 0.252 (6,40) 0.056 (1,42) 0.187 (4,75) 0.370 (9,40) 0.179 (4,55) 0.330 (8,38) H 0.296 (7,52) A 0.605 (15,37) 0.595 (15,11) 0.012 (0,305) C 0.000 (0,00) 0.019 (0,48) 0.104 (2,64) 0.096 (2,44) H 0.017 (0,43) 0.050 (1,27) C C F 0.034 (0,86) 0.
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