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TPS75003-EP

www.ti.com

SGLS311A –DECEMBER 2006– REVISED MARCH 2011

Triple-Supply Power Management IC for Powering FPGAs and DSPs

Check for Samples: TPS75003-EP

FEATURES

APPLICATIONS

• FPGA/DSP/ASIC Supplies

• Two 95% Efficient, 3-A Buck Controllers and

• Set-Top Boxes

One 300-mA LDO

• DSL Modems

• Tested and Endorsed by Xilinx for Powering

• Plasma TV Display Panels

the Spartan™-3, Spartan-3E, and Spartan-3L

FPGAs

DESCRIPTION

• Adjustable (1.2 V to 6.5 V for Bucks, 1 V to 6.5

The TPS75003 is a complete power management

V for LDO) Output Voltages on All Channels

solution for FPGA, DSP and other multi-supply

• Input Voltage Range: 2.2 V to 6.5 V

applications. The device has been tested with and

• Independent Soft-Start for Each Supply

meets all of the Xilinx Spartan-3, Spartan-3E, and

Spartan-3L start-up profile requirements, including

• Independent Enable for Each Supply for

monotonic voltage ramp and minimum voltage rail

Flexible Sequencing

rise time. Independent Enables for each output allow

• LDO Stable with 2.2-μF Ceramic Output

sequencing to minimize demand on the power supply

Capicitor

at start-up. Soft-start on each supply limits inrush

• Small, Low-Profile 4,5 mm x 3,5 mm x 0,9 mm

current during start-up. Two integrated buck

QFN Package controllers allow efficient, cost-effective voltage

conversion for both low and high current supplies

such as core and I/O. A 300-mA LDO is integrated to

SUPPORTS DEFENSE, AEROSPACE,

provide an auxiliary rail such as V

CCAUX

on the Xilinx

AND MEDICAL APPLICATIONS

Spartan-3 FPGA. All three supply voltages are

• Controlled Baseline

offered in user-programmable options for maximum

• One Assembly/Test Site

flexibility.

• One Fabrication Site

The TPS75003 is fully specified from –55°C to

• Available in Military (–55°C/125°C)

+125°C and is offered in a QFN package, yielding a

highly compact total solution size with high power

Temperature Range

(1)

dissipation capability.

• Extended Product Life Cycle

• Extended Product-Change Notification

• Product Traceability

(1) Additional temperature ranges available - contact factory

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2Spartan is a trademark of Xilinx, Inc.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (29 pages)

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TPS75003-EP SGLS311A – DECEMBER 2006 – REVISED MARCH 2011 www.ti.com Triple-Supply Power Management IC for Powering FPGAs and DSPs Check for Samples: TPS75003-EP FEATURES APPLICATIONS • • • • • 1 2 • • • • • • • Two 95% Efficient, 3-A Buck Controllers and One 300-mA LDO Tested and Endorsed by Xilinx for Powering the Spartan™-3, Spartan-3E, and Spartan-3L FPGAs Adjustable (1.2 V to 6.5 V for Bucks, 1 V to 6.5 V for LDO) Output Voltages on All Channels Input Voltage Range: 2.2 V to 6.
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TPS75003-EP SGLS311A – DECEMBER 2006 – REVISED MARCH 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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TPS75003-EP SGLS311A – DECEMBER 2006 – REVISED MARCH 2011 www.ti.com Figure 1. Wirebond Plot THERMAL INFORMATION THERMAL METRIC (1) TPS75003-EP RHL (20 PINS) θJA Junction-to-ambient thermal resistance 42.6 θJCtop Junction-to-case (top) thermal resistance 51.8 θJB Junction-to-board thermal resistance 39.5 ψJT Junction-to-top characterization parameter 0.6 ψJB Junction-to-board characterization parameter 14.2 θJCbot Junction-to-case (bottom) thermal resistance 2.
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TPS75003-EP SGLS311A – DECEMBER 2006 – REVISED MARCH 2011 www.ti.com ELECTRICAL CHARACTERISTICS VEN1 = VIN1, VEN2 = VIN2, VEN3 = VIN3, VIN1 = VIN2 = 2.2 V, VIN3 = 3 V, VOUT3 = 2.5V, COUT1 = COUT2 = 47 μF, COUT3 = 2.2 μF, TA = -55°C to 125°C, unless otherwise noted. Typical values are at TA = 25°C.
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TPS75003-EP SGLS311A – DECEMBER 2006 – REVISED MARCH 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VEN1 = VIN1, VEN2 = VIN2, VEN3 = VIN3, VIN1 = VIN2 = 2.2 V, VIN3 = 3 V, VOUT3 = 2.5V, COUT1 = COUT2 = 47 μF, COUT3 = 2.2 μF, TA = -55°C to 125°C, unless otherwise noted. Typical values are at TA = 25°C. PARAMETER CONDITIONS MIN TYP MAX UNIT LDO VOUT3 Output voltage range VFB3 Feedback pin voltage (4) Feedback pin voltage accuracy 1 6.5 - VDO 0.507 (5) 2.95 V ≤ VIN3 ≤ 6.
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TPS75003-EP SGLS311A – DECEMBER 2006 – REVISED MARCH 2011 www.ti.
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TPS75003-EP SGLS311A – DECEMBER 2006 – REVISED MARCH 2011 IS1 SW1 IN1 DGND EN1 SS1 AGND SS3 www.ti.com IS2 IN2 SW2 DGND SS2 FB2 EN2 OUT3 EN3 FB1 FB3 IN3 PIN FUNCTIONS PIN DESCRIPTION NAME RHL DGND 6, 15, PAD AGND 18 Ground connection for LDO IN1 13 Input supply to BUCK1 IN2 8 Input supply to BUCK2 IN3 20 Input supply to LDO EN1 17 Driving the enable pin (ENx) high turns on BUCK1 regulator. Driving this pin low puts it into shutdown mode, reducing operating current.
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TPS75003-EP SGLS311A – DECEMBER 2006 – REVISED MARCH 2011 www.ti.com Typical Application Circuit for Powering the Xilinx Spartan-3 FPGA 15 mH 100 mF 0.01 mF DGND SW1 IN1 DGND SW2 IN2 IS1 EN1 SS1 SS3 15.4 kW IS2 SS2 EN2 61.9 kW EN3 10 mF 0.1 mF 1 mF FB3 100 mF AGND 33 mW 33 mW 36.5 kW 0.1 mF 61.9 kW 5 mH 100 mF Figure 2. TYPICAL CHARACTERISTICS Measured using circuit in Figure 2 Buck Converter BUCK LOAD REGULATION BUCK LOAD REGULATION Figure 3. Figure 4.
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TPS75003-EP SGLS311A – DECEMBER 2006 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) Measured using circuit in Figure 2 BUCK LINE REGULATION BUCK LINE REGULATION Figure 5. Figure 6. BUCK SWITCHING FREQUENCY vs IOUT, TA BUCK SWITCHING FREQUENCY vs IOUT Figure 7. Figure 8. BUCK OUTPUT VOLTAGE RIPPLE EFFICIENCY vs IOUT Figure 9. Figure 10.
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TPS75003-EP SGLS311A – DECEMBER 2006 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) Measured using circuit in Figure 2 BUCK START-UP vs VIN and IOUT BUCK START-UP vs VIN and COUT Figure 11. Figure 12. BUCK START-UP vs VIN and CSS BUCK START-UP vs IOUT and CSS Figure 13. Figure 14. LDO LOAD REGULATION LDO LINE REGULATION Figure 15. Figure 16.
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TPS75003-EP SGLS311A – DECEMBER 2006 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) Measured using circuit in Figure 2 LDO DROPOUT vs IOUT LDO DROPOUT vs TA Figure 17. Figure 18. RDS,ON PMOS vs VIN RDS,ON NMOS vs VIN Figure 19. Figure 20. LDO VOUT vs TA Figure 21.
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TPS75003-EP SGLS311A – DECEMBER 2006 – REVISED MARCH 2011 www.ti.com APPLICATION INFORMATION The TPS75003 is an integrated power management IC designed specifically to power DSPs and FPGAs such as the Xilinx Spartan-3, Spartan-3E and Spartan-3L. Two non-synchronous buck controllers can be configured to supply up to 3 A for both CORE and I/O rails. A low dropout linear regulator powers auxiliary rails up to 300 mA.
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TPS75003-EP SGLS311A – DECEMBER 2006 – REVISED MARCH 2011 www.ti.com Table 4. Capacitors Tested with the TPS75003 MANUFACTURER CAPACITANCE ESR VOLTAGE RATING 6TPB47M (PosCap) PART NUMBER Sanyo 47 μF 0.1 Ω 6.3 V T491D476M010AS 10 V Kemet 47 μF 0.8 Ω B45197A Epco 47 μF 0.175 Ω 16 V B45294−R1107−M40 Epco 100 μF 0.045 Ω 6.3 V 594D476X0016C2 Vishay 47 μF 0.11 Ω 16 V 594D127X96R3C2 Vishay 120 μF 0.085 Ω 6.3 V AVX 100 μF 0.15 Ω 6.3 V Sanyo 100 μF 0.45 Ω 6.
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TPS75003-EP SGLS311A – DECEMBER 2006 – REVISED MARCH 2011 www.ti.com Current Limit (Buck Controllers) An external resistor (R1 or R2) is used to set the current limit for the external PMOS transistor (Q1 or Q2). These resistors are connected between IN1 and IS1 (or IN2 and IS2) to provide a reference voltage across these pins that is proportional to the current flowing through the PMOS transistor. This reference voltage is compared to an internal reference to determine if an over-current condition exists.
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TPS75003-EP SGLS311A – DECEMBER 2006 – REVISED MARCH 2011 www.ti.com Figure 23. Soft-Start Circuitry Figure 24. Soft-Start Timing Diagram Input Capacitor CIN1, CIN2 Selection (Buck Controllers) It is good analog design practice to place input capacitors near the inputs of the device in order to ensure a low impedance input supply. A capacitance of 10 μF to 22 μF for each buck converter is adequate for most applications, and should be placed within 100 mils (0.
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TPS75003-EP SGLS311A – DECEMBER 2006 – REVISED MARCH 2011 www.ti.com Inductor Value Selection (Buck Controllers) The inductor is chosen based on inductance value and maximum current rating. Larger inductors reduce current ripple (and therefore, output voltage ripple) but are physically larger and more expensive. Inductors with lower DC resistance typically improve efficiency, but also have higher cost and larger physical size. The buck converters work well with inductor values between 4.
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TPS75003-EP SGLS311A – DECEMBER 2006 – REVISED MARCH 2011 www.ti.com Diode Selection (Buck Controllers) The diode is off when the PMOS is on, and on when the PMOS is off. Since it will be turned on and off at a relatively high frequency, a Schottky diode is recommended for good performance. The peak current rating of the diode should exceed the peak current limit set by the sense resistor RIS1,2.
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TPS75003-EP SGLS311A – DECEMBER 2006 – REVISED MARCH 2011 www.ti.com CSS1 = 0.01 mF R1 = 33 mW CSS1 = 0.022 mF R1 = 143 mW CSS1 = 0.022 mF CSS1 = 0.01 mF Figure 25. Effects of CSS1 and R1 on Current Ramp Limit This soft-start current limit ramo can be used to provide inrush current control or output voltage ramp control. While the current limit ramp can be easily understood by looking at Figure 25, the output voltage ramp is a complex function of many variables.
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TPS75003-EP SGLS311A – DECEMBER 2006 – REVISED MARCH 2011 www.ti.com Output Capacitor Selection (LDO) A 2.2 μF or greater capacitor is required near the output of the device to ensure stability. The LDO is stable with any capacitor type, including ceramic. If improved transient response or ripple rejection is required, larger and/or lower ESR output capacitors can be used. Soft-Start (LDO) The LDO uses an external soft-start capacitor, CSS3, to provide an RC-ramped reference voltage to the control loop.
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TPS75003-EP SGLS311A – DECEMBER 2006 – REVISED MARCH 2011 www.ti.com Power Dissipation (LDO) The TPS75003 comes in a QFN-style package with an exposed lead frame on the package underside. The exposed lead frame is the primary path for removing heat and should be soldered to a PC board that is configured to remove the amount of power dissipated by the LDO, as calculated by Equation 15.
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TPS75003-EP SGLS311A – DECEMBER 2006 – REVISED MARCH 2011 www.ti.com Note: Most sensitive areas are highlighted in green. Figure 27.
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TPS75003-EP SGLS311A – DECEMBER 2006 – REVISED MARCH 2011 Note: www.ti.com Most sensitive areas are highlighted in green. Figure 28.
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TPS75003-EP SGLS311A – DECEMBER 2006 – REVISED MARCH 2011 www.ti.com REVISION HISTORY Changes from Original (December 2006) to Revision A • Page Replaced the DISSIPATION RATINGS table with the Thermal Information Table ..............................................................
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PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS75003MRHLREP Package Package Pins Type Drawing VQFN RHL 20 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 3000 330.0 12.4 Pack Materials-Page 1 3.8 B0 (mm) K0 (mm) P1 (mm) 4.8 1.6 8.0 W Pin1 (mm) Quadrant 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS75003MRHLREP VQFN RHL 20 3000 367.0 367.0 35.
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