Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - power management - special purpose 175 µA VQFN 20 (5x5)

27 kW

10 kW

XRS

VMON

10 Fm

SEQ

GND

VSET

5-V

Power

Supply

100 kW

SS2SS1

CT2CT1

TEST

DDIO-n

DD-n

DDIO-3

DD-3

DDIO-2

DD-2

DDIO-1

DD-1

0.1 Fm

0.1 Fm0.1 Fm 0.1 Fm

0.1 Fm

C2000

Controller

TPS75005

GND

OUT2-S

OUT2

OUT1-S

OUT1

VDET

TPS75005

www.ti.com

SBVS144C –NOVEMBER 2011–REVISED APRIL 2012

Integrated MCU Power Solution for C2000™ Microcontrollers

Check for Samples: TPS75005

FEATURES

DESCRIPTION

The TPS75005 is a complete power management

• Optimized to Supply TI's C2000 MCU Series:

solution for Texas Instruments' C2000 real-time

F2833x ( DELFINO™), F2823x, F281x, and

microcontrollers and other DSP, FPGA, and ASIC

F280x/F2801x

MCUs. The device has been tested with and meets

• Dual 500-mA Voltage Regulators with

TI's F2833x (DELFINO), F2823x, F281x, and

Dedicated Supply Voltage Supervisors (SVSs)

F280x/F2801x power requirements.

• One Auxiliary SVS

All of these C2000 controllers require ±5% power-rail

• LDO1 and SVS1 for 1.8 V/1.9 V (Selectable):

accuracy. With the combination of high-accuracy,

±5% Specified with PG low-dropout regulators (LDOs) and dedicated SVSs,

the device allows for a ±5% power supply to the

• LDO2 and SVS2 for 3.3 V:

C2000 with a power-good (PG) signal. (For more

±5% Specified with PG

details, see Application Report SBVA032, LDO+SVS

• Input Voltage Range: 3.75 V to 6.5 V

Combined Accuracy.)

• Independent Soft-Start for LDO1 and LDO2

Two power outputs are controlled by an integrated

• Preset Power-Up and Power-Down Sequencing

sequencer circuit. A single EN logic input signal

for C2000 MCUs

makes sure that the power-up and power-down

requirements of the C2000 controllers are met. The

• Supports C2000 MCU Transient with Two

sequencer includes a soft-start for both LDOs to

10-µF Ceramic Output Capacitors

avoid inrush current. A third rail monitor is provided

• 5-mm × 5-mm QFN Package

(1)

for general-purpose monitoring (for example, to

monitor input voltage).

APPLICATIONS

A quick-start guide (SBVA030) is available with step-

• C2000 MCUs

by-step instructions for connection to a C2000

• DSPs/FPGAs/ASICs controller.

The TPS75005 is available in a 5-mm × 5-mm QFN

package, yielding a compact total solution size with

(1) 16-Pin HTSSOP package can be supported but minimum

quantity may be required; contact sales representative. high power dissipation capability.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2C2000, DELFINO are trademarks of Texas Instruments.

3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (32 pages)

PAGE 1
TPS75005 www.ti.com SBVS144C – NOVEMBER 2011 – REVISED APRIL 2012 Integrated MCU Power Solution for C2000™ Microcontrollers Check for Samples: TPS75005 FEATURES DESCRIPTION • The TPS75005 is a complete power management solution for Texas Instruments' C2000 real-time microcontrollers and other DSP, FPGA, and ASIC MCUs. The device has been tested with and meets TI's F2833x (DELFINO), F2823x, F281x, and F280x/F2801x power requirements.
PAGE 2
TPS75005 SBVS144C – NOVEMBER 2011 – REVISED APRIL 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
PAGE 3
TPS75005 www.ti.com SBVS144C – NOVEMBER 2011 – REVISED APRIL 2012 THERMAL INFORMATION TPS75005 THERMAL METRIC (1) (2) RGW (QFN) (3) UNITS 20 PINS Junction-to-ambient thermal resistance (4) θJA (5) 35.1 θJCtop Junction-to-case (top) thermal resistance θJB Junction-to-board thermal resistance (6) 14.4 ψJT Junction-to-top characterization parameter (7) 0.4 ψJB Junction-to-board characterization parameter (8) 14.5 θJCbot Junction-to-case (bottom) thermal resistance (9) 3.
PAGE 4
TPS75005 SBVS144C – NOVEMBER 2011 – REVISED APRIL 2012 www.ti.com ELECTRICAL CHARACTERISTICS Over operating temperature range of TJ = –40 °C to +125 °C, with 4.0 V ≤ VIN ≤ 6.
PAGE 5
TPS75005 www.ti.com SBVS144C – NOVEMBER 2011 – REVISED APRIL 2012 ELECTRICAL CHARACTERISTICS (continued) Over operating temperature range of TJ = –40 °C to +125 °C, with 4.0 V ≤ VIN ≤ 6.
PAGE 6
TPS75005 SBVS144C – NOVEMBER 2011 – REVISED APRIL 2012 www.ti.com PIN CONFIGURATION NC IN IN EN VMON 20 19 18 17 16 RGW PACKAGE 5-mm x 5-mm QFN-20 (TOP VIEW) 13 CT1 SS2 4 12 SS1 VDET 5 11 TEST PG 3 10 CT2 9 OUT1_S VSET 14 8 2 SEQ OUT2_S 7 OUT1 GND 15 6 1 GND OUT2 PIN DESCRIPTIONS PIN RGW QFN-20 NAME CT1 13 CT2 3 SVS2 internal-power-good delay setting.
PAGE 7
TPS75005 www.ti.com SBVS144C – NOVEMBER 2011 – REVISED APRIL 2012 FUNCTIONAL BLOCK DIAGRAM IN EN1 CL1 A IOUT1 > ICL1? BG 97% UVLO UVLO OUT1 CL1 TSD 0.3 V VCORE 1.8 V/500 mA TSD VS1 PD1 EN1 OUT1_S 360 W 0.3 V SW1 97% PG1 Delay 110 pF VMON EN2 VSET CL2 A IOUT2 > ICL2? VS1 EN2 OUT2 VIO 3.3 V/500 mA 110 pF CL1 OUT2_S PD2 360 W 0.
PAGE 8
TPS75005 SBVS144C – NOVEMBER 2011 – REVISED APRIL 2012 www.ti.com TYPICAL CHARACTERISTICS At TJ = +25°C, VIN = 5 V, V(EN) = VIN, CIN = 22 μF, COUT1 = COUT2 = 10 μF, C(SS1) = C(SS2) = C(CT1) = C(CT2) = (open), VSET = 0 V, VSNS1 = VOUT1, VSNS2 = VOUT2, PG pin pulled up to VOUT2 with 100-kΩ pull-up resistor, and VDET pin pulled up to VIN with 100kΩ pull-up resistor, unless otherwise noted. LDO1 (OUTPUT AND SVS THRESHOLD) VOLTAGE vs TEMPERATURE LDO2 (OUTPUT AND SVS THRESHOLD) VOLTAGE vs TEMPERATURE 1.
PAGE 9
TPS75005 www.ti.com SBVS144C – NOVEMBER 2011 – REVISED APRIL 2012 TYPICAL CHARACTERISTICS (continued) At TJ = +25°C, VIN = 5 V, V(EN) = VIN, CIN = 22 μF, COUT1 = COUT2 = 10 μF, C(SS1) = C(SS2) = C(CT1) = C(CT2) = (open), VSET = 0 V, VSNS1 = VOUT1, VSNS2 = VOUT2, PG pin pulled up to VOUT2 with 100-kΩ pull-up resistor, and VDET pin pulled up to VIN with 100kΩ pull-up resistor, unless otherwise noted.
PAGE 10
TPS75005 SBVS144C – NOVEMBER 2011 – REVISED APRIL 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) At TJ = +25°C, VIN = 5 V, V(EN) = VIN, CIN = 22 μF, COUT1 = COUT2 = 10 μF, C(SS1) = C(SS2) = C(CT1) = C(CT2) = (open), VSET = 0 V, VSNS1 = VOUT1, VSNS2 = VOUT2, PG pin pulled up to VOUT2 with 100-kΩ pull-up resistor, and VDET pin pulled up to VIN with 100kΩ pull-up resistor, unless otherwise noted. EN PIN THRESHOLD vs TEMPERATURE SVS3 (VMON) THRESHOLD vs TEMPERATURE 1.
PAGE 11
TPS75005 www.ti.com SBVS144C – NOVEMBER 2011 – REVISED APRIL 2012 TYPICAL CHARACTERISTICS (continued) At TJ = +25°C, VIN = 5 V, V(EN) = VIN, CIN = 22 μF, COUT1 = COUT2 = 10 μF, C(SS1) = C(SS2) = C(CT1) = C(CT2) = (open), VSET = 0 V, VSNS1 = VOUT1, VSNS2 = VOUT2, PG pin pulled up to VOUT2 with 100-kΩ pull-up resistor, and VDET pin pulled up to VIN with 100kΩ pull-up resistor, unless otherwise noted. LINE TRANSIENT RESPONSE 6 LINE TRANSIENT RESPONSE 1.88 6 3.42 VIN 4 1.84 3 5 1.82 VOUT1 4 3.
PAGE 12
TPS75005 SBVS144C – NOVEMBER 2011 – REVISED APRIL 2012 www.ti.com APPLICATION INFORMATION Design Guidelines Figure 25 and Figure 26 show a basic schematic and PCB layout for applications using the internal default settings for power-good delay and rise time of the LDO1 and LDO2 outputs at turn on. This configuration is typical for applications involving the targeted C2000 microcontrollers. The unused adjustment pins, CT1, CT2, SS1, and SS2, are left open or floating.
PAGE 13
TPS75005 www.ti.com SBVS144C – NOVEMBER 2011 – REVISED APRIL 2012 The PCB layout of Figure 26 shows that the input and output capacitors C2, C3, and C8 are located near the respective pins and interconnected with a wide, low-inductance, ground plane that includes the device ground and the thermal pad ground of the device. NOTE The input capacitor ground is routed under the device package through NC, pin-20. Figure 26. TPS75005EVM-023 Recommended Layout The PCB typically consists of four layers, minimum.
PAGE 14
TPS75005 SBVS144C – NOVEMBER 2011 – REVISED APRIL 2012 www.ti.com LDO BLOCKS The TPS75005 integrates two high-bandwidth LDOs for powering the VDD and VDDIO pins of the C2000 controllers. Input Capacitor Although an input capacitor is not required for LDO stability, it is recommended to connect a 10-μF capacitor across the input supply near the device. In addition to input capacitor consideration, pay attention to the printed circuit board (PCB) design in order to reduce source impedance.
PAGE 15
TPS75005 www.ti.com SBVS144C – NOVEMBER 2011 – REVISED APRIL 2012 Soft-Start (SS1 and SS2) The TPS75005 has a soft-start (or slow-start) function for LDO1 and LDO2 that work independently of one another. The ramp-up time for LDO1 and LDO2 is by default 260 µs due to the internal 110-pF capacitors. By connecting an external capacitor(s) at the SS1 and/or SS2 pins, the ramp-up time for the LDOs increases proportionately by following this equation: C (F) + 110 ´ 10-12 (F) tRAMPUP (s) = SSx ´ 1.2 (V) 0.
PAGE 16
TPS75005 SBVS144C – NOVEMBER 2011 – REVISED APRIL 2012 www.ti.com Internal Enable Signals and Pull-Down Switches As shown in Figure 1, LDO1 is controlled by the internal signal EN1, and LDO2 is controlled by EN2. SW1 and SW2 are the inverse signals of EN1 and EN2, respectively. Whenever LDO1 and LDO2 are disabled, that means EN1 and EN2 are logic-L, respectively. The corresponding output node(s) is discharged by an internal MOSFET and 360-Ω resistor controlled by SW1 and SW2.
PAGE 17
TPS75005 www.ti.com SBVS144C – NOVEMBER 2011 – REVISED APRIL 2012 MONITOR BLOCKS Supply Voltage Supervisors (SVS1 and SVS2) The TPS75005 integrates two supply voltage supervisors (SVSs) to monitor the VDD and VDDIO pins of the C2000 controllers. Delay Setting (CT1 and CT2) The TPS75005 has a programmable delay function for both SVS1 and SVS2 that work independently of each other.
PAGE 18
TPS75005 SBVS144C – NOVEMBER 2011 – REVISED APRIL 2012 www.ti.com Auxiliary Voltage Monitor (SVS3) The TPS75005 has an independent supply voltage supervisor (SVS3) for an auxiliary purpose. The input voltage to the VMON pin is compared with the 1.206 V internal reference and VDET is the output. One of the most common uses of this feature is to monitor the input voltage. For example, many applications may need to monitor the input voltage at a level higher than the UVLO.
PAGE 19
TPS75005 www.ti.com SBVS144C – NOVEMBER 2011 – REVISED APRIL 2012 Undervoltage Lockout (UVLO) The TPS75005 uses an undervoltage lockout (UVLO) circuit to keep the output shut off until the internal circuitry is operating properly. The UVLO circuit has a hysteresis feature so that short undershoot transients are typically ignored. See Figure 11 for the actual measurement. See the section for how to set a custom threshold voltage for the input voltage.
PAGE 20
TPS75005 SBVS144C – NOVEMBER 2011 – REVISED APRIL 2012 www.ti.com SEQUENCER BLOCK The TPS75005 integrates a sequencer logic circuit to control the power-up and power-down sequences of the two output voltage rails (VDD and VDDIO) for C2000 controllers. Application Report SBVA031, TPS75005 Advanced Information: Sequencer and State Machine, explains a state machine of this sequencer logic in detail.
PAGE 21
TPS75005 www.ti.com SBVS144C – NOVEMBER 2011 – REVISED APRIL 2012 Normal Power-Up and Power-Down Sequence Figure 32 shows oscilloscope waveforms of the TPS75005 in a normal power-up and power-down sequence with SEQ = L. Refer to the time lines labeled Event A through Event H. 1. Before Event A, the TPS75005 is idle, waiting for an enable event. (Power-Up Sequence Begins) 2. At Event A, EN goes to logic-H and the device immediately discharges a soft-start capacitor (CSS1) by using a one-shot circuit.
PAGE 22
TPS75005 H nt Ev e Ev e nt F nt Ev e Ev e G www.ti.com nt Ev A en tB Ev en tC Ev en tD Ev en tE SBVS144C – NOVEMBER 2011 – REVISED APRIL 2012 EN SS1 2% VSVS1 OUT1 VDOWN1 tSS1 VCT1 CT1 tD(SVS1) SS2 2% VSVS2 OUT2 VDOWN2 tSS2 VCT2 CT2 tD(SVS2) PG Figure 32.
PAGE 23
TPS75005 www.ti.com SBVS144C – NOVEMBER 2011 – REVISED APRIL 2012 THERMAL INFORMATION Power Dissipation Knowing the device power dissipation and proper sizing of the thermal plane that is connected to the tab or pad is critical to avoiding thermal shutdown and ensuring reliable operation.
PAGE 24
TPS75005 SBVS144C – NOVEMBER 2011 – REVISED APRIL 2012 www.ti.com Estimating Junction Temperature Using the thermal metrics ΨJT and ΨJB, as shown in the Thermal Information table, the junction temperature can be estimated with corresponding formulas (given in Equation 6). For backwards compatibility, an older θJC,Top parameter is listed as well.
PAGE 25
TPS75005 www.ti.com SBVS144C – NOVEMBER 2011 – REVISED APRIL 2012 REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (March 2012) to Revision C Page • Changed Voltage Information table ...................................................................................................................................... 2 • Added new note 2 to Thermal Information table ..................................................
PAGE 26
PACKAGE OPTION ADDENDUM www.ti.
PAGE 27
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS75005RGWR VQFN RGW 20 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 TPS75005RGWT VQFN RGW 20 250 180.0 12.4 5.3 5.3 1.5 8.0 12.
PAGE 28
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS75005RGWR VQFN RGW 20 3000 367.0 367.0 35.0 TPS75005RGWT VQFN RGW 20 250 210.0 185.0 35.
PAGE 29
PAGE 30
PAGE 31
PAGE 32
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.