Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - LDO voltage regulator Positive, fixed HTSSOP 20

FEATURES DESCRIPTION

APPLICATIONS

Typical Application Circuit

PGor

RESET

OUT

GND

0.22 Fm

PGor RESET Output

OUT

47 Fm

OUT

(1)

SENSE

TPS752xxQ

TPS754xxQ

SLVS242C – MARCH 2000 – REVISED OCTOBER 2007

www.ti.com

TPS752xxQ with RESET Output, TPS754xxQ with Power Good Output

FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS

• 2-A Low-Dropout Voltage Regulator

The TPS752xxQ and TPS754xxQ devices are

low-dropout regulators with integrated power-on reset

• Available in 1.5 V, 1.8 V, 2.5 V, 3.3 V Fixed

and power-good (PG) functions respectively. These

Output and Adjustable Versions

devices are capable of supplying 2 A of output

• Open Drain Power-On Reset With 100ms Delay

current with a dropout of 210 mV (TPS75233Q,

(TPS752xxQ)

TPS75433Q). Quiescent current is 75 μ A at full load

• Open Drain Power-Good (PG) Status Output

and drops down to 1 μ A when the device is disabled.

(TPS754xxQ)

These devices are designed to have fast transient

response for larger load current changes.

• Dropout Voltage Typically 210 mV at 2 A

(TPS75233Q)

Because the PMOS device behaves as a low-value

resistor, the dropout voltage is very low (typically

• Ultralow 75- μ A Typical Quiescent Current

210 mV at an output current of 2 A for the

• Fast Transient Response

TPS75x33Q) and is directly proportional to the output

• 2% Tolerance Over Specified Conditions for

current. Additionally, because the PMOS pass

Fixed-Output Versions

element is a voltage-driven device, the quiescent

current is very low and independent of output loading

• 20-Pin TSSOP PowerPAD™ (PWP) Package

(typically 75 μ A over the full range of output current,

• Thermal Shutdown Protection

1 mA to 2 A). These two key specifications yield a

significant improvement in operating life for

battery-powered systems.

• Telecom

The device is enabled when EN is connected to a

• Servers

low-level input voltage. This LDO family also features

• DSP, FPGA Supplies

a sleep mode; applying a TTL high signal to EN

(enable) shuts down the regulator, reducing the

quiescent current to less than 1 μ A at T

= +25 ° C.

blank

(Fixed Voltage Options)

(1) See Application Information for capacitor selection details.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2 PowerPAD is a trademark of Texas Instruments.

3 All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (32 pages)

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TPS752xxQ TPS754xxQ www.ti.com SLVS242C – MARCH 2000 – REVISED OCTOBER 2007 TPS752xxQ with RESET Output, TPS754xxQ with Power Good Output FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS FEATURES DESCRIPTION 1 • 2-A Low-Dropout Voltage Regulator • Available in 1.5 V, 1.8 V, 2.5 V, 3.
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TPS752xxQ TPS754xxQ www.ti.com SLVS242C – MARCH 2000 – REVISED OCTOBER 2007 DESCRIPTION, CONTINUED The RESET (SVS, POR, or power on reset) output of the TPS752xxQ initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS752xxQ monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage.
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TPS752xxQ TPS754xxQ www.ti.com SLVS242C – MARCH 2000 – REVISED OCTOBER 2007 DISSIPATION RATINGS BOARD (1) (2) PACKAGE Low-K (1) PWP High-K (2) PWP AIRFLOW (CFM) TA < +25°C DERATING FACTOR ABOVE TA = +25°C TA = +70°C TA = +85°C 0 2.9 mW 23.5 mW/°C 1.9 W 1.5 W 300 4.3 mW 34.6 mW/°C 2.8 W 2.2 W 0 3W 23.8 mW/°C 1.9 W 1.5 W 300 7.2 W 57.9 mW/°C 4.6 W 3.
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TPS752xxQ TPS754xxQ www.ti.com SLVS242C – MARCH 2000 – REVISED OCTOBER 2007 ELECTRICAL CHARACTERISTICS Over recommended operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 1 V; IOUT = 1 mA, VEN = 0 V, COUT = 47 μF, unless otherwise noted. Typical values are at TJ = +25°C. TPS752xxQ, TPS754xxQ PARAMETER MIN TYP MAX 0.98VOUT VOUT 1.02VOUT 2.7 V < VIN < 5.5 V 1.470 1.5 1.530 1.8 V output 2.8 V < VIN < 5.5 V 1.764 1.8 1.836 2.5 V output 3.5 V < VIN < 5.5 V 2.450 2.5 2.
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TPS752xxQ TPS754xxQ www.ti.com SLVS242C – MARCH 2000 – REVISED OCTOBER 2007 FUNCTIONAL BLOCK DIAGRAMS Adjustable Voltage Versions IN EN PG or RESET _ + OUT + _ 100 ms Delay (for RESET Option) R1 Vref = 1.1834 V FB R2 GND External to the device Fixed-Voltage Versions IN EN PG or RESET _ + OUT + _ SENSE 100 ms Delay (for RESET Option) R1 Vref = 1.
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TPS752xxQ TPS754xxQ www.ti.com SLVS242C – MARCH 2000 – REVISED OCTOBER 2007 PIN CONFIGURATIONS TSSOP-20 PWP (TOP VIEW) GND/HEATSINK 1 20 GND/HEATSINK NC 2 19 NC IN 3 18 NC IN 4 17 GND EN 5 16 NC PG or RESET 6 15 NC FB/SENSE 7 14 NC OUTPUT 8 13 NC OUTPUT 9 12 NC 10 11 GND/HEATSINK GND/HEATSINK Table 1. PIN DESCRIPTIONS TPS754xxQ, TPS752xxQ 6 NAME TSSOP-20 (PWP) PIN NO.
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TPS752xxQ TPS754xxQ www.ti.com SLVS242C – MARCH 2000 – REVISED OCTOBER 2007 TPS752xxQ RESET Timing Diagram VIN Vres (1) Vres t VOUT VIT+ (2) (2) VIT+ Threshold Voltage (2) VIT- Less than 5% of the Output Voltage (2) VIT- t RESET Output 100 ms Delay 100 ms Delay Output Undefined Output Undefined t (1) Vres is the minimum input voltage for a valid RESET. The symbol Vres is not currently listed within EIA or JEDEC standards for semiconductor symbology.
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TPS752xxQ TPS754xxQ www.ti.com SLVS242C – MARCH 2000 – REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS Table of Graphs FIGURE NO.
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TPS752xxQ TPS754xxQ www.ti.com SLVS242C – MARCH 2000 – REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS Over operating temperature range (TJ= –40°C to +125°C) unless otherwise noted. Typical values are at TJ = +25°C. TPS75x33Q OUTPUT VOLTAGE vs OUTPUT CURRENT TPS75x15Q OUTPUT VOLTAGE vs OUTPUT CURRENT 3.305 1.503 VIN = 2.7 V TJ = +25°C VIN = 4.3 V TJ = +25°C 1.502 VOUT VOUT - Output Voltage - V VOUT - Output Voltage - V 3.303 VOUT 3.301 3.299 1.501 1.500 1.499 3.297 1.498 3.
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TPS752xxQ TPS754xxQ www.ti.com SLVS242C – MARCH 2000 – REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS (continued) Over operating temperature range (TJ= –40°C to +125°C) unless otherwise noted. Typical values are at TJ = +25°C. TPS75xxxQ GROUND CURRENT vs JUNCTION TEMPERATURE 85 100 VIN = 5 V IOUT = 2 A PSRR - Power-Supply Rejection Ratio - dB 90 TPS75x33Q POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY Ground Current - mA 80 75 70 65 60 55 50 -40 90 VIN = 4.
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TPS752xxQ TPS754xxQ www.ti.com SLVS242C – MARCH 2000 – REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS (continued) Over operating temperature range (TJ= –40°C to +125°C) unless otherwise noted. Typical values are at TJ = +25°C. TPS75x01Q DROPOUT VOLTAGE vs INPUT VOLTAGE TPS75x33Q DROPOUT VOLTAGE vs JUNCTION TEMPERATURE 350 300 IOUT = 2 A 300 250 IOUT = 2 A VDO - Dropout Voltage - mV VDO - Dropout Voltage - mV TJ = +125°C 250 TJ = +25°C 200 150 TJ = -40°C 100 200 IOUT = 1.5 A 150 100 IOUT = 0.
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TPS752xxQ TPS754xxQ www.ti.com SLVS242C – MARCH 2000 – REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS (continued) Over operating temperature range (TJ= –40°C to +125°C) unless otherwise noted. Typical values are at TJ = +25°C. TPS75x33Q LINE TRANSIENT RESPONSE ILOAD = 2 A CLOAD = 100 mF (Tantalum) VOUT = 1.
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TPS752xxQ TPS754xxQ www.ti.com SLVS242C – MARCH 2000 – REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS (continued) Over operating temperature range (TJ= –40°C to +125°C) unless otherwise noted. Typical values are at TJ = +25°C. Test Circuit for Typical Regions of Stability (Figure 20 and Figure 21) (Fixed Output Options) VIN To Load IN OUT + COUT EN RL GND ESR Figure 19. TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE(1) vs OUTPUT CURRENT 10 VOUT = 3.3 V COUT = 100 mF VIN = 4.
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TPS752xxQ TPS754xxQ www.ti.com SLVS242C – MARCH 2000 – REVISED OCTOBER 2007 APPLICATION INFORMATION The TPS752xxQ and TPS754xxQ devices include four fixed-output voltage regulators (1.5 V, 1.8 V, 2.5 V and 3.3 V), and an adjustable regulator, the TPS75x01Q (adjustable from 1.5 V to 5 V). Minimum Load Requirements The TPS752xxQ and TPS754xxQ families are stable even at zero load; no minimum load is required for operation.
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TPS752xxQ TPS754xxQ www.ti.com SLVS242C – MARCH 2000 – REVISED OCTOBER 2007 Output Capacitor As with most LDO regulators, the TPS752xxQ and TPS754xxQ require an output capacitor connected between OUT and GND to stabilize the internal control loop. The minimum recommended capacitance value is 47 μF and the ESR (equivalent series resistance) must be between 100 mΩ and 10 Ω.
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TPS752xxQ TPS754xxQ www.ti.com SLVS242C – MARCH 2000 – REVISED OCTOBER 2007 In steady state operation (dc state condition), the load current is supplied by the LDO (solid arrow) and the voltage across the capacitor is the same as the output voltage (V(COUT) = VOUT). This condition means that no current is flowing into the COUT branch.
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TPS752xxQ TPS754xxQ www.ti.com SLVS242C – MARCH 2000 – REVISED OCTOBER 2007 Programming the TPS75x01Q Adjustable LDO Regulator The output voltage of the TPS77x01Q adjustable regulator is programmed using an external resistor divider as shown in Figure 25. The output voltage is calculated using Equation 1: R VOUT = Vref ´ (1 + 1 ) R2 (1) Where: • Vref = 1.1834 V typ (the internal reference voltage) Resistors R1 and R2 should be chosen for approximately 40μA divider current.
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TPS752xxQ TPS754xxQ www.ti.com SLVS242C – MARCH 2000 – REVISED OCTOBER 2007 Power Dissipation and Junction Temperature Specified regulator operation is assured to a junction temperature of +125°C; the maximum junction temperature should be restricted to +125°C under normal operating conditions. This restriction limits the power dissipation the regulator can handle in any given application.
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TPS752xxQ TPS754xxQ www.ti.com SLVS242C – MARCH 2000 – REVISED OCTOBER 2007 The PWP package is designed to optimize the heat transfer to the PWB. Because of the very small size and limited mass of a TSSOP package, thermal enhancement is achieved by improving the thermal conduction paths that remove heat from the component. The thermal pad is formed using a lead-frame design (patent pending) and manufacturing technique to provide the user with direct connection to the heat-generating IC.
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TPS752xxQ TPS754xxQ www.ti.com SLVS242C – MARCH 2000 – REVISED OCTOBER 2007 3.5 3.5 TA = +25°C TA = +55°C 300 ft/min 3.0 PD - Power Dissipation Limit - W PD - Power Dissipation Limit - W 3.0 150 ft/min 2.5 2.0 Natural Convection 1.5 1.0 0.5 300 ft/min 2.5 2.0 150 ft/min 1.5 Natural Convection 1.0 0.5 0 0 0 0.3 2 6 4 Copper Heatsink Area - cm 8 0 0.3 2 4 2 Copper Heatsink Area - cm (a) 6 8 2 (b) 3.5 TA = +105°C PD - Power Dissipation Limit - W 3.0 2.5 2.0 1.
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TPS752xxQ TPS754xxQ www.ti.com SLVS242C – MARCH 2000 – REVISED OCTOBER 2007 Figure 29 is an example of a thermally-enhanced PWB layout for use with the new PWP package. This board configuration was used in the thermal experiments that generated the power ratings shown in Figure 27 and Figure 28. As discussed earlier, copper has been added on the PWB to conduct heat away from the device. RθJA for this assembly is illustrated in Figure 27 as a function of heatsink area.
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TPS752xxQ TPS754xxQ www.ti.com SLVS242C – MARCH 2000 – REVISED OCTOBER 2007 Mounting Information The primary requirement is to complete the thermal contact between the thermal pad and the PWB metal. The thermal pad is a solderable surface and is fully intended to be soldered at the time the component is mounted. Although voiding in the thermal-pad solder-connection is not desirable, up to 50% voiding is acceptable.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) TPS75201QPWPR HTSSOP PWP 20 2000 330.0 16.4 TPS75215QPWPR HTSSOP PWP 20 2000 330.0 TPS75218QPWPR HTSSOP PWP 20 2000 330.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS75201QPWPR HTSSOP PWP 20 2000 367.0 367.0 38.0 TPS75215QPWPR HTSSOP PWP 20 2000 367.0 367.0 38.0 TPS75218QPWPR HTSSOP PWP 20 2000 367.0 367.0 38.0 TPS75225QPWPR HTSSOP PWP 20 2000 367.0 367.0 38.0 TPS75233QPWPR HTSSOP PWP 20 2000 367.0 367.0 38.0 TPS75401QPWPR HTSSOP PWP 20 2000 367.0 367.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.