Datasheet

TPS780
GND
V
IN
V
OUT
MSP430
V
SS
V
CC
I/O
V =3.6V
CC
5mA
Active
Mode
700nAI
LPM3/SleepMode
Q
V =2.2V
CC
Current
1 Fm 1 Fm
2.2Vto3.6V
V
SET
LDO
GND
V
IN
V
OUT
1 Fm 1 Fm
MSP430
V
SS
V
CC
I/O
V =3.0V
CC
5mA
Active
Mode
3.0V
1.6 AI
LPM3/SleepMode
m
Q
TI Information — Selective Disclosure
TPS780 Series
SBVS083D –JANUARY 2007–REVISED SEPTEMBER 2012 www.ti.com
Powering the MSP430 Microcontroller
Several versions of the TPS780 are ideal for
powering the MSP430 microcontroller. Table 4 shows
potential applications of some voltage versions.
Table 4. Typical MSP430 Applications
V
OUT(HIGH)
V
OUT(LOW)
DEVICE (TYP) (TYP) APPLICATION
V
OUT, MIN
> 1.800V
required by many
MSP430s. Allows
TPS780360200 3.6V 2.0V
lowest power
consumption
operation.
V
OUT, MIN
> 2.200V
required by some
TPS780360220 3.6V 2.2V
MSP430s FLASH
operation.
V
OUT, MIN
> 2.700V
required by some
TPS780360300 3.6V 3.0V
MSP430s FLASH
operation.
Figure 56. Typical LDO without DVS
V
OUT, MIN
< 3.600V
required by some
TPS780360220 3.6V 2.2V MSP430s. Allows
highest speed
operation.
The TPS780 family offers many output voltage
versions to allow designers to optimize the supply
voltage for the processing speed required of the
MSP430. This flexible architecture minimizes the
supply current consumed by the particular MSP430
application. The MSP430 total system power can be
reduced by substituting the 500nA I
Q
TPS780 series
LDO in place of an existing ultra-low I
Q
LDO (typical
best case = 1μA). Additionally, DVS allows for
increasing the clock speed in active mode (MSP430
V
CC
= 3.6V). The 3.6V V
CC
reduces the MSP430 time
in active mode. In low-power mode, MSP430 system
power can be further reduced by lowering the
MSP430 V
CC
to 2.2V in sleep mode.
Key features of the TPS780 series are an ultralow
quiescent current (500nA), DVS, and miniaturized
packaging. The TPS780 family are available in SON-
Figure 57. TPS780 with Integrated DVS
6 and TSOT-23 packages. Figure 56 shows a typical
MSP430 circuit powered by an LDO without DVS.
Figure 57 is an MSP430 circuit using a TPS780 LDO
The other benefit of DVS is that it allows a higher V
CC
that incorporates an integrated DVS, thus simplifying
voltage on the MSP430, increasing the clock speed
the circuit design. In a circuit without DVS, as
and reducing the active mode dwell time.
Figure 56 illustrates, V
CC
is always at 3.0V. When the
MSP430 goes into sleep mode, V
CC
remains at 3.0V;
if DVS is applied, V
CC
could be reduced in sleep
mode. In Figure 57, the TPS780 LDO with integrated
DVS maintains 3.6V V
CC
until a logic high signal from
the MSP430 forces V
OUT
to level shift V
OUT
from 3.6V
down to 2.2V, thus reducing power in sleep mode.
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