!" # " Data Manual July 2002 Mixed Signal Products SGLS123
Contents Section Title Page 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.1 Link Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.2 Physical-Link Interface . . . . . . . . . . . . . . . . . . . . . . .
.3.1 3.3.2 3.3.3 3.3.4 3.3.5 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ATF Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ITF Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General-Receive FIFO (GRF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM Test Mode . . . . . . . . .
List of Illustrations Figure Title Page 1–1 TSB12LV01B Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4 2–1 TSB12LV01B Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1 3–1 Internal Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2 3–2 Interrupt Logic Diagram Example . . . . . . . . . . . . . . . . . . .
6–11 TSB12LV01B Link-Request-to-PHY-Layer Interface Waveforms . . . . . . . . . . . . . . . . . 6–12 Interrupt Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–13 CycleIn Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14 CYCLEIN and CYCLEOUT Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–1 PHY-LLC Interface . . . . . . .
List of Tables Table Title Page 1–1 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4 3–1 Version/Revision Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3 3–2 Node-Address/Transmitter Acknowledge Register Field Descriptions . . . . . . . . . . . . . 3–3 3–3 Control-Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1 Overview 1.1 Description The TSB12LV01B is an IEEE 1394-1995 standard (from now on referred to only as 1394) high-speed serial-bus link-layer controller that allows for easy integration into an I/O subsystem. The TSB12LV01B provides a high-performance IEEE 1394-1995 interface with the capability of transferring data between the 32-bit host bus, the 1394 PHY-link interface, and external devices connected to the local bus interface.
The following are features of the TSB12LV01B. 1.1.1 Link Core • • • • • • • 1.1.2 Supports Provision of IEEE 1394-1995 (1394) Standard for High-Performance Serial Bus Transmits and Receives Correctly Formatted 1394 Packets Supports Asynchronous and Isochronous Data Transfers Performs Function of 1394 Cycle Master Generates and Checks 32-Bit CRC Detects Lost Cycle-Start Messages Contains Asynchronous, Isochronous, and General-Receive FIFOs Totaling 2K Bytes Physical-Link Interface • • • 1.1.
1.
1.3 Host Bus Terminal Functions DATA0 – DATA31 ADDR0 – ADDR7 CS CA WR INT D0 – D7 CTL0 CTL1 LREQ SCLK PHY Interface TSB12LV01B CYCLEIN CYCLEOUT BCLK RESET MTEST3 11 20 VCC GND POWERON GRFEMP/GPO0 CYDNE/GPO1 CYST/GPO2 MTEST2 MTEST1 MTEST0 Figure 1–1. TSB12LV01B Terminal Functions Table 1–1. Terminal Functions TERMINAL I/O DESCRIPTION 22–25 27–30 I Host address bus ADDR0 is the most significant bit (MSB). Address lines 6 and 7 must be grounded.
Table 1–1. Terminal Functions (Continued) TERMINAL NAME NO. I/O DESCRIPTION PHY Interface CTL1, CTL0 62,63 I/O PHY-link interface control bus. CTL1 and CTL0 indicate the four operations that can occur on this interface (see Section 7 of this document or Annex J of the IEEE 1394-1995 standard for more information about the four operations). D0 – D7 60-57 55-52 I/O PHY-link interface data bus. Data is expected on D0 – D1 for 100 Mbits/s packets, D0 – D3 for 200 Mbits/s, and D0 – D7 for 400 Mbits/s.
Table 1–1. Terminal Functions (Continued) TERMINAL NAME NO. I/O DESCRIPTION Miscellaneous Signals (Continued) MTEST0 71 I Manufacturing Test 0. This input should be grounded under normal operating conditions. MTEST1 72 O Manufacturing Test 1. This output should remain open under normal operating conditions. MTEST2 73 I Manufacturing Test 2. This input should be grounded under normal operating conditions. MTEST3 77 I Manufacturing Test 3.
2 Architecture 2.1 Functional Block Diagram The functional block architecture of the TSB12LV01B is shown in Figure 2–1. FIFO LINK CORE Transmitter H o s t Host Processor I n t e r f a c e ATF Cycle Timer ITF CRC Cycle Monitor GRF Receiver P h y s i c a l Serial Bus I n t e r f a c e Internal Configuration Registers (CFR) Figure 2–1. TSB12LV01B Block Diagram 2.1.1 Physical Interface The physical (PHY) interface provides PHY-level services to the transmitter and receiver.
2.1.3 Receiver The receiver takes incoming data from the PHY interface and determines if the incoming data is addressed to this node. If the incoming packet is addressed to this node, the CRC of the packet is checked. If the header CRC is good, the header is confirmed in the GRF. For block and isochronous packets, the remainder of the packet is confirmed one quadlet at a time. The receiver places a status quadlet in the GRF after the last quadlet of the packet is confirmed in the GRF.
2.1.6 Cycle Monitor The cycle monitor is only used by nodes that support isochronous data transfer. The cycle monitor observes chip activity and handles scheduling of isochronous activity. When a cycle-start message is received or sent, the cycle monitor sets the cycle-started interrupt bit. It also detects missing cycle-start packets and sets the cycle-lost interrupt bit when this occurs. When the isochronous cycle is complete, the cycle monitor sets the cycle-done-interrupt bit.
3 Internal Registers 3.1 General The host-bus processor directs the operation of the TSB12LV01B through a set of registers internal to the TSB12LV01B itself. These registers are read or written by asserting CS with the proper address on ADDR0 – ADDR7 and asserting or deasserting WR depending on whether a read or write is needed. Figure 3–1 lists the register addresses; subsequent sections describe the function of the various registers. 3.
Reserved ClrGRF AckV FhBad FrGp IArbFl CyLst CArbFl CyLst CArbFl IArbFl IRP1En IRP2En CyDne CyPnd CyDne CyPnd ArbGp CySrc CyTEn TrgEn CySt CySt FrGp CyMas CyTm0 CySec CyTm0 CySec TCErr TCErr Interrupt Interrupt Mask 12 Bits MonTag TAG2 Control Reserved Cycle Offset IR Port2 Reserved Trigger Size ATFSize regRW Reserved ENSp 24h Reserved CLrATF 20h Reserved Reserved SntRj HdrEr SntRj HdrEr ATBadF ATBadF Reserved Reserved RstTx RstRx ITBadF AckCen Reserved Reserv
3.2.1 Version/Revision Register (@00h) The version/revision register allows software to be written that supports multiple versions of the high-speed serial-bus link-layer controllers. This register is at address 00h and is read only. The initial value is 3031_3043h. Table 3–1. Version/Revision Register Field Descriptions 3.2.
3.2.3 Control Register (@08h) The control register dictates the basic operation of the TSB12LV01B. This register is at address 08h and is read/write. The initial value is 0000_0000h. Table 3–3. Control-Register Field Descriptions BITS ACRONYM FUNCTION NAME DESCRIPTION 0 IdVal ID valid When IdVal is set, the TSB12LV01B accepts packets addressed to the IEEE 1212 address set (Node Number) in the node-address register. When IdVal is cleared, the TSB12LV01B accepts only broadcast packets.
Table 3–3. Control-Register Field Descriptions (Continued) BITS ACRONYM FUNCTION NAME DESCRIPTION 20 CyMas Cycle master When CyMas is set and the TSB12LV01B is attached to the root phy, the cyclemaster function is enabled. When the cycle_count field of the cycle timer register increments, the transmitter sends a cycle-start packet. This bit is not cleared upon bus reset.
Set PhInt Source DATA (01) WR CS Clear Q PhInt Bit Clk SCLK PhInt Bit Interrupt Bit (INT) PhIntMask Bit Other Interrupts Interrupt Bit INT IntMask Bit Figure 3–2. Interrupt Logic Diagram Example Table 3–4. Interrupt- and Mask-Register Field Descriptions BITS ACRONYM FUNCTION NAME DESCRIPTION 0 Int Interrupt Int contains the value of all interrupt and interrupt mask bits ORed together.
Table 3–4. Interrupt- and Mask-Register Field Descriptions (Continued) BITS ACRONYM FUNCTION NAME DESCRIPTION 11 ITBadF Bad packet formatted in ITF When ITBadF is set, the transmitter has detected invalid data at the isochronous transmit-FIFO interface. 12 ATBadF Bad packet formatted in ATF When ATBadF is set, the transmitter has detected invalid data at the asynchronous transmit-FIFO interface.
3.2.5 Cycle-Timer Register (@14h) The cycle-timer register contains the seconds_count, cycle_count and cycle_offset fields of the cycle timer. This register is controlled by the cycle master, cycle source, and cycle timer enable bits of the control register. This register is read/write and must be written to as a quadlet. The initial value of the Cycle-Timer register is 0000_0000h. Table 3–5. Cycle-Timer Register Field Descriptions 3.2.
Table 3–7. Node-Address/Transmitter Acknowledge Register Field Descriptions (Continued) BITS ACRONYM FUNCTION NAME DESCRIPTION 5 – 13 Trigger Size Trigger size in quadlets Trigger size is used to partition a received packet into several smaller blocks of data. For example: if trigger size = 8, total received packet size (excluding header CRC and data CRC) = 20 quadlets, the receiver creates 3 blocks of data in the GRF.
Table 3–9. PHY-Chip Access Register BITS ACRONYM FUNCTION NAME DESCRIPTION 0 RdPhy Read PHY-chip register When RdPhy is set, the TSB12LV01B sends a read register request with address equal to phyRgAd to the PHY interface. This bit is cleared when the request is sent. 1 WrPhy Write PHY-chip register When WrPhy is set, the TSB12LV01B sends a write register request with an address equal to phyRgAd on to the PHY interface. This bit is cleared when the request is sent.
Table 3–10. ATF Status Register (Continued) BITS ACRONYM FUNCTION NAME DESCRIPTION 4 Control Control bit The value of control bit is used to relate the MSB of access RAM location in RAM test mode. For RAM test mode WRITE– control bit value concatenated with DATA0 – DATA31, writes to the location pointed by the AdrCounter. For RAM test mode READ– the read location is pointed to by the current AdrCounter.
Table 3–12. GRF Status Register (Continued) BITS 2 ACRONYM PacCom FUNCTION NAME Packet complete DESCRIPTION When cd = 1 and PacCom = 1, the next block of data from the GRF is the last one for the packet. When cd = 1 and PacComp = 0, the next block of data from the GRF is just one block for the current received packet. If the trigger size function is disabled or flush bad packet bit is set, cd = 1 and PacCom is 1. This means each received packet only contains one block of GRF data.
3.2.14 Mux Control Register (@44h) The Mux control register resides in the BCLK domain. The power-up reset value of this register is 0000_0000’h. After reset the GRFEMP, CYDNE, and CYST pins will have the same functionality as the TSB12LV01A device. Tables 3–14, 3–15, and 3–16 describe the bit fields of this register. A logic high on each GPO pin indicates that the corresponding internal device event or bus event has taken place.
Table 3–15.
Table 3–16.
3.3 FIFO Access Access to all the transmit FIFOs is fundamentally the same; only the address to where the write is made changes. 3.3.1 General The TSB12LV01B controller FIFO-access address map shown in Figure 3–3 illustrates how the FIFOs are mapped. The suffix _First denotes the FIFO location where the first quadlet of a packet should be written when the writer wants to transmit the packet. The first quadlet will be held in the FIFO until a quadlet is written to an update location.
3.3.2 ATF Access The procedure to access the ATF is as follows: 1. Write the first quadlet of the packet to ATF location 80h: the data is not confirmed for transmission. 2. Write the second to n-1 quadlets of the packet to ATF location 84h: Can use burst write to write (n-2) quadlets into GRF, which requires only one host write transaction, the data is not confirmed for transmission. 3.
Example 3–1. Non-Burst Write 80h (ATF_First) DATA1[0:31] 84h (ATF_Continue) DATA2[0:31] . . . . 84h (ATF_Continue) DATA(n–1)[0:31] 8Ch (ATF_Continue & Update) DATAn[0:31] Example 3–2. Allowable Burst Write 80h (ATF_First) DATA1[0:31] 84h (ATF_Continue) (burst write) DATA2[0:31], DATA3[0:31], …… , DATA(n–1)[0:31] 8Ch (ATF_Continue & Update) DATAn[0:31] Example 3–3. Allowable Burst Write, But Riskier 80h (ATF_First) DATA1[0:31] 8Ch (ATF_Continue & Update) (burst write) DATA2[0:31], DATA3[0:31], ….
Writing to 90h(ITF_First) writes DATA0–DATA31 into the ITF and sets the control bit to 1 to indicate the first quadlet of the packet, but the data is not confirmed for transmission. It is allowable to burst write to 94h(ITF_Continue), which allows multiple quadlets to load into ITF, but the data is not confirmed for transmission. If bursting writes to ITF_Continue & Update do not keep up with data being put on the 1394 bus, an ITF underflow error will occur.
3.3.4 General-Receive FIFO (GRF) Access to the GRF is done with a read from the GRF, which requires a read from address C0h. Read from the GRF can be done in burst mode. Before reading the GRF, check whether the RxDta interrupt is set, which indicates data stored in GRF is ready to read. The GRF status register may also be read and the cd bit checked if it is 1 and the write count is greater than 0. The cd bit is equal to 1 means the packet token is on top of GRF.
{0, quadlet_5[0:31]} {0, quadlet_6[0:31]} {1, 0004_0670} <– second packet token, PacComp = 0 {0, quadlet_7[0:31]} {0, quadlet_8[0:31]} {0, quadlet_9[0:31]} {0, quadlet_10[0:31]} {0, quadlet_11[0:31]} {0, quadlet_12[0:31]} {1, 0014_0271} <– the last packet token, PacComp = 1, Ack = 4’0001 {0, quadlet_13[0:31]} {0, quadlet_14[0:31]} This following example generates one RxDta interrupt.
Another way to access specific location in the RAM during RAM test mode is to write desired value to AdrCounter of ATF status register. The next RAM test read or write accesses the location pointed by AdrCounter. AdrCounter contains current RAM address in RAM test mode During RAM test mode any location inside FIFO can be accessed by writing the address to AdrCounter of ATF status register. Each read or write accesses the location pointed by AdrCounter and Adrcounter increments by 1 after each transaction.
4 TSB12LV01B Data Formats The data formats for transmission and reception of data are shown in the following sections. The transmit format describes the expected organization of data presented to the TSB12LV01B at the host-bus interface. The receive formats describe the data format that the TSB12LV01B presents to the host-bus interface. 4.1 Asynchronous Transmit (Host Bus to TSB12LV01B) Asynchronous transmit refers to the use of the asynchronous-transmit FIFO (ATF) interface.
4.1.1.2 Quadlet Read-Response and Write Response Packets The format for a quadlet read-response packet is shown in Figure 4–3. The first quadlet contains the packet control information. The first 16 bits of the second quadlet is the destination identifier, which is the address of the destination or requesting node. The second quadlet also contains the response code of this transaction. The third quadlet is reserved. The fourth quadlet is the quadlet data used.
Table 4–1. Quadlet-Transmit Format FIELD NAME DESCRIPTION spd The spd field indicates the speed at which the current packet is to be sent (00 = 100 Mbits/s, 01 = 200 Mbits/s, and 10 = 400 Mbits/s, and 11 is undefined). tLabel The tLabel field is the transaction label, which is a unique tag for each outstanding transaction between two nodes. This field is used to pair up a response packet with its corresponding request packet.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Reserved spd tLabel destinationID rt tCode priority destinationOffsetHigh destinationOffsetLow dataLength extended_tCode block data Figure 4–5. Block-Transmit Format (Write Request) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Reserved spd tLabel destinationID rt tCode priority destinationOffsetHigh destinationOffsetLow dataLength extended_tCode Figure 4–6.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 spd Reserved destinationID tLabel rt rCode tCode priority Reserved RESERVED dataLength extended_tCode block data Figure 4–8. Block-Transmit Format (Write Response) Table 4–2. Block-Transmit Format Functions FIELD NAME DESCRIPTION spd The spd field indicates the speed at which the current packet is to be sent (00 = 100 Mbits/s, 01 = 200 Mbits/s, and 10 = 400 Mbits/s, and 11 is undefined).
4.2 Asynchronous Receive (TSB12LV01B to Host Bus) The general-receive FIFO (GRF) is shared by asynchronous data and isochronous data. There are two basic formats for data to be received. The first is for quadlet packets, and the second is for block packets. For block receives, the data length, which is found in the header of the packet, determines the number of bytes in the packet.
4.2.1.2 Quadlet Read-Response and Write-Response Packets The format for a quadlet read-response packet is shown in Figure 4–11. The first quadlet read from the GRF is the packet token described in section 3.3.4. It contains packet-reception status information added by the TSB12LV01B. The first 16 bits of the second quadlet contains the destination node and bus ID. The second quadlet also contains the response code of this transaction. The third quadlet is reserved.
Table 4–3. Quadlet-Receive Format Functions FIELD NAME DESCRIPTION PacCom Packet Complete. When PacCom = 1, the current block of data is the last one for the packet. When PacCom = 0, the current block of data is just another block of the current packet. spd The spd field indicates the speed at which the current packet is to be sent (00 = 100 Mbits/s, 01 = 200 Mbits/s, and 10 = 400 Mbits/s, and 11 is undefined). WriteCount WriteCount indicates the number of data quadlets in the packet.
4.2.2 Block Receive The IEEE 1394-1995 standard specified four types of block receive packets: write request, read request, write response, and read response packet. Refer to Table 4–4 for a description of the packet fields. 4.2.2.1 Block Write-Request and Read-Request Packets The format for a block write-request packet is shown in Figure 4–13. The first quadlet read from the GRF is the packet token described in section 3.3.4. It contains packet-reception status information added by the TSB12LV01B.
4.2.2.2 Block Read-Response and Write-Response Packets The format for a block read-response packet is shown in Figure 4–15. The first quadlet read from the GRF is the packet token described in section 3.3.4. It contains packet-reception status information added by the TSB12LV01B. The first 16 bits of the second quadlet contains the destination node and bus ID. The second quadlet also contains the response code of this transaction. The third quadlet is reserved.
Table 4–4. Block-Receive Format Functions FIELD NAME DESCRIPTION PacCom Packet Complete. When PacCom = 1, the current block of data is the last one for the packet. When PacCom = 0, the current block of data is just another block of the current packet. spd The spd field indicates the speed at which the current packet is to be sent (00 = 100 Mbits/s, 01 = 200 Mbits/s, and 10 = 400 Mbits/s, and 11 is undefined). WriteCount WriteCount indicates the number of data quadlets in the packet.
4.3 Isochronous Transmit (Host Bus to TSB12LV01B) The format of the isochronous-transmit packet is shown in Figure 4–17 and is described in Table 4–5. The data for each channel must be presented to the isochronous-transmit FIFO interface in this format in the order that packets are to be sent. The transmitter requests the bus to send any packets available at the isochronous-transmit interface immediately following reception or transmission of the cycle-start message.
Table 4–6. Isochronous-Receive Functions FIELD NAME DESCRIPTION PacCom Packet complete. When PacCom = 1, the current block of data is the last one for the packet. When PacCom = 0, the current block of data is just another block of the current packet. spd The spd field indicates the speed at which the current packet is to be sent (00 = 100 Mbits/s, 01 = 200 Mbits/s, and 10 = 400 Mbits/s, and 11 is undefined). WriteCount WriteCount indicates the number of data quadlets in the packet.
4.6 CycleMark The format of the CycleMark data is shown in Figure 4–20 and is described in Table 4–8. The receiver module inserts a single quadlet to mark the end of an isochronous cycle. The quadlet is inserted into the GRF. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Reserved Reserved CyDne 0 Reserved Figure 4–20. CycleMark Format Table 4–8. CycleMark Function FIELD NAME DESCRIPTION CyDne 4.7 The CyDne field indicates the end of an isochronous cycle.
Table 4–9. PHY-Configuration Functions FIELD NAME DESCRIPTION root_ID The root_ID field is the physical_ID of the node to have its force_root bit set (only meaningful when R is set). R When R is set, the force-root bit of the node identified in root_ID is set and the force_root bit of all other nodes are cleared. When R is cleared, root_ID is ignored. T When T is set, the gap count field of all the nodes is set to the value in the gap_cnt field.
4.9 Receive Self-ID The format of the receive self-ID packet is shown in Figure 4–23 and described in Table 4–11. The first quadlet is the packet token with the special code of Eh. The quadlets that follow are a concatenation of all received self-ID packets. See paragraph 4.3.4.1 of the IEEE 1394-1995 standard for additional information about self-ID packets.
0 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 phy_ID Packet Identifier 1 n(1) rsv p11 p12 p13 p14 p15 reserved Logical inverse of first quadlet Figure 4–26. PHY Self-ID Packet #2 Format Table 4–12. PHY Self-ID Packet Fields FIELD NAME DESCRIPTION phy_ID The phy_ID field contains the physical identification of the node transmitting the self-ID packet. L If set, this node has an active link and transaction layers.
4.10 Received PHY Configuration and Link-On Packet The format of the received PHY-configuration and link-on packet is similar to the received self-ID packet. In this case, the value of the errCode is 0000. Only the first quadlet of each packet is stored in the GRF. If the received second quadlet of each packet is not the inverse of the first one, the packet is ignored. See paragraph 4.3.4.2 of the IEEE 1394-1995 standard for additional information on link-on packets, and paragraph 4.3.4.
5 Electrical Characteristics 5.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range (Unless Otherwise Noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V Supply voltage range, VCC5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V Input voltage range, VI (standard TTL/LVCMOS) . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.
5.2 Recommended Operating Conditions Supply voltage, VCC Supply voltage voltage, VCC5V MIN NOM MAX 3 3.3 3.6 UNIT V 5-V tolerant 3 5 5.5 V Non 5-V tolerant 3 3.3 3.6 V High-level input voltage, VIH 2 Low-level input voltage, VIL 0.8 Transition time, (tt) (10% to 90%) 0 Operating free-air temperature, TA Virtual junction temperature, TJ‡ V 6 ns –40 25 85 °C 0 25 115 °C † This applies to external output buffers.
5.4 Host-Interface Timing Requirements, TA = 25°C (see Note 3) PARAMETER MIN MAX 111 UNIT tc1 tw1(H) Cycle time, BCLK (see Figure 6–1) 20 Pulse duration, BCLK high (see Figure 6–1) 8.6 ns ns tw1(L) tsu1 Pulse duration, BCLK low (see Figure 6–1) 8.
5.
6 Parameter Measurement Information BCLK 50% (Input) tw1(H) 50% 50% tw1(L) tc1 Figure 6–1. BCLK Waveform BCLK (Input) tsu1 th1 tsu2 th2 DATA0 – DATA31 (Input) ADDR0 – ADDR7 (Input) ÎÎÎÎ ÎÎÎÎ tsu3 ÎÎÎÎÎÎ ÎÎÎÎÎÎ th3 CS (Input) ÎÎÎÎ ÎÎÎÎ th4 tsu4 WR (Input) td1 ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ td2 CA (Output) NOTE A. Following a CS assertion, there may be a maximum of 9 rising edges of BCLK before a CA is returned. CA must be returned before another CS may be asserted. Figure 6–2.
BCLK (Input) DATA0 – DATA31 (Output) td4 td3 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ tsu2 ADDR0 – ADDR7 (Input) CS (Input) th2 tsu3 th3 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ th4 tsu4 WR (Input) CA (Output) td1 td2 NOTE A. Following a CS assertion, there may be a maximum of 9 rising edges of BCLK before a CA is returned. CA must be returned before another CS may be asserted. Figure 6–3.
BCLK (Input) td3 DATA0 – DATA31 (Output) ADDR0 – ADDR7 (Input) CS (Input) WR (Input) td4 DATA1 ÎÎ ÎÎ ADDR1 DATA2 ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ td1 ADDR2 ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ td2 CA (Output) NOTE A. There must be a minimum of 3 rising edges of BCLK between assertions of CS. Figure 6–5.
BCLK (Input) (see Note A) ÎÎÎ ÎÎÎ ÎÎÎ 0 1 2 ADDR0 – ADDR7 (Input) 8 9 10 td4 td3 DATA0 – DATA31 (Output) DATA1 DATA2 DATA7 DATA8 DATA9 CS (Input) ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ WR (Input) td1 td2 CA (Output) (see Note B) NOTES: A. At the (nth+1) BCLK rising edge, host bus should latch DATAn. B. CA is one cycle delay from respective CS. C. These waveforms only apply to address C0h. Figure 6–7. Burst Read Waveforms SCLK 50% (Input) tw2(H) 50% 50% tw2(L) tc2 Figure 6–8.
SCLK (Input) 50% tsu5 th5 D0 – D7 (Input) tsu6 th6 CTL0 – CTL1 (Input) Figure 6–10. PHY Layer Interface-to-TSB12LV01B Transfer Waveforms SCLK (Input) 50% td11 LREQ (Output) Figure 6–11. TSB12LV01B Link-Request-to-PHY-Layer Interface Waveforms SCLK (Input) 50% 50% td12 INT (Output) td13 50% 50% Figure 6–12.
CYCLEIN (Input) 50% 50% 50% tw3(H) tw3(L) tc3 Figure 6–13. CYCLEIN Waveform 50% SCLK (Input) 50% CYCLEIN (Input) td14 CYCLEOUT (Output) td15 50% Figure 6–14.
7 TSB12LV01B to 1394 PHY Interface Specification This chapter provides an overview of the digital interface between a TSB12LV01B and a physical layer device (PHY). The information that follows can be used as a guide through the process of connecting the TSB12LV01B to a 1394 PHY. The part numbers referenced, the TSB41LV03A and the TSB12LV01B, represent the Texas Instruments implementation of the PHY (TSB41LV03A) and link (TSB12LV01B) layers of the IEEE 1394-1995 and P1394a standards.
The ISO terminal is used to enable the output differentiation logic on the CTL0-CTL1 and D0-D7 terminals. Output differentiation is required when an Annex J type isolation barrier is implemented between the PHY and TSB12LV01B. The TSB41LV03A normally controls the CTL0–CTL1 and D0-D7 bidirectional buses. The TSB12LV01B is allowed to drive these buses only after the TSB12LV01B has been granted permission to do so by the PHY.
Regardless of the type of request, a start-bit of 1 is required at the beginning of the stream, and a stop-bit of 0 is required at the end of the stream. The second through fourth bits of the request stream indicate the type of the request. In the descriptions below, bit 0 is the most significant and is transmitted first in the request bit stream. The LREQ terminal is normally low. Encoding for the request type is shown in Table 7–4. Table 7–4.
For a read register request the length of the LREQ bit stream is 9 bits as shown in Table 7–7. Table 7–7. Read Register Request BIT(S) 0 NAME DESCRIPTION Start bit Indicates the beginning of the transfer (always 1) 1–3 Request type A 100 indicates this is a read register request.
For write register requests, the PHY loads the specified data into the addressed register as soon as the request transfer is complete. For read register requests, the PHY returns the contents of the addressed register to the TSB12LV01B at the next opportunity through a status transfer. If a received packet interrupts the status transfer, then the PHY continues to attempt the transfer of the requested register until it is successful.
Table 7–10. Status Bits BIT(s) NAME DESCRIPTION 0 Arbitration reset gap Indicates that the PHY has detected that the bus has been idle for an arbitration reset gap time (as defined in IEEE Std 1394-1995). This bit is used by the TSB12LV01B in the busy/retry state machine. 1 Subaction gap Indicates that the PHY has detected that the bus has been idle for a subaction gap time (as defined in IEEE Std 1394-1995). This bit is used by the TSB12LV01B to detect the completion of an isochronous cycle.
It is possible for the PHY to receive a null packet, which consists of the data-prefix state on the serial bus followed by the data-end state, without any packet data. A null packet is transmitted whenever the packet speed exceeds the capability of the receiving PHY, or whenever the TSB12LV01B immediately releases the bus without transmitting any data.
The sequence of events for a null packet reception is as follows: • Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL lines. Normally, the interface is idle when receive is asserted. However, the receive operation may interrupt a status transfer operation that is in progress so that the CTL lines may change from status to receive without an intervening idle. • Data-on indication.
After sending the last packet for the current bus ownership, the TSB12LV01B releases the bus by asserting idle on the CTL terminals for two clock cycles. The PHY begins asserting idle on the CTL terminals one clock cycle after sampling idle from the link. Note, that whenever the D and CTL terminals change direction between the PHY and the TSB12LV01B, there is an extra clock period allowed so that both sides of the interface can operate on registered versions of the interface signals.
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MECHANICAL DATA MTQF012B – OCTOBER 1994 – REVISED DECEMBER 1996 PZT (S-PQFP-G100) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 75 0,08 M 51 76 50 100 26 0,13 NOM 25 1 12,00 TYP Gage Plane 14,20 SQ 13,80 16,20 SQ 15,80 0,25 0,05 MIN 1,05 0,95 0°– 7° 0,75 0,45 Seating Plane 1,20 MAX 0,08 4073179 / B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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