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DESCRIPTION

TSB12LV01B

SLLA212 – JUNE 2006

IEEE 1394-1995 High-Speed Serial-Bus Link-Layer Controller

• Physical-Link Interface

• Link Core – Compatible With Texas Instruments

Physical Layer Devices (PHYs)

– Supports Provision of IEEE 1394-1995

(1394) Standard for High-Performance – Supports Transfer Speeds of 100, 200, and

Serial Bus 400 Mbits/s

– Transmits and Receives Correctly – Timing Compliant with IEEE 1394a–2000

Formatted 1394 Packets

• Host Bus Interface

– Supports Asynchronous and Isochronous

– Provides Chip Control With Directly

Data Transfers

Addressable Registers

– Performs Function of 1394 Cycle Master

– Is Interrupt Driven to Minimize Host Polling

– Generates and Checks 32-Bit CRC

– Has a Generic 32-Bit Host Bus Interface

– Detects Lost Cycle-Start Messages

• General

– Contains Asynchronous, Isochronous, and

– Operates From a 3.3-V Power Supply While

General-Receive FIFOs Totaling 2K Bytes

Maintaining 5-V Tolerant Inputs

– Manufactured With Low-Power CMOS

Technology

– 100-Pin PZT Package for 0 ° C to 70 ° C and

-40 ° C to 85 ° C (I Temperature) Operation

The TSB12LV01B is an IEEE 1394-1995 standard (from now on referred to only as 1394) high-speed serial-bus

link-layer controller that allows for easy integration into an I/O subsystem. The TSB12LV01B provides a

high-performance IEEE 1394-1995 interface with the capability of transferring data between the 32-bit host bus,

the 1394 PHY-link interface, and external devices connected to the local bus interface. The 1394 PHY-link

interface provides the connection to the 1394 physical (PHY) layer device and is supported by the link-layer

controller (LLC). The LLC provides the control for transmitting and receiving 1394 packet data between the FIFO

and PHY-link interface at rates of 100 Mbits/s, 200 Mbits/s, and 400 Mbits/s. The TSB12LV01B transmits and

receives correctly-formatted 1394 packets and generates and inspects the 32-bit cyclic redundancy check

(CRC). The TSB12LV01B is capable of being cycle master and supports reception of isochronous data on two

channels. TSB12LV01B has a generic 32-bit host bus interface, which will connect to most 32-bit hosts. The

LLC also provides the capability to receive status from the physical layer device and to access the physical layer

control and status registers by the application software. An internal 2K-byte memory is provided that can be

configured as multiple variable-size FIFOs and eliminates the need for external FIFOs. Separate FIFOs can be

user configured to support general 1394 receive, asynchronous transmit, and isochronous transmit transfer

operations. These functions are accomplished by appropriately sizing the general receive FIFO (GRF),

asynchronous transmit FIFO (ATF), and isochronous transmit FIFO (ITF).

The TSB12LV01B is a revision of the TSB12LV01A, with feature enhancements and corrections. It is pin for pin

compatible with the TSB12LV01A with the restrictions noted below. It is also software compatible with the

extensions noted below.

All errata items to the TSB12LV01A have been fixed, and the following feature enhancements have been made:

• Two new internal registers have been added at CFR address 40h and 44h. The Host Bus Control Register

at 40h and the Mux Control Register @44h .

• Three programmable general-purpose output pins have been added.

• Several pin changes have been made. Refer to TSB12LV01A to TSB12LV01B Transition Document, TI

literature number SLLA081 dated May 2000.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (5 pages)

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TSB12LV01B www.ti.
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TSB12LV01B www.ti.com SLLA212 – JUNE 2006 However, there are three restrictions that were not present in the TSB12LV01A device: • The TSB12LV01B may only operate with a 50 MHz host-interface clock (BCLK) if the duty cycle is less than 5% away from the 50-50 point, (i.e., the duty cycle must be within 45-55% inclusive). A 40-60% duty cycle clock is acceptable for host clock frequencies at or below 47 MHz. • The TSB12LV01B does not have bus holder cells on the PHY-link interface.
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PACKAGE OPTION ADDENDUM www.ti.
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MECHANICAL DATA MTQF012B – OCTOBER 1994 – REVISED DECEMBER 1996 PZT (S-PQFP-G100) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 75 0,08 M 51 76 50 100 26 0,13 NOM 25 1 12,00 TYP Gage Plane 14,20 SQ 13,80 16,20 SQ 15,80 0,25 0,05 MIN 1,05 0,95 0°– 7° 0,75 0,45 Seating Plane 1,20 MAX 0,08 4073179 / B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.