Host Controller Data Manual

3–16

Table 3–18. Link Enhancement Control Register Description (Continued)

BIT FIELD NAME TYPE DESCRIPTION

1 enab_accel R/W

Enable acceleration enhancements. OHCI-Lynx compatible. When set to 1, this bit notifies the PHY

that the link supports the 1394a acceleration enhancements, i.e., ack-accelerated, fly-by

concatenation, etc. It is recommended that this bit be set to 1.

0 RSVD R Reserved. Bit 0 returns 0 when read.

3.22 Subsystem Access Register

Write access to the subsystem access register updates the subsystem identification registers identically to

OHCI-Lynx. The system ID value written to this register may also be read back from this register. See Table 3–19 for

a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Subsystem access

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Subsystem access

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Type: Read/Write

Offset: F8h

Default: 0000 0000h

Table 3–19. Subsystem Access Register Description

BIT FIELD NAME TYPE DESCRIPTION

31–16 SUBDEV_ID R/W Subsystem device ID. This field indicates the subsystem device ID.

15–0 SUBVEN_ID R/W Subsystem vendor ID. This field indicates the subsystem vendor ID.