Host Controller Data Manual

4–21

4.24 Isochronous Transmit Interrupt Mask Register

The isochronous transmit interrupt mask set/clear register is used to enable the isochTx interrupt source on a

per-channel basis. Reads from either the set register or the clear register always return the contents of the

isochronous transmit interrupt mask register. In all cases the enables for each interrupt event align with the event

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Isochronous transmit interrupt mask

Type R R R R R R R R R R R R R R R R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Isochronous transmit interrupt mask

Type R R R R R R R R RSC RSC RSC RSC RSC RSC RSC RSC

Default 0 0 0 0 0 0 0 0 X X X X X X X X

Type: Read/Set/Clear, Read-only

Offset: 98h set register

9Ch clear register

Default: 0000 00XXh