Host Controller Data Manual

7–3
7.3 Electrical Characteristics Over Recommended Operating Conditions (unless
otherwise noted)
OPERATION
TEST
CONDITIONS
MIN MAX UNIT
PCI
I
OH
= – 0.5 mA 0.9 V
CC
PCI
I
OH
= – 2 mA 2.4
V
OH
High-level output voltage
PHY interface
I
OH
= – 4 µA 2.8
V
PHY
interface
I
OH
= – 8 mA V
CC
– 0.6
Miscellaneous
‡
I
OH
= – 4 mA V
CC
– 0.6
†
PCI
I
OL
= 1.5 mA 0.1 V
CC
†
PCI
I
OL
= 6 mA 0 0.55
V
OL
†
Low-level output voltage
PHY interface
I
OL
= 4 mA 0.4
V
PHY
interface
I
OL
= 8 mA
Miscellaneous
‡
I
OL
= 4 mA 0.5
I
OZ
3-state output high-impedance Output pins 3.6 V V
O
= V
CC
or GND ±20 µA
I
IL
Low level in
p
ut current
Input pins 3.6 V V
I
= GND
‡
±20
µA
I
IL
Lo
w-
le
v
el
inp
u
t
c
u
rrent
I/O pins
†
3.6 V V
I
= GND
‡
±20
µ
A
I
IH
High level in
p
ut current
PCI
†
3.6 V V
I
= V
CC
‡
±20
µA
I
IH
High
-
le
v
el
inp
u
t
c
u
rrent
Others
†
3.6 V V
I
= V
CC
‡
±20
µ
A
†
For I/O pins, input leakage (I
IL
and I
IH
) includes I
OZ
of the disabled output.
‡
Miscellaneous pins are: GPIO2, GPIO3, SDA, SCL, CYCLEOUT.
7.4 Switching Characteristics for PCI Interface
§
PARAMETER MEASURED MIN TYP MAX UNIT
t
su
Setup time before PCLK –50% to 50% 3 ns
t
h
Hold time before PCLK –50% to 50% 0 ns
t
d
Delay time, PHY_CLK to data valid –50% to 50% 2 6 ns
§
These parameters are ensured by design.
7.5 Switching Characteristics for PHY-Link Interface
§
PARAMETER MEASURED MIN TYP MAX UNIT
t
su
Setup time, Dn, CTLn, LREQ to PHY_CLK –50% to 50% 6 ns
t
h
Hold time, Dn, CTLn, LREQ before PHY_CLK –50% to 50% 1 ns
t
d
Delay time, PHY_CLK to Dn, CTLn –50% to 50% 2 11 ns
§
These parameters are ensured by design.