! Data Manual April 2004 Mixed-Signal Products SGLS139B
Contents Contents Section 1 2 3 4 Page Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 TSB12LV32 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 TSB12LV32-EP Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents 5 Data-Mover Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Data-Mover Data Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.1 Isochronous Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.2 Isochronous Transmit . . . . . . . . . . . .
List of Illustrations List of Illustrations Figure Title Page 1−1 TSB12LV32 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3−1 Microcontroller Byte Stack (Write) Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3−2 Microcontroller Byte Unstack (Read) Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Illustrations 5−21 Asynchronous Block Transmit With Automatic Header Insertion at 200 Mbps . . . . . . . . . . . . . . . . . . . . . . . . 59 5−22 Asynchronous Block Transmit With Automatic Header Insertion at 400 Mbps . . . . . . . . . . . . . . . . . . . . . . . . 59 5−23 Asynchronous Quadlet Transmit Without Automatic Header Insertion at 400 Mbps . . . . . . . . . . . . . . . . . . . 60 5−24 Asynchronous Block Transmit Without Automatic Header Insertion at 400 Mbps . . . . . . . . . . . . . . .
List of Tables List of Tables Table Title Page 1−1 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1−2 STAT Terminal Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2−1 Configuration Register (CFR) Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Tables viii SGLS139B October 2003 − Revised April 2004
Overview 1 Overview 1.1 TSB12LV32 Description The TSB12LV32 (GP2Lynx) is a high-performance general-purpose IEEE 1394a-2000 link-layer controller (LLC) with the capability of transferring data between the 1394 Phy-link interface, an external host controller, and an external device connected to the data-mover port (local bus interface). The 1394 Phy-link interface provides the connection to a 1394 physical layer device and is supported by the LLC.
Overview • • • • • • • • • 1.3 2K byte General Receive FIFO (GRF) Accessed Through Microcontroller Interface Supports Asynchronous and Isochronous Receive. 2K byte Asynchronous Transmit FIFO (ATF) Accessed Through Microcontroller Interface Supports Asynchronous Transmissions.
Overview 1.
Overview 1.5 Terminal Functions The terminal functions are described in Table 1−1. No input terminals or I/O terminals should be left floating; unless otherwise specified, connect any unused input terminals or I/O terminals to ground using 1-kΩ resistors. Table 1−1. Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION Microcontroller/Microprocessor Interface BCLK 6 I Microcontroller interface clock. Maximum frequency is 60 MHz.
Overview Table 1−1. Terminal Functions (Continued) TERMINAL NAME NO. I/O DESCRIPTION Data-Mover Port Interface (Continued) DMRW 49 O Data-mover read/write indicator. When data is being moved from 1394 to the DM port (receive) this signal goes high to indicate data is available on DMD[0:15]. When data is being moved from DM to 1394 bus (transmit) this signal goes high to indicate that data must be supplied to the DMD[0:15] port for transmission. PKTFLAG 51 O Packet flag.
Overview 1.5.1 STAT0, STAT1, and STAT2 Programming The STAT0, STAT1, and STAT2 terminals can be independently programmed to show one of 14 possible internal hardware status signals. The controls for the STAT terminals are in the Diagnostic register at address 20h of the CFR register. STAT0 is controlled by STATSEL0 (bits 16-19), STAT1 is controlled by bits STATSEL1 (bits 20−23), and STAT2 is controlled by STATSEL2 (bits 24−27). See Table 1−2 for programming the STAT terminals. Table 1−2.
Internal Registers 2 Internal Registers 2.1 TSB12LV32 Configuration Registers Table 2−1.
Internal Registers Table 2−2. Header/Trailer Usage for CFRs 38h−48h DIRECTION OF DM DATA TRANSFER PACKET TYPE AUTO HEADER/ TRAILER INSERT/ EXTRACT HEADER/TRAILER REGISTER YES Header0 CFR is formatted for isochronous transmission. Header1−header3 CFRs can be used for additional channels. NO Isochronous header is supplied by the external device on the DM interface. The header0 CFR is automatically written with the isochronous header extracted from the transmitted packet.
Internal Registers BIT NUMBER BIT NAME FUNCTION DIR DESCRIPTION 13 BYTEMODE Byte mode R/W Byte mode. When this bit is set the DM port only looks at DM0−DM7. DM8−DM15 are ignored for transmit and are not driven on receive. In this mode, the maximum speed supported on the 1394 bus is 200 Mbps. 14 HANDSHK Handshake mode (GPLynx mode) R/W Handshake. When this bit is set, DMREADY and DMDONE are in strict handshake mode (i.e., TSB12LV31 compatible mode).
Internal Registers 2.2.3 Control Register at 08h IRP2EN IRP1EN SID ERROR CODE CMAUTO CYTEN CLSIDER CYSRC CYMAS FIFOACKCOMP BDIV1 DMACKCOMP BDIV0 BUSNRST CTNDRISIN CTNDRSTAT RSTTX RSTRX ENA_INSERT_IDLE ENA_ACCEL ENA_CONCAT TXEN RXEN BSYCTRL PHY_PKT_ENA RXSID FULLSID FLSHERR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 The control register dictates the basic operation of the TSB12LV32.
Internal Registers BIT NUMBER BIT NAME FUNCTION DIR DESCRIPTION 15 BUSNRST Bus number reset enable R/W When this enable is set high, the bus number field in the bus reset CFR at 34h clears to 3FFh when a local 1394 bus reset is received. 16−17 BDIV0, BDIV1 BCLK divisor encode bits R/W BCLK divisor encode bits. Used to divide down the BCLK to generate the link power status (LPS) clock to the Phy. BDIV0 BDIV1 DESCRIPTION 0 0 Divide by 16. Default power-on value.
Internal Registers 2.2.
Internal Registers BIT NUMBER BIT NAME FUNCTION DIR DESCRIPTION 14 SNTRJ Busy acknowledge sent by receiver R/W When SNTRJ is set, the receiver is forced to send a busy acknowledge to any packet addressed to this node because the GRF overflowed. 15 HDRERR Header error R/W When HDRERR is set, the receiver detected a header CRC error on an incoming packet that may have been addressed to this node. Any packet with a CRC error is discarded.
Internal Registers 2.2.6 Isochronous Port Register at 18h ISYNCRCVN MONTAG IRPORT2 IRCVALL IRPORT1 TAG2 TAG1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 The power-up reset value of this register equals 0000 0000h. BIT NUMBER BIT NAME FUNCTION DIR DESCRIPTION 0−1 TAG1 Tag field 1 R/W The TAG1 field can further qualify the isochronous reception for isochronous receive PORT1 when the MONTAG bit is set.
Internal Registers 2.2.7 Maint_Control Register at 1Ch F_ACK NO_ACK NO_PKT E_DCRC E_HCRC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ACK PING VALUE This register is used to generate test conditions. The control bits in this register allow errors to be inserted into various places in the packets generated by this node. After the completion of error insertion, enabled error-insertion controls are disabled.
Internal Registers 3 4 5 6 B1_BUSY B2_BUSY B3_BUSY B0_PND B1_PND B2_PND 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 REGRW 2 B3_PND 1 RAMTEST 0 B0_BUSY 2.2.8 Diagnostic Register at 20h STATESEL0 STATESEL1 STATESEL2 The power-up reset value of this register equals 0000 4AD0h. BIT NUMBER BIT NAME FUNCTION DIR DESCRIPTION 0 B0_BUSY Byte 0 busy R Byte 0 busy. When this bit is set, no microcontroller write to byte 0 of any CFRs is allowed.
Internal Registers 2.2.9 Phy Access Register at 24h RDPHY WRPHY 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 PHYRGAD PHYRGDATA PHYRXAD PHYRXDATA The Phy access register allows access to the registers in the attached 1394 Phy. The most-significant 16 bits send read and write requests to the Phy registers. The least-significant 16 bits are for the Phy to respond to a read request sent by the TSB12LV32.
Internal Registers 2.2.11 FIFO Status Register at 30h CD GRFEMPTY ATFAVAIL GRFCLR ATFFULL ATFCLR ATFWBMTY 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ATACK GRFUSED The power-up reset value of this register equals 6083 0000h. BIT NUMBER 18 BIT NAME FUNCTION DIR DESCRIPTION 0 ATFCLR ATF clear R/W ATF clear. When this bit is set to 1, the ATF is cleared. This bit clears itself. 1 ATFWBMTY ATF write buffer empty R ATF write buffer empty.
Internal Registers 2.2.12 Bus Reset Register at 34h ROOT NODECNT CONTENDER NRIDVAL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 IRMNODEID BUS NUMBER NODE NUMBER The power-up reset value of this register equals 81BF FFC0h. NOTE: The power-up reset value shown above assumes one node on the bus only. A 1394a-2000 compliant Phy is assumed to be attached to the TSB12LV32. If a 1394-1995 Phy is attached to the TSB12LV32 link, the NODECNT filed is 0.
Internal Registers ASYNCHRONOUS HEADER FOR QUADLET 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SPEED BIT NUMBER BIT NAME FUNCTION DIR TLABEL RT TCODE PRIORITY DESCRIPTION 0−13 RESERVED 14−15 SPEED Speed R/W Speed at which the Phy is to transmit the packet: 00 => S100 01 => S200 10 => S400 16−21 TLABEL Transaction label R/W Transaction label 22−23 RT Retry code R/W The retry code specifies whether this packet is a retry attempt and the ret
Internal Registers 2.2.15 Header2 Register at 40h Header2 register contains the isochronous packet header (if multiple channels are supported) or the third quadlet of an asynchronous packet header if the deivce is in automatic-header-insert transmit mode. If the device is not in automatic-header-insert transmit mode or if it is in receive mode, this register is updated with the third quadlet of the asynchronous received header or the DM-supplied transmit header.
Internal Registers 2.2.16 Header3 Register at 44h Header3 register contains the isochronous packet header (if multiple channels are supported) or the fourth quadlet of an asynchronous packet header if the device is in automatic-header-insert transmit mode. If the device is not in automatic-header-insert mode or if it is in receive mode, this register is updated with the fourth quadlet of the asynchronous received header or DM-supplied transmit header. This register powers up with all bits reset to 0.
Internal Registers 2.2.17 Trailer Register at 48h ACKCODE SPD LPS_OFF NUMBER OF QUADLETS LPS_RESET 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 The power-up reset value of this register equals 0000 0000h.
Internal Registers 2.2.18 Asynchronous Retry Register at 4Ch 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ASYNC RETRY COUNT RETRY INTERVAL The TSB12LV32 only supports single-phase retry protocol and does not implement dual-phase retry protocol. See Section 7.3.5 of the IEEE Std 1394-1995 (IEEE standard for a high-performance serial bus) for more information on retry protocol. The power-up reset value of this register equals 0000 0000h.
Microcontroller Interface 3 Microcontroller Interface The microcontroller interface allows the local microcontroller/microprocessor to communicate with the internal control and configuration registers (CFR), asynchronous transfer FIFO (ATF) and general receive FIFO (GRF). All microcontroller reads/writes are initiated by the microcontroller. The microcontroller interface supports read transactions from the CFR or GRF, and write transactions to the CFR or ATF.
Microcontroller Interface • The requested data transfer size is unsupported. − − − − − • ColdFire error − 3.1 An ATF burst access ends on a nonquadlet boundary. A microcontroller address is not on a word boundary whil in 16-bid data-bus mode. The microcontroller attempts to write to the CFR across quadlet boundaries. A GRF read-byte address does not start from 00h. GRF read is not done on a quadlet boundary. MCS is asserted for more than one BCLK cycle for each transaction.
Microcontroller Interface 3.2 Microcontroller Byte Unstack (Read) Operation The microcontroller byte unstack (read) protocol is shown in Figure 3−2. TSB12LV32 Read Yes No Microcontroller Reads Same Quadlet As Before Yes Microcontroller Reads Same Byte/Doublet As Before Yes TSB12LV32 Provides Updated Byte/Doublet Data No TSB12LV32 Provides Updated Byte/Doublet Data No TSB12LV32 Provides Held Byte/Doublet Data Figure 3−2. Microcontroller Byte Unstack (Read) Operation 3.
Microcontroller Interface BCLK MWR MCS MCA MA[0:6] A0 A1 A2 A3 MD[0:7] MD[8:15] D0 D1 D2 D3 M8BIT/SIZ0 MCMODE/SIZ1 COLDFIRE Figure 3−3. Byte Handshake Read Figure 3−4 shows a word handshake read transaction. In this case, all 16 bits of the MD lines are used. Note that MD[0] contains the MSB and MD[15] contains the LSB. As in the byte read case, after MCA is asserted high another read or write transaction can begin after the next rising edge of BCLK.
Microcontroller Interface Byte handshake write and word handshake write are shown in Figure 3−5 and Figure 3−6. In this case, the microcontroller interface asserts MCA low immediately after MCS is sampled low. The data on the MD bus is valid when MCS and MWR are both low. The microcontroller interface keeps MCA low until it samples MCS high. For 8-bit accesses, the MD[0:7] lines are not used. If a transfer error condition occurs, TEA is asserted low for one BCLK cycle.
Microcontroller Interface BCLK MWR MCS MCA MA[0:6] A0 A1 A2 A3 MD[0:7] D0 D2 D4 D6 MD[8:15] D1 D3 D5 D7 M8BIT/SIZ0 MCMODE/SIZ1 COLDFIRE Figure 3−6. Word Handshake Write 3.3.2 Microcontroller Fixed-Timing Mode Byte fixed-timing reads and word fixed-timing reads are shown in Figure 3−7 and Figure 3−8, respectively. In addition to single byte or single word transfers, fixed-timing mode supports burst transfers. If MCS is asserted low for more than one BCLK cycle, burst mode is enabled.
Microcontroller Interface BCLK MWR MCS MCA MA[0:6] A0 A1 A2 MD[0:7] MD[8:15] D0 D1 D2 D3 D4 D5 D6 D7 D8 M8BIT/SIZ0 MCMODE/SIZ1 COLDFIRE Figure 3−7. Byte Fixed-Timing Read BCLK MWR MCS MCA MA[0:6] A0 A1 A2 MD[0:7] D0 D2 D4 D6 D8 D10 D12 D14 D16 MD[8:15] D1 D3 D5 D7 D9 D11 D13 D15 D17 M8BIT/SIZ0 MCMODE/SIZ1 COLDFIRE Figure 3−8.
Microcontroller Interface Byte fixed-timing write and word fixed-timing write are shown in Figure 3−9 and Figure 3−10, respectively. Unlike the fixed-timing read transfers, no extra wait cycles are required for fixed-timing write transfers. For an 8-bit data bus, MD[0:7] is not used (don’t care) and is driven with zeros. If the write transaction is accessing a CFR register, it cannot cross any register boundary. The first write data for each ATF quadlet must start at byte0.
Microcontroller Interface BCLK MWR MCS MCA MA[0:6] A0 A1 MD[0:7] D0 D2 D4 D6 D8 D10 D12 D14 D16 D18 D20 D22 D24 MD[8:15] D1 D3 D5 D7 D9 D11 D13 D15 D17 D19 D21 D23 D25 A2 M8BIT/SIZ0 MCMODE/SIZ1 COLDFIRE Figure 3−10. Word Fixed-Timing Write 3.3.2.1 GRF READ in Fixed-Timing Mode The timing requirements when performing a GRF read access in fixed-timing mode are different from timing requirements of a CFR read access in the fixed-timing mode.
Microcontroller Interface BCLK MWR MCS MCA MA[0:6] A0 A1 MD[0:7] MD[8:15] D0 D1 D2 D3 D4 D5 D6 D7 M8BIT/SIZ0 MCMODE/SIZ1 COLDFIRE Figure 3−11. GRF Read Access (Byte Fixed-Timing Mode) BCLK MWR MCS MCA MA[0:6] A0 A1 MD[0:7] D0 D2 D4 D6 MD[8:15] D1 D3 D5 D7 M8BIT/SIZ0 MCMODE/SIZ1 COLDFIRE Figure 3−12.
Microcontroller Interface 3.3.3 Microcontroller ColdFire Mode The TSB12LV32 supports a glueless interface to the ColdFire family of microcontrollers. To enable this mode, the COLDFIRE pin must be asserted and kept high for the entire access cycle. The timing diagram for a ColdFire read operation is shown in Figure 3−13. The timing sequence for a ColdFire read access can be summarized as follows: 1. The ColdFire pulses MCS low for one BCLK cycle to signal the start of access.
Microcontroller Interface BCLK MWR MCS MCA MA[0:6] A1 A2 A3 MD[0:7] D1 D3 D5 MD[8:15] D2 D4 D6 M8BIT/SIZ0 MCMODE/SIZ1 COLDFIRE TEA Figure 3−13. ColdFire Read The ColdFire write transaction is shown in Figure 3−14. Unlike the handshake and fixed-timing write modes, the ColdFire write operation requires the data on the MD lines be available one BCLK cycle after the address on the MA lines is sampled.
Microcontroller Interface BCLK MWR MCS MCA MA[0:6] A1 A2 A3 MD[0:7] D1 D3 D5 MD[8:15] D2 D4 D6 M8BIT/SIZ0 MCMODE/SIZ1 COLDFIRE TEA Figure 3−14. ColdFire Write 3.3.4 Microcontroller Critical Timing tsu4 tsu3 th4 tsu2 tsu1 th3 th1 th0 tsu0 tsu5 th2 th5 BCLK MWR MCS td0 MCA MA[0:6] XX ADDRESS XX ADDRESS XX td2 MD[0:15] DATA XXXX XXXX DATA XXXX td1 TEA M8BIT/SIZ0 MCMODE/SIZ1 Figure 3−15.
Microcontroller Interface Table 3−3. Microcontroller Timing PARAMETER† td0 td1 TERMINAL NAME ACCESS TYPE MIN MAX MCA Read/Write 3.75 9.5 TEA Read/Write 3.75 9.5 td2 tsu0 MD[0:15] Read 2.5 10.5 MWR Read/Write 4.5 tsu1 tsu2 MCS Read/Write 6.5 MA[0:6] Read/Write 6.5 M8BIT/SIZ0 Read/Write 5 MCMODE/SIZ1 Read/Write 3.5 tsu5 th0 MD[0:15] Write MWR Read/Write 1.75 th1 th2 MCS Read/Write 1.5 MA[0:6] Read/Write 2 M8BIT/SIZ0 Read/Write 1.5 MCMODE/SIZ1 Read/Write 1.
Microcontroller Interface Table 3−4.
Microcontroller Interface Byte 3 (MSByte) Byte 2 Byte 1 Byte 0 (LSByte) Little Endian Processor Memory aa bb cc dd TSB12LV32 CFR/Memory dd cc bb aa (MSByte) Byte 0 Byte 1 Byte 2 (LSByte) Byte 3 Figure 3−19.
Link Core 4 Link Core This section describes the link core components and operations. Figure 4−1 shows the link core components. Transmitter Cycle Timer CRC Physical Interface Cycle Monitor Receiver Figure 4−1. Link Core Components 4.1 Physical Interface The physical (Phy) interface provides Phy-level services to the transmitter and receiver. This includes gaining access to the serial bus, sending packets, receiving packets, and sending and receiving acknowledge packets.
Link Core 4.4 Cycle Timer The cycle timer is only used by nodes that support isochronous data transfer. The cycle timer is a 32-bit cycle-timer register. Each node with isochronous data-transfer capability has a cycle-timer register as defined by the IEEE 1394-1995 specification. In the TSB12LV32, the cycle-timer register is implemented in the cycle timer located in the IEEE 1212 initial register space at location 200h and can also be accessed through the local bus at TSB12LV32 CFR address 14h.
Link Core Table 4−1.
Link Core 44 TSB12LV32-EP SGLS139B − October 2003 − Revised April 2004
Data-Mover Port Interface 5 Data-Mover Port Interface The data-mover (DM) port in the TSB12LV32 is the physical medium by which autonomous data streams of different types are piped to/from an application that uses the TSB12LV32. The DM port is meant to support an external memory interface that supplies or accepts large data packets.
Data-Mover Port Interface Isochronous DM Idle (DMDONE Is High) DMEN Is 1, DMASYNC Is 0 DMREADY Is High? No Yes No Isochronous DM Go (DMDONE Is Low) New Isochronous Cycle Started? Yes Isochronous Arbitrate/Xmit (DMDONE Is Low) Arbitrate for Isochronous Transmit and Send One Isochronous Packet All Channels Done (DMDONE Is Low) End of All Channels? No Yes Data Block Done (DMDONE Is Low) End of All Packets for This Data Block? No Yes Handshake Mode? No Yes No Handshake (DMDONE Is High) DMREADY I
Data-Mover Port Interface Asynchronous DM Idle (DMDONE Is High) DMEN is 1, DMASYNC is 0 DMREADY Is High? No Yes Asynchronous Arbitrate/Xmit (DMDONE Is Low) Arbitrate for Asynchronous Transmit and Send Asynchronous Packet Wait for Acknowledge No Ack Complete received? DM Disabled Re-enable via Software Yes No Data Block Done (DMDONE Is Low) End of All Packets for This Data Block? Yes Figure 5−4. Asynchronous Transmit DM Flow Control (TSB12LV32 Transmit to 1394 Bus) (DMASYNC = 1) 5.
Data-Mover Port Interface 5.1.1.1 Isochronous Packet Receive With Automatic Header and Trailer Removal Step 1: Isochronous packet is received through the receiver logic of the link core. Step 2: The packet header is stripped off from the packet and loaded into the header0 register at 38h. Step 3: Packet data (payload only) is routed directly to the DM port without any buffering. Step 4: Trailer quadlet is loaded into the trailer register at 48h.
Data-Mover Port Interface 5.1.2 Isochronous Transmit There are two ways (modes of operation) to transmit isochronous data through the data mover: • Isochronous packet transmit with automatic header insertion. • Isochronous packet transmit without automatic header insertion. The difference between the two modes lies in the mechanism with which the header information is inserted into the data stream.
Data-Mover Port Interface 5.1.2.2 Isochronous Packet Transmit Without Automatic Header Insertion In this mode, both the packet header and data payload is loaded through the data-mover port. This mode is sometimes called isochronous packet transmit with manual header insertion. This is because the header quadlet is not preloaded into the header0 register via the microcontroller interface. Instead, it is inserted manually into the data stream at the same time as the rest of the packet.
Data-Mover Port Interface 5.1.3 Asynchronous Receive In both the asynchronous receive modes, the packet header information is always loaded into the header registers in the CFR. In quadlet receive mode, the first three header quadlets are loaded into the header0 register at 38h, header1 register at 3Ch, and header2 register at 40h, respectively. In block receive mode, an additional step is performed, loading the fourth header quadlet received into the header3 register at 44h.
Data-Mover Port Interface 5.1.3.2 Asynchronous Packet Receive With Headers and Trailer Step 1: Asynchronous packet is received through the receiver logic of the link core. Step 2: The header quadlets are loaded into their respective header registers and routed to the DM port without any buffering. Step 3: Packet data is routed directly to the DM port (no buffering performed). Step 4: Trailer quadlet is loaded into the trailer register at 48h and routed to the DM port.
Data-Mover Port Interface 5.1.4.1 Asynchronous Packet Transmit With Automatic Header Insertion In this mode, the header information is first loaded into the header0−header3 registers through the microcontroller interface. The headers subsequently are inserted automatically into the data once the data mover starts streaming data through to the link core transmitter logic. The following steps further illustrate the process.
Data-Mover Port Interface 5.1.4.2 Asynchronous Packet Transmit Without Automatic Header Insertion In this mode, the packet headers and data information are loaded through the data-mover port. This mode is sometimes called asynchronous packet transmit with manual header insertion. This is because the header quadlets are not preloaded into the header registers via the microcontroller interface. Instead, they are inserted manually into the data stream at the same time as the rest of the packet.
Data-Mover Port Interface Table 5−1.
Data-Mover Port Interface DMCLK DMRW DMD[0:15] DMREADY DMPRE DMDONE Figure 5−15. Isochronous Transmit With Auto Header Insertion at 100 Mbps 5.2.2 Isochronous Transmit Without Automatic Header Insertion Upon receiving a high on DMREADY, the following sequence of operations is performed. Step 1: DMDONE is driven low (deactivated) at the next DMCLK cycle. Step 2: DMPRE pulses for one DMCLK cycle before the first header quadlet is is accepted from lthe external device.
Data-Mover Port Interface 5.2.3 Isochronous Packet Receive With Automatic Header and Trailer Removal In this mode, when the link receives an isochronous packet that is addressed to it, the following sequence of operations is performed. Step 1: The packet router control logic routes the packet to the data mover. If the sync bit field in the header quadlet matches a bit pattern in the ISYNCRCVN field of the isochronous port register at 18h, DMPRE is asserted high for one DMCLK cycle.
Data-Mover Port Interface 5.2.4 Isochronous Packet Receive With Header and Trailer In this mode, when the link receives an isochronous packet that is addressed to it, the following sequence of operations is performed. Step 1: The packet router control logic routes the packet to the data mover. If the sync bit field in the header quadlet matches a bit pattern in the ISYNCRCVN field of the isochronous port register at 18h, DMPRE is asserted high for one DMCLK cycle.
Data-Mover Port Interface 5.2.5 Asynchronous Packet Transmit With Automatic Header Insertion Upon receiving a high signal on DMREADY from the external logic, the following sequence of operations is performed. Step 1: DMDONE is asserted low (deactivated) at the next DMCLK cycle. Step 2: The data mover takes the headers that have been loaded into the header0−header3 registers and requests the link core to transmit the data onto the 1394 bus.
Data-Mover Port Interface 5.2.6 Asynchronous Packet Transmit Without Automatic Header Insertion Upon receiving a high signal on DMREADY from the external logic, the following sequence of operations is performed. Step 1: DMDONE is asserted low (deactivated) at the next DMCLK cycle. Step 2: DMPRE pulses for one DMCLK cycle before the header quadlets are accepted from the external device on the DM port. Step 3: The data mover fetches the headers by asserting DMRW high.
Data-Mover Port Interface 5.2.7 Asynchronous Packet Receive With Headers and Trailer In this mode, when the link receives an asynchronous packet that is addressed to it, the following sequence of operations is performed. Step 1: The packet router control logic routes the packet to the data mover. At the same time, DMDONE is asserted high for one DMCLK cycle. Step 2: This is followed by DMRW asserted high as the packet comes through.
Data-Mover Port Interface 5.2.8 Asynchronous Packet Receive With Automatic Header and Trailer Removal In this mode, when the link receives an asynchronous packet that is addressed to it, the following sequence of operations is performed. Step 1: The packet router control logic routes the packet to the data mover. After the headers are sent through, DMDONE is asserted high for one DMCLK cycle. Step 2: DMRW is then asserted high as the data payload comes through.
Data-Mover Port Interface 5.5 Data-Mover Handshake Mode In this mode, when DMDONE is asserted high the data-mover port interface checks for DMREADY low as an acknowledge. This is equivalent to the mode used in the TSB12LV31 (GPLynx), as shown in Figure 5−31. DMCLK DMRW DMD[0:15] DMREADY DMPRE DMDONE Figure 5−31. Data-Mover Handshake Mode (GPLynx Mode) 5.
Data-Mover Port Interface 64 TSB12LV32-EP SGLS139B − October 2003 − Revised April 2004
FIFO Memory Access 6 FIFO Memory Access The TSB12LV32 FIFO interfaces with the microcontroller, the CFR and the 1394 link layer controller (LLC). The FIFO is separated into an asynchronous transmit FIFO (ATF) and a general receive FIFO (GRF), each of 520 quadlets (2K bytes). The FIFO provides storage for transmit packets (ATF) and receive packets (GRF). When an asynchronous packet is confirmed into the ATF, the transmitter of the LLC requests the 1394 bus to send the asynchronous packet.
FIFO Memory Access Each quadlet can be written into the ATF register on a byte (8-bit) boundary or word (16-bit) boundary. To write to the ATF in a byte fashion, the following steps should be followed. Step 1: Writing the first quadlet of the packet: a) Write the first 8 bits of the quadlet to ATF location 50h. b) Write the second 8 bits of the quadlet to ATF location 51h. c) Write the third 8 bits of the quadlet to ATF location 52h. d) Write the fourth 8 bits of the quadlet to ATF location 53h.
FIFO Memory Access To perform a burst write operation, the microcontroller must continually drive MCS low. The TSB12LV32 loads MD0–MD15 to the ATF during each rising edge of BCLK while MCS is low. At the same time it asserts MCA (MCA is always one cycle behind MCS) low. The ATF_First_Update address location is optimized for transmitting zero-length isochronous packets or asynchronous stream packets. A zero-length packet contains no data payload and only the packet header and header CRC are transmitted. 6.
FIFO Memory Access 68 TSB12LV32-EP SGLS139B − October 2003 − Revised April 2004
TSB12LV32 Data Formats 7 TSB12LV32 Data Formats The data formats for transmission and reception of data are shown in the following sections. The transmit format describes the expected organization of data presented to the TSB12LV32 at the data-mover port or the microcontroller interface. The receive formats describe the data format that the TSB12LV32 presents to the data-mover port or the microcontroller interface. 7.
TSB12LV32 Data Formats Table 7−1. Quadlet Transmit Format Functions FIELD NAME DESCRIPTION spd The Spd field indicates the speed at which the current packet is to be sent. 00 = 100 Mbps, 01 = 200 Mbps, 10 = 400 Mbps, and 11 is undefined for this implementation. tLabel The tLabel field is the transaction label, which is a unique tag for each outstanding transaction between two nodes. This field is used to pair up a response packet with its corresponding request packet.
TSB12LV32 Data Formats Table 7−2. Block Transmit Format Functions FIELD NAME DESCRIPTION spd The Spd field indicates the speed at which the current packet is to be sent. 00 = 100 Mbps, 01 = 200 Mbps, and 10 = 400 Mbps, and 11 is undefined for this implementation. tLabel The tLabel field is the transaction label, which is a unique tag for each outstanding transaction between two nodes. This field is used to pair up a response packet with its corresponding request packet.
TSB12LV32 Data Formats 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 destinationID tLabel sourceID rt tCode priority destination OffsetHigh destination OffsetLow quadlet data (write requests and read responses only, omitted for write responses and read requests) 0 0 numofQuadlets 0 0 0 ackCode 0 0 spd 0 0 0 0 Figure 7−4. Data-Mover Quadlet-Receive Format Table 7−3.
TSB12LV32 Data Formats 7.1.4 Block Receive The block receive format through the GRF is shown in Figure 7−5 and is described in Table 7−4. The first packet contains packet reception status that is added by the TSB12LV32. The first 16 bits of the second quadlet contain the node and bus ID of the destination node, and the last 16 bits contain packet control information.
TSB12LV32 Data Formats Table 7−4. Block Receive Format Functions FIELD NAME DESCRIPTION numofQuadlets Total number of quadlets in the current packet (payload and header quadlets only) ackCode This 5-bit field holds the acknowledge code sent by the receiver for the current packet. destinationID The destinationID field is the concatenation of the 10-bit bus number and the 6-bit node number that forms the node address to which the current packet is being sent.
TSB12LV32 Data Formats Table 7−5. Isochronous Transmit Functions FIELD NAME DESCRIPTION dataLength The dataLength field indicates the number of bytes in the current packet. TAG The TAG field indicates the format of data carried by the isochronous packet (00 = formatted, 01−11 are reserved). chanNum The chanNum field carries the channel number with which the current data is associated. tCode The transaction code for the current packet (tCode = Ah).
TSB12LV32 Data Formats 7.3 Phy Configuration The format of the Phy configuration packet is shown in Figure 7−10 and is described in Table 7−7. The Phy configuration packet transmit contains two quadlets, which are loaded into the ATF. The first quadlet is written to address 50h. The second quadlet is written to address 58h. The 00E0h in the first quadlet (bits 16−31) tells the TSB12LV32 that this quadlet is the Phy configuration packet.
TSB12LV32 Data Formats 7.3.1 Extended Phy Packets 7.3.1.1 Ping Packets The reception of a Phy ping packet causes the node identified by Phy_ID to transmit Self-ID packet(s) that reflect the current configuration and status of the Phy. The ping packet provides a method of measuring the round-trip delay of packets between two nodes on the bus that are farthest from one another in terms of cable hops. The format of this packet is shown in Figure 7−12 and described in Table 7−9.
TSB12LV32 Data Formats 7.3.1.3 Remote Command Packets The remote command packet provides a method for one node to issue a number of Phy-specific commands to the selected port within the target Phy. The reception of a remote command packet requests the node identified by the Phy_ID field to perform the operation specified in the cmnd field and subsequently return a remote confirmation packet. The format of this packet is shown in Figure 7−14 and described in Table 7−11.
TSB12LV32 Data Formats 7.4 Receive Self-ID Packet Based on the settings of the RXSID and FULLSID bits in the control register at 08h, the self-ID packets can be either ignored or received into the GRF. See Table 7−13. Table 7−13. GRF Receive Self-ID Setup Using Control Register Bits (RXSID and FULLSID) RXSID (bit 1) FULLSID (bit 2) 0 X Self-ID packets are not received by the link. 1 0 Only the data quadlet (first quadlet) of the self-ID packets is received into the GRF.
TSB12LV32 Data Formats The cable Phy sends one to three self-ID packets at the base rate (100 Mbps) during the self-ID phase of arbitration or in response to a ping packet. The number of self-ID packets sent depends on the number of ports. Figure 7−18, Figure 7−19, and Figure 7−20 show the format of the cable Phy self-ID packets. Inside the GRF, the first received quadlet of a self-ID packet is always the header quadlet shown first in Figure 7−17 or Figure 7−18.
TSB12LV32 Data Formats Table 7−15. Phy Self-ID Packet Fields FIELD NAME DESCRIPTION 10 The 10 field is the self-ID packet identifier. L If set, this node has an active link and transaction layers. gap_cnt The gap_cnt field contains the current value for the current node PHY_CONFIGURATION.gap_count field. sp The sp field contains the Phy speed capability. The code is: 00 98.304 Mbps 01 98.304 Mbps and 196.608 Mbps 10 98.304 Mbps, 196.608 Mbps, and 393.
TSB12LV32 Data Formats 82 TSB12LV32-EP SGLS139B − October 2003 − Revised April 2004
TSB12LV32/Phy Interface 8 TSB12LV32/Phy Interface This section provides an overview of the digital interface between a TSB12LV32 and a physical layer device (Phy). The information that follows can be used as a guide through the process of connecting the TSB12LV32 to a 1394 Phy. The part numbers referenced, the TSB41LV03A and the TSB12LV32, represent the Texas Instruments implementation of the Phy (TSB41LV03A) and link (TSB12LV32) layers of the IEEE 1394-1995 and 1394a-2000 standards.
TSB12LV32/Phy Interface The LREQ terminal is controlled by the TSB12LV32 to send serial service requests to the Phy in order to request access to the serial bus for packet transmission, read or write Phy registers, or control arbitration acceleration. The LPS and LINKON terminals are used for power management of the Phy and TSB12LV32. The LPS terminal indicates the power status of the TSB12LV32, and can be used to reset the Phy-LLC interface or to disable SYSCLK.
TSB12LV32/Phy Interface Table 8−3. Request Stream Bit Length REQUEST TYPE NUMBER OF BITS Bus request 7 or 8 Read register request 9 Write register request 17 Acceleration control request 6 Regardless of the type of request, a start bit of 1 is required at the beginning of the stream, and a stop bit of 0 is required at the end of the stream. The second through fourth bits of the request stream indicate the type of the request.
TSB12LV32/Phy Interface For a write register request the length of the LREQ bit stream is 17 bits as shown in Table 8−8. Table 8−8.
TSB12LV32/Phy Interface The arbitration acceleration enhancements can interfere with the ability of the cycle master node to transmit the cycle start message under certain circumstances. The acceleration control request is therefore provided to allow the TSB12LV32 to temporarily enable or disable the arbitration acceleration enhancements of the TSB41LV03A during the asynchronous period.
TSB12LV32/Phy Interface The sequence of events for a status transfer is as follows: 8.4 • Status transfer initiated. The Phy indicates a status transfer by asserting status on the CTL lines along with the status data on the D0 and D1 lines (only 2 bits of status are transferred per cycle). Normally (unless interrupted by a receive operation), a status transfer is either 2 or 8 cycles long. A 2-cycle (4-bit) transfer occurs when only status information is to be sent.
TSB12LV32/Phy Interface • Receive data. Following the data-on indication (if any) and the speed-code, the Phy asserts packet data on the D lines with receive on the CTL lines for the remainder of the receive operation. • Receive operation terminated. The Phy terminates the receive operation by asserting idle on the CTL lines. The Phy asserts at least one cycle of idle following a receive operation.
TSB12LV32/Phy Interface The hold state asserted at the end of packet transmission indicates to the Phy that the TSB12LV32 requests to send another packet (concatenated packet) without releasing the serial bus. The Phy responds to this concatenation request by waiting the required minimum packet separation time and then asserting grant as before. This function can be used to send a unified response after sending an acknowledge, or to send consecutive isochronous packets during a single isochronous period.
TSB12LV32/Phy Interface 8.6 TSB12LV32/Phy Interface Critical Timing tsu1 tsu2 th1 th3 tsu0 th2 tsu3 th0 SCLK td0 LREQ CYCLEIN CONTNDR td1 CTL[0:1] X CONTROL X CONTROL td2 D[0:7] XX DATA XX DATA Figure 8−7. Critical Timing for the TSB12LV32/Phy Interface Table 8−12. TSB12LV32/Phy Interface Timing PARAMETER† td0 td1 Delay time (SCLK to Q) TERMINAL NAME MIN MAX UNIT LREQ 3 9.5 ns CTL[0:1] 3 9.5 ns 3.
TSB12LV32/Phy Interface 92 TSB12LV32-EP SGLS139B − October 2003 − Revised April 2004
Electrical Characteristics 9 Electrical Characteristics 9.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range (Unless Otherwise Noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.6 V Supply voltage range, VCC5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 5.5 V Input voltage range, VI . . . . . . . . . . . .
Electrical Characteristics 9.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature (Unless Otherwise Noted) PARAMETER VOH VOL High-level output voltage IIL IIH Low-level input current Low-level output voltage High-level input current TEST CONDITIONS IOH = − 8 mA IOL = 8 mA TSB12LV32-EP TYP† MAX VCC−0.
Mechanical Information 10 Mechanical Information The TSB12LV32 is packaged in a high-performance 100-pin PZ package. The following shows the mechanical dimensions of the PZ package.
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