Datasheet

Internal Registers
24
SGLS139B − October 2003 − Revised April 2004TSB12LV32-EP
2.2.18 Asynchronous Retry Register at 4Ch
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 29 30 3128
ASYNC RETRY COUNT
RETRY INTERVAL
The TSB12LV32 only supports single-phase retry protocol and does not implement dual-phase retry protocol.
See Section 7.3.5 of the IEEE Std 1394-1995 (IEEE standard for a high-performance serial bus) for more
information on retry protocol. The power-up reset value of this register equals 0000 0000h.
BIT
NUMBER
BIT NAME FUNCTION DIR DESCRIPTION
0−7 ASYNC RETRY
COUNT
Retry count R/W The asynchronous retry count field specifies the number of times to automatically retry
sending asynchronous packets from the ATF before giving up. After the retry count is
exhausted the FIFOACK interrupt in the interrupt CFR at 0Ch is generated when an
ACK_BUSY_X is received.
8−15 RETRY
INTERVAL
Retry inter-
val
R/W Asynchronous retry interval is the time in increments of isochronous cycles between
asynchronous retries.
16−31 RESERVED Reserved