Datasheet

Data-Mover Port Interface
51
SGLS139B − October 2003 − Revised April 2004 TSB12LV32-EP
5.1.3 Asynchronous Receive
In both the asynchronous receive modes, the packet header information is always loaded into the header
registers in the CFR. In quadlet receive mode, the first three header quadlets are loaded into the header0
register at 38h, header1 register at 3Ch, and header2 register at 40h, respectively. In block receive mode, an
additional step is performed, loading the fourth header quadlet received into the header3 register at 44h. The
trailer quadlet always is loaded into the trailer register at 48h.
5.1.3.1 Asynchronous Packet Receive With Automatic Header and Trailer Removal
Step 1: Asynchronous packet is received through the receiver logic of the link core
Step 2: The packet headers are stripped from the packet and loaded into the header registers:
a) If in quadlet receive mode, the three header quadlets are loaded into the header0−header2
registers.
b) If in block receive mode, the four header quadlets are loaded into the header0−header3 registers.
Step 3: Packet data (payload only) is routed directly to the DM port without any buffering.
Step 4: Trailer quadlet is loaded into the trailer register at 48h.
CFR REGISTER
Step 1
Data-
Mover
Port
Header0 Register at 38h
Trailer Register at 48h
LINK CORE
Transmitter
Receiver
Quadlet#0
Step 4
Packet Received From
1394 Bus Through the Phy
Step 3 (Packet Data)
Header1 Register at 3Ch
Quadlet#1
Header2 Register at 40h
Quadlet#2
Header3 Register at 42h
Quadlet#3
Step 2
Loaded Only in
Block Receive
Figure 5−9. Asynchronous Receive Without Header and Trailer Removal